Cleanup MMU code to do book required sync. Update exception handler to clear fault...

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10366 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Drivers/CpuDxe/ExceptionSupport.ARMv6.S b/ArmPkg/Drivers/CpuDxe/ExceptionSupport.ARMv6.S
index 646aca76a405de2c413cfc76bc9a09b2d7583aea..bf9a4d4b76bf71d460c93a8350441730275133a8 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/ExceptionSupport.ARMv6.S
+++ b/ArmPkg/Drivers/CpuDxe/ExceptionSupport.ARMv6.S
@@ -256,6 +256,12 @@ CommonCExceptionHandler (
 
 */  
   blx       ASM_PFX(CommonCExceptionHandler)  @ Call exception handler
 
 */  
   blx       ASM_PFX(CommonCExceptionHandler)  @ Call exception handler

+
+  ldr       R1, [SP, #0x4c]         @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
+  mcr       p15, 0, R1, c5, c0, 1   @ Write IFSR
+
+  ldr       R1, [SP, #0x44]         @ sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR
+  mcr       p15, 0, R1, c5, c0, 0   @ Write DFSR

   
   ldr       R1,[SP,#0x3c]           @ EFI_SYSTEM_CONTEXT_ARM.PC
   str       R1,[SP,#0x58]           @ Store it back to srsfd stack slot so it can be restored 
   
   ldr       R1,[SP,#0x3c]           @ EFI_SYSTEM_CONTEXT_ARM.PC
   str       R1,[SP,#0x58]           @ Store it back to srsfd stack slot so it can be restored 

diff --git a/ArmPkg/Drivers/CpuDxe/ExceptionSupport.ARMv6.asm b/ArmPkg/Drivers/CpuDxe/ExceptionSupport.ARMv6.asm
index 3bcca4d6aa69af76e10274965ab4dfb9d52c21cf..b45f6682a1449598e82928b18fa29fa4ac8547bd 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/ExceptionSupport.ARMv6.asm
+++ b/ArmPkg/Drivers/CpuDxe/ExceptionSupport.ARMv6.asm
@@ -254,6 +254,12 @@ CommonCExceptionHandler (
 */
   blx       CommonCExceptionHandler ; Call exception handler
   
 */
   blx       CommonCExceptionHandler ; Call exception handler
   

+  ldr       R1, [SP, #0x4c]         ; Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
+  mcr       p15, 0, R1, c5, c0, 1   ; Write IFSR
+
+  ldr       R1, [SP, #0x44]         ; sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR
+  mcr       p15, 0, R1, c5, c0, 0   ; Write DFSR
+  

   ldr       R1,[SP,#0x3c]           ; EFI_SYSTEM_CONTEXT_ARM.PC
   str       R1,[SP,#0x58]           ; Store it back to srsfd stack slot so it can be restored 
 
   ldr       R1,[SP,#0x3c]           ; EFI_SYSTEM_CONTEXT_ARM.PC
   str       R1,[SP,#0x58]           ; Store it back to srsfd stack slot so it can be restored 
 

diff --git a/ArmPkg/Drivers/CpuDxe/Mmu.c b/ArmPkg/Drivers/CpuDxe/Mmu.c
index e81e58a9b113ec8a3d0c94feb8786619c16d3bf1..bcb66e5879a62b1c418421bb97862e965ba98fb0 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/Mmu.c
+++ b/ArmPkg/Drivers/CpuDxe/Mmu.c
@@ -105,7 +105,7 @@ typedef UINT32    ARM_PAGE_TABLE_ENTRY;
 #define ARM_PAGE_TYPE_SMALL           0x2\r
 #define ARM_PAGE_TYPE_SMALL_XN        0x3\r
 \r
 #define ARM_PAGE_TYPE_SMALL           0x2\r
 #define ARM_PAGE_TYPE_SMALL_XN        0x3\r
 \r

-#define SMALL_PAGE_TABLE_ENTRY_COUNT  (ARM_PAGE_DESC_ENTRY_MVA_SIZE / EFI_PAGE_SIZE)\r
+#define SMALL_PAGE_TABLE_ENTRY_COUNT  (ARM_PAGE_DESC_ENTRY_MVA_SIZE / SIZE_4KB)\r

 \r
 \r
 // Translation Table Base 0 fields\r
 \r
 \r
 // Translation Table Base 0 fields\r


@@ -434,6 +434,8 @@ UpdatePageEntries (
   UINT32        p;\r
   UINT32        PageTableIndex;\r
   UINT32        PageTableEntry;\r
   UINT32        p;\r
   UINT32        PageTableIndex;\r
   UINT32        PageTableEntry;\r

+  UINT32        CurrentPageTableEntry;\r
+  VOID          *Mva;\r

 \r
   volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;\r
   volatile ARM_PAGE_TABLE_ENTRY         *PageTable;\r
 \r
   volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;\r
   volatile ARM_PAGE_TABLE_ENTRY         *PageTable;\r


@@ -492,7 +494,7 @@ UpdatePageEntries (
   FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r
 \r
   // calculate number of 4KB page table entries to change\r
   FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r
 \r
   // calculate number of 4KB page table entries to change\r

-  NumPageEntries = Length/EFI_PAGE_SIZE;\r
+  NumPageEntries = Length/SIZE_4KB;\r

   \r
   // iterate for the number of 4KB pages to change\r
   Offset = 0;\r
   \r
   // iterate for the number of 4KB pages to change\r
   Offset = 0;\r


@@ -525,10 +527,10 @@ UpdatePageEntries (
     ASSERT (PageTableIndex < SMALL_PAGE_TABLE_ENTRY_COUNT);\r
 \r
     // get the entry\r
     ASSERT (PageTableIndex < SMALL_PAGE_TABLE_ENTRY_COUNT);\r
 \r
     // get the entry\r

-    PageTableEntry = PageTable[PageTableIndex];\r
+    CurrentPageTableEntry = PageTable[PageTableIndex];\r

 \r
     // mask off appropriate fields\r
 \r
     // mask off appropriate fields\r

-    PageTableEntry &= ~EntryMask;\r
+    PageTableEntry = CurrentPageTableEntry & ~EntryMask;\r

 \r
     // mask in new attributes and/or permissions\r
     PageTableEntry |= EntryValue;\r
 \r
     // mask in new attributes and/or permissions\r
     PageTableEntry |= EntryValue;\r


@@ -537,13 +539,22 @@ UpdatePageEntries (
       // Make this virtual address point at a physical page\r
       PageTableEntry &= ~VirtualMask;\r
     }\r
       // Make this virtual address point at a physical page\r
       PageTableEntry &= ~VirtualMask;\r
     }\r

-    \r
-    // update the entry\r
-    PageTable[PageTableIndex] = PageTableEntry; \r

    \r
    \r

+    if (CurrentPageTableEntry  != PageTableEntry) {\r
+      Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << ARM_SECTION_BASE_SHIFT) + (PageTableIndex << ARM_SMALL_PAGE_BASE_SHIFT));\r
+      if ((CurrentPageTableEntry & ARM_PAGE_C) == ARM_PAGE_C) {\r
+        // The current section mapping is cacheable so Clean/Invalidate the MVA of the page\r
+        // Note assumes switch(Attributes), not ARMv7 possibilities\r
+        WriteBackInvalidateDataCacheRange (Mva, SIZE_4KB);\r
+      }\r
+\r
+      // Only need to update if we are changing the entry  \r
+      PageTable[PageTableIndex] = PageTableEntry; \r
+      ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);\r
+    }\r

 \r
     Status = EFI_SUCCESS;\r
 \r
     Status = EFI_SUCCESS;\r

-    Offset += EFI_PAGE_SIZE;\r
+    Offset += SIZE_4KB;\r

     \r
   } // end first level translation table loop\r
 \r
     \r
   } // end first level translation table loop\r
 \r


@@ -566,8 +577,9 @@ UpdateSectionEntries (
   UINT32        FirstLevelIdx;\r
   UINT32        NumSections;\r
   UINT32        i;\r
   UINT32        FirstLevelIdx;\r
   UINT32        NumSections;\r
   UINT32        i;\r

+  UINT32        CurrentDescriptor;\r

   UINT32        Descriptor;\r
   UINT32        Descriptor;\r

-\r
+  VOID          *Mva;\r

   volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;\r
 \r
   // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
   volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;\r
 \r
   // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r


@@ -582,28 +594,28 @@ UpdateSectionEntries (
   switch(Attributes) {\r
     case EFI_MEMORY_UC:\r
       // modify cacheability attributes\r
   switch(Attributes) {\r
     case EFI_MEMORY_UC:\r
       // modify cacheability attributes\r

-      EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+      EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r

       // map to strongly ordered\r
       EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0\r
       break;\r
 \r
     case EFI_MEMORY_WC:\r
       // modify cacheability attributes\r
       // map to strongly ordered\r
       EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0\r
       break;\r
 \r
     case EFI_MEMORY_WC:\r
       // modify cacheability attributes\r

-      EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+      EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r

       // map to normal non-cachable\r
       EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r
       break;\r
 \r
     case EFI_MEMORY_WT:\r
       // modify cacheability attributes\r
       // map to normal non-cachable\r
       EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r
       break;\r
 \r
     case EFI_MEMORY_WT:\r
       // modify cacheability attributes\r

-      EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+      EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r

       // write through with no-allocate\r
       EntryValue |= ARM_SECTION_C; // TEX [2:0] = 0, C=1, B=0\r
       break;\r
 \r
     case EFI_MEMORY_WB:\r
       // modify cacheability attributes\r
       // write through with no-allocate\r
       EntryValue |= ARM_SECTION_C; // TEX [2:0] = 0, C=1, B=0\r
       break;\r
 \r
     case EFI_MEMORY_WB:\r
       // modify cacheability attributes\r

-      EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+      EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r

       // write back (with allocate)\r
       EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT) | ARM_SECTION_C | ARM_SECTION_B; // TEX [2:0] = 001, C=1, B=1\r
       break;\r
       // write back (with allocate)\r
       EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT) | ARM_SECTION_C | ARM_SECTION_B; // TEX [2:0] = 001, C=1, B=1\r
       break;\r


@@ -635,17 +647,17 @@ UpdateSectionEntries (
   \r
   // iterate through each descriptor\r
   for(i=0; i<NumSections; i++) {\r
   \r
   // iterate through each descriptor\r
   for(i=0; i<NumSections; i++) {\r

-    Descriptor = FirstLevelTable[FirstLevelIdx + i];\r
+    CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];\r

 \r
     // has this descriptor already been coverted to pages?\r
 \r
     // has this descriptor already been coverted to pages?\r

-    if ((Descriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {\r
+    if ((CurrentDescriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {\r

       // forward this 1MB range to page table function instead\r
       Status = UpdatePageEntries ((FirstLevelIdx + i) << ARM_SECTION_BASE_SHIFT, ARM_PAGE_DESC_ENTRY_MVA_SIZE, Attributes, VirtualMask);\r
     } else {\r
       // still a section entry\r
       \r
       // mask off appropriate fields\r
       // forward this 1MB range to page table function instead\r
       Status = UpdatePageEntries ((FirstLevelIdx + i) << ARM_SECTION_BASE_SHIFT, ARM_PAGE_DESC_ENTRY_MVA_SIZE, Attributes, VirtualMask);\r
     } else {\r
       // still a section entry\r
       \r
       // mask off appropriate fields\r

-      Descriptor &= ~EntryMask;\r
+      Descriptor = CurrentDescriptor & ~EntryMask;\r

 \r
       // mask in new attributes and/or permissions\r
       Descriptor |= EntryValue;\r
 \r
       // mask in new attributes and/or permissions\r
       Descriptor |= EntryValue;\r


@@ -653,7 +665,18 @@ UpdateSectionEntries (
         Descriptor &= ~VirtualMask;\r
       }\r
 \r
         Descriptor &= ~VirtualMask;\r
       }\r
 \r

-      FirstLevelTable[FirstLevelIdx + i] = Descriptor;\r
+      if (CurrentDescriptor  != Descriptor) {\r
+        Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << ARM_SECTION_BASE_SHIFT);\r
+        if ((CurrentDescriptor & ARM_SECTION_C) == ARM_SECTION_C) {\r
+          // The current section mapping is cacheable so Clean/Invalidate the MVA of the section\r
+          // Note assumes switch(Attributes), not ARMv7 possabilities\r
+          WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);\r
+        }\r
+\r
+        // Only need to update if we are changing the descriptor  \r
+        FirstLevelTable[FirstLevelIdx + i] = Descriptor;\r
+        ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);\r
+      }\r

 \r
       Status = EFI_SUCCESS;\r
     }\r
 \r
       Status = EFI_SUCCESS;\r
     }\r


@@ -720,12 +743,12 @@ ConvertSectionToPages (
   PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;\r
 \r
   // write the page table entries out\r
   PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;\r
 \r
   // write the page table entries out\r

-  for (i=0; i<(ARM_PAGE_DESC_ENTRY_MVA_SIZE/EFI_PAGE_SIZE); i++) {\r
+  for (i=0; i<(ARM_PAGE_DESC_ENTRY_MVA_SIZE/SIZE_4KB); i++) {\r

     PageTable[i] = ((BaseAddress + (i << 12)) & ARM_SMALL_PAGE_BASE_MASK) | PageDescriptor;\r
   }\r
 \r
   // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
     PageTable[i] = ((BaseAddress + (i << 12)) & ARM_SMALL_PAGE_BASE_MASK) | PageDescriptor;\r
   }\r
 \r
   // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r

-  InvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, EFI_PAGE_SIZE);\r
+  WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, SIZE_4KB);\r

 \r
   // formulate page table entry, Domain=0, NS=0\r
   PageTableDescriptor = (((UINTN)PageTableAddr) & ARM_PAGE_DESC_BASE_MASK) | ARM_DESC_TYPE_PAGE_TABLE;\r
 \r
   // formulate page table entry, Domain=0, NS=0\r
   PageTableDescriptor = (((UINTN)PageTableAddr) & ARM_PAGE_DESC_BASE_MASK) | ARM_DESC_TYPE_PAGE_TABLE;\r


@@ -802,9 +825,9 @@ CpuSetMemoryAttributes (
   )\r
 {\r
   DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress, Length, Attributes));\r
   )\r
 {\r
   DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress, Length, Attributes));\r

-  if ( ((BaseAddress & (EFI_PAGE_SIZE-1)) != 0) || ((Length & (EFI_PAGE_SIZE-1)) != 0)){\r
-    // minimum granularity is EFI_PAGE_SIZE (4KB on ARM)\r
-    DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is EFI_PAGE_SIZE\n", BaseAddress, Length, Attributes));\r
+  if ( ((BaseAddress & (SIZE_4KB-1)) != 0) || ((Length & (SIZE_4KB-1)) != 0)){\r
+    // minimum granularity is SIZE_4KB (4KB on ARM)\r
+    DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is SIZE_4KB\n", BaseAddress, Length, Attributes));\r

     return EFI_UNSUPPORTED;\r
   }\r
   \r
     return EFI_UNSUPPORTED;\r
   }\r
   \r

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index e762489e2f517925ac59deee214efbe84c30e52c..f6fd84688c33f13d368bcaa485eca7a2fcf5f2be 100644 (file)
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -268,7 +268,8 @@ ArmInvalidateTlb (
 VOID
 EFIAPI
 ArmUpdateTranslationTableEntry (
 VOID
 EFIAPI
 ArmUpdateTranslationTableEntry (

-  IN  UINTN    Mva
+  IN  VOID     *TranslationTableEntry,
+  IN  VOID     *Mva

   );
   
 VOID
   );
   
 VOID


@@ -345,4 +346,5 @@ ArmInstructionSynchronizationBarrier (
   VOID
   );
   
   VOID
   );
   

+

 #endif // __ARM_LIB__
 #endif // __ARM_LIB__

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S
index cdfd3dc9cf4cd3bd92d13970fea8b093a6a067a5..9932e1462b93c6ac2b32e39313f2ec188f14cccc 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S
@@ -1,6 +1,6 @@
 #------------------------------------------------------------------------------ 
 #
 #------------------------------------------------------------------------------ 
 #

-# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+# Copyright (c) 2008-2010 Apple Inc. All rights reserved.

 #
 # All rights reserved. This program and the accompanying materials
 # are licensed and made available under the terms and conditions of the BSD License
 #
 # All rights reserved. This program and the accompanying materials
 # are licensed and made available under the terms and conditions of the BSD License


@@ -12,8 +12,6 @@
 #
 #------------------------------------------------------------------------------
 
 #
 #------------------------------------------------------------------------------
 

-.text
-.align 2

 .globl ASM_PFX(Cp15IdCode)
 .globl ASM_PFX(Cp15CacheInfo)
 .globl ASM_PFX(ArmEnableInterrupts)
 .globl ASM_PFX(Cp15IdCode)
 .globl ASM_PFX(Cp15CacheInfo)
 .globl ASM_PFX(ArmEnableInterrupts)


@@ -26,11 +24,14 @@
 .globl ASM_PFX(ArmSetTranslationTableBaseAddress)
 .globl ASM_PFX(ArmGetTranslationTableBaseAddress)
 .globl ASM_PFX(ArmSetDomainAccessControl)
 .globl ASM_PFX(ArmSetTranslationTableBaseAddress)
 .globl ASM_PFX(ArmGetTranslationTableBaseAddress)
 .globl ASM_PFX(ArmSetDomainAccessControl)

+.globl ASM_PFX(ArmUpdateTranslationTableEntry)

 .globl ASM_PFX(CPSRMaskInsert)
 .globl ASM_PFX(CPSRRead)
 .globl ASM_PFX(ReadCCSIDR)
 .globl ASM_PFX(ReadCLIDR)
 
 .globl ASM_PFX(CPSRMaskInsert)
 .globl ASM_PFX(CPSRRead)
 .globl ASM_PFX(ReadCCSIDR)
 .globl ASM_PFX(ReadCLIDR)
 

+.text
+.align 2

 
 #------------------------------------------------------------------------------
 
 
 #------------------------------------------------------------------------------
 


@@ -67,7 +68,7 @@ ASM_PFX(ArmDisableFiq):
 
 ASM_PFX(ArmGetFiqState):
        mrs     R0,CPSR
 
 ASM_PFX(ArmGetFiqState):
        mrs     R0,CPSR

-       tst     R0,#0x30            @Check if IRQ is enabled.
+       tst     R0,#0x40            @Check if FIQ is enabled.

        moveq   R0,#1
        movne   R0,#0
        bx      LR
        moveq   R0,#1
        movne   R0,#0
        bx      LR


@@ -75,6 +76,8 @@ ASM_PFX(ArmGetFiqState):
 ASM_PFX(ArmInvalidateTlb):
   mov     r0,#0
   mcr     p15,0,r0,c8,c7,0
 ASM_PFX(ArmInvalidateTlb):
   mov     r0,#0
   mcr     p15,0,r0,c8,c7,0

+  mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp
+  dsb

   isb
   bx      lr
 
   isb
   bx      lr
 


@@ -85,6 +88,7 @@ ASM_PFX(ArmSetTranslationTableBaseAddress):
 
 ASM_PFX(ArmGetTranslationTableBaseAddress):
   mrc     p15,0,r0,c2,c0,0
 
 ASM_PFX(ArmGetTranslationTableBaseAddress):
   mrc     p15,0,r0,c2,c0,0

+  isb

   bx      lr
 
 
   bx      lr
 
 


@@ -93,6 +97,21 @@ ASM_PFX(ArmSetDomainAccessControl):
   isb
   bx      lr
 
   isb
   bx      lr
 

+//
+//VOID
+//ArmUpdateTranslationTableEntry (
+//  IN VOID  *TranslationTableEntry  // R0
+//  IN VOID  *MVA                    // R1
+//  );
+ASM_PFX(ArmUpdateTranslationTableEntry):
+  mcr     p15,0,R0,c7,c14,1     @ DCCIMVAC Clean data cache by MVA
+  dsb
+  mcr     p15,0,R1,c8,c7,1      @ TLBIMVA TLB Invalidate MVA  
+  mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp
+  dsb
+  isb
+  bx      lr
+

 ASM_PFX(CPSRMaskInsert):    @ on entry, r0 is the mask and r1 is the field to insert
   stmfd   sp!, {r4-r12, lr} @ save all the banked registers
   mov     r3, sp            @ copy the stack pointer into a non-banked register
 ASM_PFX(CPSRMaskInsert):    @ on entry, r0 is the mask and r1 is the field to insert
   stmfd   sp!, {r4-r12, lr} @ save all the banked registers
   mov     r3, sp            @ copy the stack pointer into a non-banked register


@@ -101,6 +120,7 @@ ASM_PFX(CPSRMaskInsert):    @ on entry, r0 is the mask and r1 is the field to in
   and     r1, r1, r0        @ clear bits outside the mask in the input
   orr     r2, r2, r1        @ set field
   msr     cpsr_cxsf, r2     @ write back cpsr (may have caused a mode switch)
   and     r1, r1, r0        @ clear bits outside the mask in the input
   orr     r2, r2, r1        @ set field
   msr     cpsr_cxsf, r2     @ write back cpsr (may have caused a mode switch)

+  isb

   mov     sp, r3            @ restore stack pointer
   ldmfd   sp!, {r4-r12, lr} @ restore registers
   bx      lr                @ return (hopefully thumb-safe!)
   mov     sp, r3            @ restore stack pointer
   ldmfd   sp!, {r4-r12, lr} @ restore registers
   bx      lr                @ return (hopefully thumb-safe!)


@@ -109,14 +129,22 @@ ASM_PFX(CPSRRead):
   mrs     r0, cpsr
   bx      lr
   
   mrs     r0, cpsr
   bx      lr
   

+// UINT32 
+// ReadCCSIDR (
+//   IN UINT32 CSSELR
+//   )  

 ASM_PFX(ReadCCSIDR):
   mcr p15,2,r0,c0,c0,0   @ Write Cache Size Selection Register (CSSELR)
   isb
   mrc p15,1,r0,c0,c0,0   @ Read current CP15 Cache Size ID Register (CCSIDR)
   bx  lr
   
 ASM_PFX(ReadCCSIDR):
   mcr p15,2,r0,c0,c0,0   @ Write Cache Size Selection Register (CSSELR)
   isb
   mrc p15,1,r0,c0,c0,0   @ Read current CP15 Cache Size ID Register (CCSIDR)
   bx  lr
   

-
+// UINT32 
+// ReadCLIDR (
+//   IN UINT32 CSSELR
+//   )  

 ASM_PFX(ReadCLIDR):
   mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
 ASM_PFX(ReadCLIDR):
   mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register

+  bx  lr

 
 ASM_FUNCTION_REMOVE_IF_UNREFERENCED
 
 ASM_FUNCTION_REMOVE_IF_UNREFERENCED

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
index 65b3683f2670a916ddb8fe40253ec37593eec1b6..b0350998d12b55f44a4c8709aec9bfe2d57e3764 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
@@ -1,6 +1,6 @@
 //------------------------------------------------------------------------------ 
 //
 //------------------------------------------------------------------------------ 
 //

-// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+// Copyright (c) 2008-2010 Apple Inc. All rights reserved.

 //
 // All rights reserved. This program and the accompanying materials
 // are licensed and made available under the terms and conditions of the BSD License
 //
 // All rights reserved. This program and the accompanying materials
 // are licensed and made available under the terms and conditions of the BSD License


@@ -25,6 +25,7 @@
     EXPORT  ArmSetTranslationTableBaseAddress
     EXPORT  ArmGetTranslationTableBaseAddress
     EXPORT  ArmSetDomainAccessControl
     EXPORT  ArmSetTranslationTableBaseAddress
     EXPORT  ArmGetTranslationTableBaseAddress
     EXPORT  ArmSetDomainAccessControl

+    EXPORT  ArmUpdateTranslationTableEntry

     EXPORT  CPSRMaskInsert
     EXPORT  CPSRRead
     EXPORT  ReadCCSIDR
     EXPORT  CPSRMaskInsert
     EXPORT  CPSRRead
     EXPORT  ReadCCSIDR


@@ -32,6 +33,9 @@
     
     AREA ArmLibSupport, CODE, READONLY
 
     
     AREA ArmLibSupport, CODE, READONLY
 

+
+//------------------------------------------------------------------------------
+

 Cp15IdCode
   mrc     p15,0,R0,c0,c0,0
   bx      LR
 Cp15IdCode
   mrc     p15,0,R0,c0,c0,0
   bx      LR


@@ -41,11 +45,11 @@ Cp15CacheInfo
   bx      LR
 
 ArmEnableInterrupts
   bx      LR
 
 ArmEnableInterrupts

-  CPSIE   i
+  cpsie   i

        bx      LR
 
 ArmDisableInterrupts
        bx      LR
 
 ArmDisableInterrupts

-  CPSID   i
+  cpsid   i

        bx      LR
 
 ArmGetInterruptState
        bx      LR
 
 ArmGetInterruptState


@@ -54,18 +58,18 @@ ArmGetInterruptState
        moveq   R0,#1
        movne   R0,#0
        bx      LR
        moveq   R0,#1
        movne   R0,#0
        bx      LR

-       
+

 ArmEnableFiq
 ArmEnableFiq

-  CPSIE   f
+  cpsie   f

        bx      LR
 
 ArmDisableFiq
        bx      LR
 
 ArmDisableFiq

-  CPSID   f
+  cpsid   f

        bx      LR
 
 ArmGetFiqState
        mrs     R0,CPSR
        bx      LR
 
 ArmGetFiqState
        mrs     R0,CPSR

-       tst     R0,#0x40            ;Check if IRQ is enabled.
+       tst     R0,#0x40            ;Check if FIQ is enabled.

        moveq   R0,#1
        movne   R0,#0
        bx      LR
        moveq   R0,#1
        movne   R0,#0
        bx      LR


@@ -73,22 +77,40 @@ ArmGetFiqState
 ArmInvalidateTlb
   mov     r0,#0
   mcr     p15,0,r0,c8,c7,0
 ArmInvalidateTlb
   mov     r0,#0
   mcr     p15,0,r0,c8,c7,0

-  ISB
+  mcr     p15,0,R9,c7,c5,6      ; BPIALL Invalidate Branch predictor array. R9 == NoOp
+  dsb
+  isb

   bx      lr
 
 ArmSetTranslationTableBaseAddress
   mcr     p15,0,r0,c2,c0,0
   bx      lr
 
 ArmSetTranslationTableBaseAddress
   mcr     p15,0,r0,c2,c0,0

-  ISB
+  isb

   bx      lr
 
 ArmGetTranslationTableBaseAddress
   mrc     p15,0,r0,c2,c0,0
   bx      lr
 
 ArmGetTranslationTableBaseAddress
   mrc     p15,0,r0,c2,c0,0

-  ISB
+  isb

   bx      lr
 
   bx      lr
 

+

 ArmSetDomainAccessControl
   mcr     p15,0,r0,c3,c0,0
 ArmSetDomainAccessControl
   mcr     p15,0,r0,c3,c0,0

-  ISB
+  isb
+  bx      lr
+
+//
+//VOID
+//ArmUpdateTranslationTableEntry (
+//  IN VOID  *TranslationTableEntry  // R0
+//  IN VOID  *MVA                    // R1
+//  );
+ArmUpdateTranslationTableEntry
+  mcr     p15,0,R0,c7,c14,1     ; DCCIMVAC Clean data cache by MVA
+  dsb
+  mcr     p15,0,R1,c8,c7,1      ; TLBIMVA TLB Invalidate MVA  
+  mcr     p15,0,R9,c7,c5,6      ; BPIALL Invalidate Branch predictor array. R9 == NoOp
+  dsb
+  isb

   bx      lr
 
 CPSRMaskInsert              ; on entry, r0 is the mask and r1 is the field to insert
   bx      lr
 
 CPSRMaskInsert              ; on entry, r0 is the mask and r1 is the field to insert


@@ -99,7 +121,7 @@ CPSRMaskInsert              ; on entry, r0 is the mask and r1 is the field to in
   and     r1, r1, r0        ; clear bits outside the mask in the input
   orr     r2, r2, r1        ; set field
   msr     cpsr_cxsf, r2     ; write back cpsr (may have caused a mode switch)
   and     r1, r1, r0        ; clear bits outside the mask in the input
   orr     r2, r2, r1        ; set field
   msr     cpsr_cxsf, r2     ; write back cpsr (may have caused a mode switch)

-  ISB
+  isb

   mov     sp, r3            ; restore stack pointer
   ldmfd   sp!, {r4-r12, lr} ; restore registers
   bx      lr                ; return (hopefully thumb-safe!)
   mov     sp, r3            ; restore stack pointer
   ldmfd   sp!, {r4-r12, lr} ; restore registers
   bx      lr                ; return (hopefully thumb-safe!)


@@ -114,10 +136,10 @@ CPSRRead
 //   IN UINT32 CSSELR
 //   )  
 ReadCCSIDR
 //   IN UINT32 CSSELR
 //   )  
 ReadCCSIDR

-  MCR p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
-  ISB
-  MRC p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
-  BX  lr
+  mcr p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
+  isb
+  mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
+  bx  lr

   
 
 // UINT32 
   
 
 // UINT32 


@@ -125,7 +147,10 @@ ReadCCSIDR
 //   IN UINT32 CSSELR
 //   )  
 ReadCLIDR
 //   IN UINT32 CSSELR
 //   )  
 ReadCLIDR

-  MRC p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
-  END
+  mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
+  bx  lr
+  
+
+END

 
 
 
 

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
index 6d65b7e7278be7c2c4a6f1c2d7f93a48c4182bad..64c820725177871ca89c79ff1fc3fcda685405ad 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
@@ -114,6 +114,7 @@ ArmDisableMmu
   isb
   bx      LR
 
   isb
   bx      LR
 

+

 ArmEnableDataCache
   ldr     R1,=DC_ON
   mrc     p15,0,R0,c1,c0,0      ;Read control register configuration data
 ArmEnableDataCache
   ldr     R1,=DC_ON
   mrc     p15,0,R0,c1,c0,0      ;Read control register configuration data

diff --git a/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandler.c b/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandler.c
index 927a66b915ab76ac3ad421992261ffc91166599c..ebbaeb24bfc821026591d45bd9235cc167c06d36 100644 (file)
--- a/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandler.c
+++ b/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandler.c
@@ -299,6 +299,10 @@ DefaultExceptionHandler (
   DEBUG ((EFI_D_ERROR, "\n"));\r
   ASSERT (FALSE);\r
   \r
   DEBUG ((EFI_D_ERROR, "\n"));\r
   ASSERT (FALSE);\r
   \r

+  // Clear the error registers that we have already displayed incase some one wants to keep going\r
+  SystemContext.SystemContextArm->DFSR = 0;\r
+  SystemContext.SystemContextArm->IFSR = 0;\r
+\r

   // If some one is stepping past the exception handler adjust the PC to point to the next instruction \r
   SystemContext.SystemContextArm->PC += PcAdjust;\r
 }\r
   // If some one is stepping past the exception handler adjust the PC to point to the next instruction \r
   SystemContext.SystemContextArm->PC += PcAdjust;\r
 }\r