]> git.proxmox.com Git - mirror_edk2.git/commitdiff
IntelFsp2Pkg/GenCfgOpt.py: support FixedAtBuild PCD
authorChasel, Chiu <chasel.chiu@intel.com>
Wed, 26 Sep 2018 02:52:36 +0000 (10:52 +0800)
committerChasel, Chiu <chasel.chiu@intel.com>
Thu, 27 Sep 2018 23:58:48 +0000 (07:58 +0800)
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1210

FixedAtBuild PCD is suggested to be used instead
of FeatureFlag PCD so extend this tool to support.
Also skipped PCDs which commented out by '#'.

Test: Verified with FixedAtBuild PCD for including or
excluding lines in generated UPD header files successfully.

Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
IntelFsp2Pkg/Tools/GenCfgOpt.py

index c9b7bc5373fb77c3ac46cba54489f2a31f90dfbc..32cf63ff03a4ee6e74d026f35e4d303862363ace 100644 (file)
@@ -1,6 +1,6 @@
 ## @ GenCfgOpt.py\r
 #\r
-# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
 # This program and the accompanying materials are licensed and made available under\r
 # the terms and conditions of the BSD License that accompanies this distribution.\r
 # The full text of the license may be found at\r
@@ -449,7 +449,7 @@ EndList
                 IsUpdSect = False\r
                 if  Match.group(1).lower() == "Defines".lower():\r
                     IsDefSect = True\r
-                if  Match.group(1).lower() == "PcdsFeatureFlag".lower():\r
+                if  (Match.group(1).lower() == "PcdsFeatureFlag".lower() or Match.group(1).lower() == "PcdsFixedAtBuild".lower()):\r
                     IsPcdSect = True\r
                 elif Match.group(1).lower() == "PcdsDynamicVpd.Upd".lower():\r
                     ConfigDict = {}\r
@@ -491,7 +491,7 @@ EndList
                             IfStack.append(Result)\r
                             ElifStack.append(0)\r
                         else:\r
-                            Match  = re.match("!(if|elseif)\s+(.+)", DscLine)\r
+                            Match  = re.match("!(if|elseif)\s+(.+)", DscLine.split("#")[0])\r
                             if Match:\r
                                 Result = self.EvaluateExpress(Match.group(2))\r
                                 if Match.group(1) == "if":\r