MdePkg: Remove the macro definitions regarding Opcode.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790

Remove the macro definitions regarding Opcode because new version of
NASM tool(e.g. v2.15.05) supports the corresponding instructions.
Note: This patch need to be merged after other NASM code change to avoid
compilation errors.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

diff --git a/MdePkg/Include/Ia32/Nasm.inc b/MdePkg/Include/Ia32/Nasm.inc
index c794d9ece3774510125a40eb6d30aea2a9382bfc..e92c032bd8dbb6bfc72ba76c8ac72cbcf637beb8 100644 (file)
--- a/MdePkg/Include/Ia32/Nasm.inc
+++ b/MdePkg/Include/Ia32/Nasm.inc
@@ -1,6 +1,6 @@
 ;------------------------------------------------------------------------------\r
 ;\r
-; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
 ; Abstract:\r
@@ -9,30 +9,6 @@
 ;\r
 ;------------------------------------------------------------------------------\r
 \r
-%macro SAVEPREVSSP     0\r
-    DB 0xF3, 0x0F, 0x01, 0xEA\r
-%endmacro\r
-\r
-%macro CLRSSBSY_EAX    0\r
-    DB 0x67, 0xF3, 0x0F, 0xAE, 0x30\r
-%endmacro\r
-\r
-%macro RSTORSSP_EAX    0\r
-    DB 0x67, 0xF3, 0x0F, 0x01, 0x28\r
-%endmacro\r
-\r
-%macro SETSSBSY        0\r
-    DB 0xF3, 0x0F, 0x01, 0xE8\r
-%endmacro\r
-\r
-%macro READSSP_EAX     0\r
-    DB 0xF3, 0x0F, 0x1E, 0xC8\r
-%endmacro\r
-\r
-%macro INCSSP_EAX      0\r
-    DB 0xF3, 0x0F, 0xAE, 0xE8\r
-%endmacro\r
-\r
 ; NASM provides built-in macros STRUC and ENDSTRUC for structure definition.\r
 ; For example, to define a structure called mytype containing a longword,\r
 ; a word, a byte and a string of bytes, you might code\r

diff --git a/MdePkg/Include/X64/Nasm.inc b/MdePkg/Include/X64/Nasm.inc
index cfb14edc944958be4953ef8b45201b32cdab09db..bb77ca6c32da0aaa06bbb79b1bcce271b2b97a44 100644 (file)
--- a/MdePkg/Include/X64/Nasm.inc
+++ b/MdePkg/Include/X64/Nasm.inc
@@ -1,6 +1,6 @@
 ;------------------------------------------------------------------------------\r
 ;\r
-; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
 ; Abstract:\r
@@ -9,30 +9,6 @@
 ;\r
 ;------------------------------------------------------------------------------\r
 \r
-%macro SAVEPREVSSP     0\r
-    DB 0xF3, 0x0F, 0x01, 0xEA\r
-%endmacro\r
-\r
-%macro CLRSSBSY_RAX    0\r
-    DB 0xF3, 0x0F, 0xAE, 0x30\r
-%endmacro\r
-\r
-%macro RSTORSSP_RAX    0\r
-    DB 0xF3, 0x0F, 0x01, 0x28\r
-%endmacro\r
-\r
-%macro SETSSBSY        0\r
-    DB 0xF3, 0x0F, 0x01, 0xE8\r
-%endmacro\r
-\r
-%macro READSSP_RAX     0\r
-    DB 0xF3, 0x48, 0x0F, 0x1E, 0xC8\r
-%endmacro\r
-\r
-%macro INCSSP_RAX      0\r
-    DB 0xF3, 0x48, 0x0F, 0xAE, 0xE8\r
-%endmacro\r
-\r
 ;\r
 ; Macro for the PVALIDATE instruction, defined in AMD APM volume 3.\r
 ; NASM feature request URL: https://bugzilla.nasm.us/show_bug.cgi?id=3392753\r