git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6240 6f19259b...

diff --git a/DuetPkg/IsaAcpiDxe/PcatIsaAcpi.c b/DuetPkg/IsaAcpiDxe/PcatIsaAcpi.c
index a6187287918f87d46677b7708b333cd426ce1e7d..674c6dfc00ae300d695daa1fde4b24bbd6ec2eac 100644 (file)
--- a/DuetPkg/IsaAcpiDxe/PcatIsaAcpi.c
+++ b/DuetPkg/IsaAcpiDxe/PcatIsaAcpi.c
@@ -115,14 +115,14 @@ Returns:
         //\r
         // See if this is a standard PCI to ISA Bridge from the Base Code and Class Code\r
         //\r
-        if (Pci.Hdr.ClassCode[1] == PCI_CLASS_ISA) {\r
+        if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA) {\r
           Status = EFI_SUCCESS;\r
         } \r
 \r
         //\r
         // See if this is an Intel PCI to ISA bridge in Positive Decode Mode\r
         //\r
-        if (Pci.Hdr.ClassCode[1] == PCI_CLASS_ISA_POSITIVE_DECODE &&\r
+        if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE &&\r
             Pci.Hdr.VendorId == 0x8086 && \r
             Pci.Hdr.DeviceId == 0x7110) {\r
           Status = EFI_SUCCESS;\r

diff --git a/DuetPkg/PciBusNoEnumerationDxe/PciBus.h b/DuetPkg/PciBusNoEnumerationDxe/PciBus.h
index 568f3ffb6bfb0599056bd378756a58f750897065..db5215ca1b8490b6a99923a0216e0f28e543dc23 100644 (file)
--- a/DuetPkg/PciBusNoEnumerationDxe/PciBus.h
+++ b/DuetPkg/PciBusNoEnumerationDxe/PciBus.h
@@ -218,7 +218,7 @@ static UINT64                      gAllZero   = 0;
 #include "PciPowerManagement.h"\r
 \r
 \r
-#define IS_ISA_BRIDGE(_p)       IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_ISA)  \r
-#define IS_INTEL_ISA_BRIDGE(_p) (IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_ISA_POSITIVE_DECODE) && ((_p)->Hdr.VendorId == 0x8086) && ((_p)->Hdr.DeviceId == 0x7110))\r
+#define IS_ISA_BRIDGE(_p)       IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)  \r
+#define IS_INTEL_ISA_BRIDGE(_p) (IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE) && ((_p)->Hdr.VendorId == 0x8086) && ((_p)->Hdr.DeviceId == 0x7110))\r
 \r
 #endif\r

diff --git a/DuetPkg/PciBusNoEnumerationDxe/PciCommand.c b/DuetPkg/PciBusNoEnumerationDxe/PciCommand.c
index 1654952d0317b5bde2222e13b0ea83293c287b46..61393edeb4e7129d7eff445c06aaa51700443813 100644 (file)
--- a/DuetPkg/PciBusNoEnumerationDxe/PciCommand.c
+++ b/DuetPkg/PciBusNoEnumerationDxe/PciCommand.c
@@ -420,7 +420,7 @@ Returns:
       PciIoDevice->PciIo.Pci.Read (\r
                                &PciIoDevice->PciIo,\r
                                EfiPciIoWidthUint32,\r
-                               EFI_PCI_CAPABILITY_PTR,\r
+                               PCI_CAPBILITY_POINTER_OFFSET,\r
                                1,\r
                                &Temp\r
                                );\r

diff --git a/DuetPkg/PciBusNoEnumerationDxe/PciOptionRomSupport.c b/DuetPkg/PciBusNoEnumerationDxe/PciOptionRomSupport.c
index 02815c76d38d3f0462afdf8793f9c6dd76a56266..a863475061b2a3db719fba0914cf1fc9b9286ab7 100644 (file)
--- a/DuetPkg/PciBusNoEnumerationDxe/PciOptionRomSupport.c
+++ b/DuetPkg/PciBusNoEnumerationDxe/PciOptionRomSupport.c
@@ -68,7 +68,7 @@ Returns:
   //\r
   // 0x30\r
   //\r
-  RomBarIndex = PCI_DEVICE_ROMBAR;\r
+  RomBarIndex = PCI_EXPANSION_ROM_BASE;\r
 \r
   if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {\r
     //\r
@@ -174,7 +174,7 @@ Returns:
   //\r
   // 0x30\r
   //\r
-  RomBarIndex = PCI_DEVICE_ROMBAR;\r
+  RomBarIndex = PCI_EXPANSION_ROM_BASE;\r
   if (IS_PCI_BRIDGE (&(PciDevice->Pci))) {\r
     //\r
     // if is ppb\r

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBus.h
index 9db1dde553fd2b0473a6231805f96c88377385ff..e594ae0fdb43cda42b759bf1b78b79c6caa1f9e7 100644 (file)
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBus.h
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBus.h
@@ -46,7 +46,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #include <Library/PcdLib.h>\r
 #include <Library/PciIncompatibleDeviceSupportLib.h>\r
 \r
-#include <IndustryStandard/Pci23.h>\r
+#include <IndustryStandard/Pci.h>\r
 #include <IndustryStandard/PeImage.h>\r
 #include <IndustryStandard/Acpi.h>\r
 #include "ComponentName.h"\r

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c
index 05d7273075c2f974f95059ffe646054a13e59cdf..6fa61cae291e6c259abc36489cc0a301b79d1f6f 100644 (file)
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c
@@ -146,7 +146,7 @@ LocateCapabilityRegBlock (
       PciIoRead (\r
                   &PciIoDevice->PciIo,\r
                   EfiPciIoWidthUint8,\r
-                  EFI_PCI_CAPABILITY_PTR,\r
+                  PCI_CAPBILITY_POINTER_OFFSET,\r
                   1,\r
                   &CapabilityPtr\r
                 );\r

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
index 90f3591cd9b4a9d908a9e6444e59405e1ae1c40b..c66c7e9bb31f5ec2f3f95c2e3f58a7aee6018bb1 100644 (file)
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
@@ -63,7 +63,7 @@ GetOpRomInfo (
   //\r
   // 0x30\r
   //\r
-  RomBarIndex = PCI_DEVICE_ROMBAR;\r
+  RomBarIndex = PCI_EXPANSION_ROM_BASE;\r
 \r
   if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {\r
     //\r
@@ -163,7 +163,7 @@ LoadOpRomImage (
   //\r
   // 0x30\r
   //\r
-  RomBarIndex = PCI_DEVICE_ROMBAR;\r
+  RomBarIndex = PCI_EXPANSION_ROM_BASE;\r
   if (IS_PCI_BRIDGE (&(PciDevice->Pci))) {\r
     //\r
     // if is ppb\r

diff --git a/MdePkg/Include/IndustryStandard/Pci22.h b/MdePkg/Include/IndustryStandard/Pci22.h
index e5b7077cebef47e056c3f2fa9ce50fea9f4c5da7..4a613f4e38c871f64591eaa094ab511161338729 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Pci22.h
+++ b/MdePkg/Include/IndustryStandard/Pci22.h
@@ -1,7 +1,12 @@
 /** @file\r
   Support for PCI 2.2 standard.\r
 \r
-  Copyright (c) 2006 - 2007, Intel Corporation                                                         \r
+  This file includes the definitions in the following specifications,\r
+    PCI Local Bus Specification, 2.0\r
+    PCI-to-PCI Bridge Architecture Specification,\r
+    PC Card Standard, 8.0\r
+\r
+  Copyright (c) 2006 - 2008, Intel Corporation                                                         \r
   All rights reserved. This program and the accompanying materials                          \r
   are licensed and made available under the terms and conditions of the BSD License         \r
   which accompanies this distribution.  The full text of the license may be found at        \r
@@ -16,16 +21,10 @@
 #define _PCI22_H_\r
 \r
 #define PCI_MAX_SEGMENT 0\r
-\r
 #define PCI_MAX_BUS     255\r
-\r
 #define PCI_MAX_DEVICE  31\r
 #define PCI_MAX_FUNC    7\r
 \r
-//\r
-// Command\r
-//\r
-#define PCI_VGA_PALETTE_SNOOP_DISABLED  0x20\r
 \r
 #pragma pack(1)\r
 typedef struct {\r
@@ -61,6 +60,9 @@ typedef struct {
   PCI_DEVICE_HEADER_TYPE_REGION Device;\r
 } PCI_TYPE00;\r
 \r
+///\r
+/// defined in PCI-to-PCI Bridge Architecture Specification\r
+///\r
 typedef struct {\r
   UINT32  Bar[2];\r
   UINT8   PrimaryBus;\r
@@ -96,162 +98,191 @@ typedef union {
   PCI_TYPE01  Bridge;\r
 } PCI_TYPE_GENERIC;\r
 \r
+/// \r
+/// CardBus Conroller Configuration Space, defined in PC Card Standard. 8.0\r
+///\r
 typedef struct {\r
-  UINT32  CardBusSocketReg; // Cardus Socket/ExCA Base\r
-  // Address Register\r
-  //\r
-  UINT16  Reserved;\r
-  UINT16  SecondaryStatus;      // Secondary Status\r
-  UINT8   PciBusNumber;         // PCI Bus Number\r
-  UINT8   CardBusBusNumber;     // CardBus Bus Number\r
-  UINT8   SubordinateBusNumber; // Subordinate Bus Number\r
-  UINT8   CardBusLatencyTimer;  // CardBus Latency Timer\r
-  UINT32  MemoryBase0;          // Memory Base Register 0\r
-  UINT32  MemoryLimit0;         // Memory Limit Register 0\r
+  UINT32  CardBusSocketReg;     ///< Cardus Socket/ExCA Base\r
+  UINT8   Cap_Ptr;\r
+  UINT8   Reserved;\r
+  UINT16  SecondaryStatus;      ///< Secondary Status\r
+  UINT8   PciBusNumber;         ///< PCI Bus Number\r
+  UINT8   CardBusBusNumber;     ///< CardBus Bus Number\r
+  UINT8   SubordinateBusNumber; ///< Subordinate Bus Number\r
+  UINT8   CardBusLatencyTimer;  ///< CardBus Latency Timer\r
+  UINT32  MemoryBase0;          ///< Memory Base Register 0\r
+  UINT32  MemoryLimit0;         ///< Memory Limit Register 0\r
   UINT32  MemoryBase1;\r
   UINT32  MemoryLimit1;\r
   UINT32  IoBase0;\r
-  UINT32  IoLimit0;             // I/O Base Register 0\r
-  UINT32  IoBase1;              // I/O Limit Register 0\r
+  UINT32  IoLimit0;             ///< I/O Base Register 0\r
+  UINT32  IoBase1;              ///< I/O Limit Register 0\r
   UINT32  IoLimit1;\r
-  UINT8   InterruptLine;        // Interrupt Line\r
-  UINT8   InterruptPin;         // Interrupt Pin\r
-  UINT16  BridgeControl;        // Bridge Control\r
+  UINT8   InterruptLine;        ///< Interrupt Line\r
+  UINT8   InterruptPin;         ///< Interrupt Pin\r
+  UINT16  BridgeControl;        ///< Bridge Control\r
 } PCI_CARDBUS_CONTROL_REGISTER;\r
 \r
-//\r
-// Definitions of PCI class bytes and manipulation macros.\r
-//\r
+///\r
+/// Definitions of PCI class bytes and manipulation macros.\r
+///\r
 #define PCI_CLASS_OLD                 0x00\r
-#define PCI_CLASS_OLD_OTHER           0x00\r
-#define PCI_CLASS_OLD_VGA             0x01\r
+#define   PCI_CLASS_OLD_OTHER           0x00\r
+#define   PCI_CLASS_OLD_VGA             0x01\r
 \r
 #define PCI_CLASS_MASS_STORAGE        0x01\r
-#define PCI_CLASS_MASS_STORAGE_SCSI   0x00\r
-#define PCI_CLASS_MASS_STORAGE_IDE    0x01  // obsolete\r
-#define PCI_CLASS_IDE                 0x01\r
-#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\r
-#define PCI_CLASS_MASS_STORAGE_IPI    0x03\r
-#define PCI_CLASS_MASS_STORAGE_RAID   0x04\r
-#define PCI_CLASS_MASS_STORAGE_OTHER  0x80\r
+#define   PCI_CLASS_MASS_STORAGE_SCSI   0x00\r
+#define   PCI_CLASS_MASS_STORAGE_IDE    0x01\r
+#define   PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\r
+#define   PCI_CLASS_MASS_STORAGE_IPI    0x03\r
+#define   PCI_CLASS_MASS_STORAGE_RAID   0x04\r
+#define   PCI_CLASS_MASS_STORAGE_OTHER  0x80\r
 \r
 #define PCI_CLASS_NETWORK             0x02\r
-#define PCI_CLASS_NETWORK_ETHERNET    0x00\r
-#define PCI_CLASS_ETHERNET            0x00  // obsolete\r
-#define PCI_CLASS_NETWORK_TOKENRING   0x01\r
-#define PCI_CLASS_NETWORK_FDDI        0x02\r
-#define PCI_CLASS_NETWORK_ATM         0x03\r
-#define PCI_CLASS_NETWORK_ISDN        0x04\r
-#define PCI_CLASS_NETWORK_OTHER       0x80\r
+#define   PCI_CLASS_NETWORK_ETHERNET    0x00  \r
+#define   PCI_CLASS_NETWORK_TOKENRING   0x01\r
+#define   PCI_CLASS_NETWORK_FDDI        0x02\r
+#define   PCI_CLASS_NETWORK_ATM         0x03\r
+#define   PCI_CLASS_NETWORK_ISDN        0x04\r
+#define   PCI_CLASS_NETWORK_OTHER       0x80\r
 \r
 #define PCI_CLASS_DISPLAY             0x03\r
-#define PCI_CLASS_DISPLAY_CTRL        0x03  // obsolete\r
-#define PCI_CLASS_DISPLAY_VGA         0x00\r
-#define PCI_CLASS_VGA                 0x00  // obsolete\r
-#define PCI_CLASS_DISPLAY_XGA         0x01\r
-#define PCI_CLASS_DISPLAY_3D          0x02\r
-#define PCI_CLASS_DISPLAY_OTHER       0x80\r
-#define PCI_CLASS_DISPLAY_GFX         0x80\r
-#define PCI_CLASS_GFX                 0x80  // obsolete\r
+#define   PCI_CLASS_DISPLAY_VGA         0x00\r
+#define     PCI_IF_VGA_VGA                0x00\r
+#define     PCI_IF_VGA_8514               0x01\r
+#define   PCI_CLASS_DISPLAY_XGA         0x01\r
+#define   PCI_CLASS_DISPLAY_3D          0x02\r
+#define   PCI_CLASS_DISPLAY_OTHER       0x80  \r
+#define   PCI_CLASS_DISPLAY_GFX         0x80\r
+\r
+#define PCI_CLASS_MEDIA               0x04\r
+#define   PCI_CLASS_MEDIA_VIDEO         0x00\r
+#define   PCI_CLASS_MEDIA_AUDIO         0x01\r
+#define   PCI_CLASS_MEDIA_TELEPHONE     0x02\r
+#define   PCI_CLASS_MEDIA_OTHER         0x80\r
+\r
+#define PCI_CLASS_MEMORY_CONTROLLER   0x05\r
+#define   PCI_CLASS_MEMORY_RAM          0x00\r
+#define   PCI_CLASS_MEMORY_FLASH        0x01\r
+#define   PCI_CLASS_MEMORY_OTHER        0x80\r
+\r
 #define PCI_CLASS_BRIDGE              0x06\r
-#define PCI_CLASS_BRIDGE_HOST         0x00\r
-#define PCI_CLASS_BRIDGE_ISA          0x01\r
-#define PCI_CLASS_ISA                 0x01  // obsolete\r
-#define PCI_CLASS_BRIDGE_EISA         0x02\r
-#define PCI_CLASS_BRIDGE_MCA          0x03\r
-#define PCI_CLASS_BRIDGE_P2P          0x04\r
-#define PCI_CLASS_BRIDGE_PCMCIA       0x05\r
-#define PCI_CLASS_BRIDGE_NUBUS        0x06\r
-#define PCI_CLASS_BRIDGE_CARDBUS      0x07\r
-#define PCI_CLASS_BRIDGE_RACEWAY      0x08\r
-#define PCI_CLASS_BRIDGE_ISA_PDECODE  0x80\r
-#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80  // obsolete\r
-\r
-#define PCI_CLASS_SCC                 0x07  // Simple communications controllers \r
-#define PCI_SUBCLASS_SERIAL           0x00\r
-#define PCI_IF_GENERIC_XT             0x00\r
-#define PCI_IF_16450                  0x01\r
-#define PCI_IF_16550                  0x02\r
-#define PCI_IF_16650                  0x03\r
-#define PCI_IF_16750                  0x04\r
-#define PCI_IF_16850                  0x05\r
-#define PCI_IF_16950                  0x06\r
-#define PCI_SUBCLASS_PARALLEL         0x01\r
-#define PCI_IF_PARALLEL_PORT          0x00\r
-#define PCI_IF_BI_DIR_PARALLEL_PORT   0x01\r
-#define PCI_IF_ECP_PARALLEL_PORT      0x02\r
-#define PCI_IF_1284_CONTROLLER        0x03\r
-#define PCI_IF_1284_DEVICE            0xFE\r
-#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r
-#define PCI_SUBCLASS_MODEM            0x03\r
-#define PCI_IF_GENERIC_MODEM          0x00\r
-#define PCI_IF_16450_MODEM            0x01\r
-#define PCI_IF_16550_MODEM            0x02\r
-#define PCI_IF_16650_MODEM            0x03\r
-#define PCI_IF_16750_MODEM            0x04\r
-#define PCI_SUBCLASS_OTHER            0x80\r
+#define   PCI_CLASS_BRIDGE_HOST         0x00\r
+#define   PCI_CLASS_BRIDGE_ISA          0x01\r
+#define   PCI_CLASS_BRIDGE_EISA         0x02\r
+#define   PCI_CLASS_BRIDGE_MCA          0x03\r
+#define   PCI_CLASS_BRIDGE_P2P          0x04\r
+#define     PCI_IF_BRIDGE_P2P             0x00\r
+#define     PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01\r
+#define   PCI_CLASS_BRIDGE_PCMCIA       0x05\r
+#define   PCI_CLASS_BRIDGE_NUBUS        0x06\r
+#define   PCI_CLASS_BRIDGE_CARDBUS      0x07\r
+#define   PCI_CLASS_BRIDGE_RACEWAY      0x08\r
+#define   PCI_CLASS_BRIDGE_OTHER        0x80\r
+#define   PCI_CLASS_BRIDGE_ISA_PDECODE  0x80\r
+\r
+#define PCI_CLASS_SCC                 0x07  ///< Simple communications controllers \r
+#define   PCI_SUBCLASS_SERIAL           0x00\r
+#define     PCI_IF_GENERIC_XT             0x00\r
+#define     PCI_IF_16450                  0x01\r
+#define     PCI_IF_16550                  0x02\r
+#define     PCI_IF_16650                  0x03\r
+#define     PCI_IF_16750                  0x04\r
+#define     PCI_IF_16850                  0x05\r
+#define     PCI_IF_16950                  0x06\r
+#define   PCI_SUBCLASS_PARALLEL         0x01\r
+#define     PCI_IF_PARALLEL_PORT          0x00\r
+#define     PCI_IF_BI_DIR_PARALLEL_PORT   0x01\r
+#define     PCI_IF_ECP_PARALLEL_PORT      0x02\r
+#define     PCI_IF_1284_CONTROLLER        0x03\r
+#define     PCI_IF_1284_DEVICE            0xFE\r
+#define   PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r
+#define   PCI_SUBCLASS_MODEM            0x03\r
+#define     PCI_IF_GENERIC_MODEM          0x00\r
+#define     PCI_IF_16450_MODEM            0x01\r
+#define     PCI_IF_16550_MODEM            0x02\r
+#define     PCI_IF_16650_MODEM            0x03\r
+#define     PCI_IF_16750_MODEM            0x04\r
+#define   PCI_SUBCLASS_SCC_OTHER          0x80\r
 \r
 #define PCI_CLASS_SYSTEM_PERIPHERAL   0x08\r
-#define PCI_SUBCLASS_PIC              0x00\r
-#define PCI_IF_8259_PIC               0x00\r
-#define PCI_IF_ISA_PIC                0x01\r
-#define PCI_IF_EISA_PIC               0x02\r
-#define PCI_IF_APIC_CONTROLLER        0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.  \r
-#define PCI_IF_APIC_CONTROLLER2       0x20 \r
-#define PCI_SUBCLASS_TIMER            0x02\r
-#define PCI_IF_8254_TIMER             0x00\r
-#define PCI_IF_ISA_TIMER              0x01\r
-#define PCI_EISA_TIMER                0x02\r
-#define PCI_SUBCLASS_RTC              0x03\r
-#define PCI_IF_GENERIC_RTC            0x00\r
-#define PCI_IF_ISA_RTC                0x00\r
-#define PCI_SUBCLASS_PNP_CONTROLLER   0x04 // HotPlug Controller\r
+#define   PCI_SUBCLASS_PIC              0x00\r
+#define     PCI_IF_8259_PIC               0x00\r
+#define     PCI_IF_ISA_PIC                0x01\r
+#define     PCI_IF_EISA_PIC               0x02\r
+#define     PCI_IF_APIC_CONTROLLER        0x10  ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.  \r
+#define     PCI_IF_APIC_CONTROLLER2       0x20 \r
+#define   PCI_SUBCLASS_DMA              0x01\r
+#define     PCI_IF_8237_DMA               0x00\r
+#define     PCI_IF_ISA_DMA                0x01\r
+#define     PCI_IF_EISA_DMA               0x02\r
+#define   PCI_SUBCLASS_TIMER            0x02\r
+#define     PCI_IF_8254_TIMER             0x00\r
+#define     PCI_IF_ISA_TIMER              0x01\r
+#define     PCI_IF_EISA_TIMER             0x02\r
+#define   PCI_SUBCLASS_RTC              0x03\r
+#define     PCI_IF_GENERIC_RTC            0x00\r
+#define     PCI_IF_ISA_RTC                0x00\r
+#define   PCI_SUBCLASS_PNP_CONTROLLER   0x04    ///< HotPlug Controller\r
+#define   PCI_SUBCLASS_PERIPHERAL_OTHER 0x80\r
 \r
 #define PCI_CLASS_INPUT_DEVICE        0x09\r
-#define PCI_SUBCLASS_KEYBOARD         0x00\r
-#define PCI_SUBCLASS_PEN              0x01\r
-#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r
-#define PCI_SUBCLASS_SCAN_CONTROLLER  0x03\r
-#define PCI_SUBCLASS_GAMEPORT         0x04\r
+#define   PCI_SUBCLASS_KEYBOARD         0x00\r
+#define   PCI_SUBCLASS_PEN              0x01\r
+#define   PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r
+#define   PCI_SUBCLASS_SCAN_CONTROLLER  0x03\r
+#define   PCI_SUBCLASS_GAMEPORT         0x04\r
+#define     PCI_IF_GAMEPORT               0x00\r
+#define     PCI_IF_GAMEPORT1              0x01\r
+#define   PCI_SUBCLASS_INPUT_OTHER      0x80\r
 \r
 #define PCI_CLASS_DOCKING_STATION     0x0A\r
 \r
 #define PCI_CLASS_PROCESSOR           0x0B\r
-#define PCI_SUBCLASS_PROC_386         0x00\r
-#define PCI_SUBCLASS_PROC_486         0x01\r
-#define PCI_SUBCLASS_PROC_PENTIUM     0x02\r
-#define PCI_SUBCLASS_PROC_ALPHA       0x10\r
-#define PCI_SUBCLASS_PROC_POWERPC     0x20\r
-#define PCI_SUBCLASS_PROC_MIPS        0x30\r
-#define PCI_SUBCLASS_PROC_CO_PORC     0x40 // Co-Processor\r
+#define   PCI_SUBCLASS_PROC_386         0x00\r
+#define   PCI_SUBCLASS_PROC_486         0x01\r
+#define   PCI_SUBCLASS_PROC_PENTIUM     0x02\r
+#define   PCI_SUBCLASS_PROC_ALPHA       0x10\r
+#define   PCI_SUBCLASS_PROC_POWERPC     0x20\r
+#define   PCI_SUBCLASS_PROC_MIPS        0x30\r
+#define   PCI_SUBCLASS_PROC_CO_PORC     0x40 ///< Co-Processor\r
 \r
 #define PCI_CLASS_SERIAL              0x0C\r
-#define PCI_CLASS_SERIAL_FIREWIRE     0x00\r
-#define PCI_CLASS_SERIAL_ACCESS_BUS   0x01\r
-#define PCI_CLASS_SERIAL_SSA          0x02\r
-#define PCI_CLASS_SERIAL_USB          0x03\r
-#define PCI_IF_EHCI                   0x20\r
-#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r
-#define PCI_CLASS_SERIAL_SMB          0x05\r
+#define   PCI_CLASS_SERIAL_FIREWIRE     0x00\r
+#define     PCI_IF_1394                   0x00\r
+#define     PCI_IF_1394_OPEN_HCI          0x10\r
+#define   PCI_CLASS_SERIAL_ACCESS_BUS   0x01\r
+#define   PCI_CLASS_SERIAL_SSA          0x02\r
+#define   PCI_CLASS_SERIAL_USB          0x03\r
+#define     PCI_IF_UHCI                   0x00\r
+#define     PCI_IF_OHCI                   0x10\r
+#define     PCI_IF_USB_OTHER              0x80\r
+#define     PCI_IF_USB_DEVICE             0xFE\r
+#define   PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r
+#define   PCI_CLASS_SERIAL_SMB          0x05\r
 \r
 #define PCI_CLASS_WIRELESS            0x0D\r
-#define PCI_SUBCLASS_IRDA             0x00\r
-#define PCI_SUBCLASS_IR               0x01\r
-#define PCI_SUBCLASS_RF               0x02\r
+#define   PCI_SUBCLASS_IRDA             0x00\r
+#define   PCI_SUBCLASS_IR               0x01\r
+#define   PCI_SUBCLASS_RF               0x02\r
+#define   PCI_SUBCLASS_WIRELESS_OTHER   0x80\r
 \r
 #define PCI_CLASS_INTELLIGENT_IO      0x0E\r
 \r
 #define PCI_CLASS_SATELLITE           0x0F\r
-#define PCI_SUBCLASS_TV               0x01\r
-#define PCI_SUBCLASS_AUDIO            0x02\r
-#define PCI_SUBCLASS_VOICE            0x03\r
-#define PCI_SUBCLASS_DATA             0x04\r
+#define   PCI_SUBCLASS_TV               0x01\r
+#define   PCI_SUBCLASS_AUDIO            0x02\r
+#define   PCI_SUBCLASS_VOICE            0x03\r
+#define   PCI_SUBCLASS_DATA             0x04\r
 \r
-#define PCI_SECURITY_CONTROLLER       0x10 // Encryption and decryption controller\r
-#define PCI_SUBCLASS_NET_COMPUT       0x00\r
-#define PCI_SUBCLASS_ENTERTAINMENT    0x10 \r
+#define PCI_SECURITY_CONTROLLER       0x10   ///< Encryption and decryption controller\r
+#define   PCI_SUBCLASS_NET_COMPUT       0x00\r
+#define   PCI_SUBCLASS_ENTERTAINMENT    0x10 \r
+#define   PCI_SUBCLASS_SECURITY_OTHER   0x80\r
 \r
 #define PCI_CLASS_DPIO                0x11\r
+#define   PCI_SUBCLASS_DPIO             0x00\r
+#define   PCI_SUBCLASS_DPIO_OTHER       0x80\r
 \r
 #define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))\r
 #define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
@@ -272,18 +303,25 @@ typedef struct {
 #define IS_PCI_16550_SERIAL(_p)       IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
 #define IS_PCI_USB(_p)                IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r
 \r
+//\r
+// the definition of Header Type \r
+//\r
 #define HEADER_TYPE_DEVICE            0x00\r
 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\r
 #define HEADER_TYPE_CARDBUS_BRIDGE    0x02\r
-\r
 #define HEADER_TYPE_MULTI_FUNCTION    0x80\r
+//\r
+// Mask of Header type\r
+//\r
 #define HEADER_LAYOUT_CODE            0x7f\r
 \r
 #define IS_PCI_BRIDGE(_p)             (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r
 #define IS_CARDBUS_BRIDGE(_p)         (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r
 #define IS_PCI_MULTI_FUNC(_p)         ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r
 \r
-#define PCI_DEVICE_ROMBAR             0x30\r
+///\r
+/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,\r
+///\r
 #define PCI_BRIDGE_ROMBAR             0x38\r
 \r
 #define PCI_MAX_BAR                   0x0006\r
@@ -301,27 +339,29 @@ typedef struct {
 #define PCI_BIST_OFFSET                             0x0F\r
 #define PCI_BASE_ADDRESSREG_OFFSET                  0x10\r
 #define PCI_CARDBUS_CIS_OFFSET                      0x28\r
-#define PCI_SVID_OFFSET                             0x2C // SubSystem Vendor id\r
+#define PCI_SVID_OFFSET                             0x2C ///< SubSystem Vendor id\r
 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET              0x2C\r
-#define PCI_SID_OFFSET                              0x2E // SubSystem ID\r
+#define PCI_SID_OFFSET                              0x2E ///< SubSystem ID\r
 #define PCI_SUBSYSTEM_ID_OFFSET                     0x2E\r
 #define PCI_EXPANSION_ROM_BASE                      0x30\r
 #define PCI_CAPBILITY_POINTER_OFFSET                0x34\r
-#define PCI_INT_LINE_OFFSET                         0x3C // Interrupt Line Register\r
-#define PCI_INT_PIN_OFFSET                          0x3D // Interrupt Pin Register\r
-#define PCI_MAXGNT_OFFSET                           0x3E // Max Grant Register\r
-#define PCI_MAXLAT_OFFSET                           0x3F // Max Latency Register\r
-\r
-#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E\r
-#define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E\r
+#define PCI_INT_LINE_OFFSET                         0x3C ///< Interrupt Line Register\r
+#define PCI_INT_PIN_OFFSET                          0x3D ///< Interrupt Pin Register\r
+#define PCI_MAXGNT_OFFSET                           0x3E ///< Max Grant Register\r
+#define PCI_MAXLAT_OFFSET                           0x3F ///< Max Latency Register\r
 \r
-#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18\r
-#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19\r
-#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a\r
+///\r
+/// defined in PCI-to-PCI Bridge Architecture Specification\r
+///\r
+#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18   \r
+#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19   \r
+#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a   \r
+#define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E   \r
+#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E   \r
 \r
-//\r
-// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r
-//\r
+///\r
+/// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r
+///\r
 #define PCI_INT_LINE_UNKNOWN                        0xFF               \r
 \r
 typedef union {\r
@@ -338,85 +378,55 @@ typedef union {
 \r
 #pragma pack()\r
 \r
-#define PCI_EXPANSION_ROM_HEADER_SIGNATURE              0xaa55\r
-#define PCI_DATA_STRUCTURE_SIGNATURE                    EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')\r
-#define PCI_CODE_TYPE_PCAT_IMAGE                        0x00\r
-#define PCI_CODE_TYPE_EFI_IMAGE                         0x03\r
-#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED         0x0001\r
-\r
-#define EFI_PCI_COMMAND_IO_SPACE                        0x0001\r
-#define EFI_PCI_COMMAND_MEMORY_SPACE                    0x0002\r
-#define EFI_PCI_COMMAND_BUS_MASTER                      0x0004\r
-#define EFI_PCI_COMMAND_SPECIAL_CYCLE                   0x0008\r
-#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE     0x0010\r
-#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP               0x0020\r
-#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND            0x0040\r
-#define EFI_PCI_COMMAND_STEPPING_CONTROL                0x0080\r
-#define EFI_PCI_COMMAND_SERR                            0x0100\r
-#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK               0x0200\r
-\r
-#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE    0x0001\r
-#define EFI_PCI_BRIDGE_CONTROL_SERR                     0x0002\r
-#define EFI_PCI_BRIDGE_CONTROL_ISA                      0x0004\r
-#define EFI_PCI_BRIDGE_CONTROL_VGA                      0x0008\r
-#define EFI_PCI_BRIDGE_CONTROL_VGA_16                   0x0010\r
-#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT             0x0020\r
-#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS      0x0040\r
-#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK        0x0080\r
-#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER    0x0100\r
-#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER  0x0200\r
-#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS             0x0400\r
-#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR       0x0800\r
+#define EFI_PCI_COMMAND_IO_SPACE                        BIT0   ///< 0x0001\r
+#define EFI_PCI_COMMAND_MEMORY_SPACE                    BIT1   ///< 0x0002\r
+#define EFI_PCI_COMMAND_BUS_MASTER                      BIT2   ///< 0x0004\r
+#define EFI_PCI_COMMAND_SPECIAL_CYCLE                   BIT3   ///< 0x0008\r
+#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE     BIT4   ///< 0x0010\r
+#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP               BIT5   ///< 0x0020\r
+#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND            BIT6   ///< 0x0040\r
+#define EFI_PCI_COMMAND_STEPPING_CONTROL                BIT7   ///< 0x0080\r
+#define EFI_PCI_COMMAND_SERR                            BIT8   ///< 0x0100\r
+#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK               BIT9   ///< 0x0200\r
 \r
-//\r
-// Following are the PCI-CARDBUS bridge control bit\r
-//\r
-#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE       0x0080\r
-#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE   0x0100\r
-#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE   0x0200\r
-#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400\r
+///\r
+/// defined in PCI-to-PCI Bridge Architecture Specification\r
+///\r
+#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE    BIT0   ///< 0x0001\r
+#define EFI_PCI_BRIDGE_CONTROL_SERR                     BIT1   ///< 0x0002\r
+#define EFI_PCI_BRIDGE_CONTROL_ISA                      BIT2   ///< 0x0004\r
+#define EFI_PCI_BRIDGE_CONTROL_VGA                      BIT3   ///< 0x0008\r
+#define EFI_PCI_BRIDGE_CONTROL_VGA_16                   BIT4   ///< 0x0010\r
+#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT             BIT5   ///< 0x0020\r
+#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS      BIT6   ///< 0x0040\r
+#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK        BIT7   ///< 0x0080\r
+#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER    BIT8   ///< 0x0100\r
+#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER  BIT9   ///< 0x0200\r
+#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS             BIT10  ///< 0x0400\r
+#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR       BIT11  ///< 0x0800\r
+\r
+///\r
+/// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\r
+///\r
+#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE           BIT7   ///< 0x0080\r
+#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE       BIT8   ///< 0x0100\r
+#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE       BIT9   ///< 0x0200\r
+#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE     BIT10  ///< 0x0400\r
 \r
 //\r
 // Following are the PCI status control bit\r
 //\r
-#define EFI_PCI_STATUS_CAPABILITY             0x0010\r
-#define EFI_PCI_STATUS_66MZ_CAPABLE           0x0020\r
-#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE     0x0080\r
-#define EFI_PCI_MASTER_DATA_PARITY_ERROR      0x0100\r
+#define EFI_PCI_STATUS_CAPABILITY                       BIT4   ///< 0x0010\r
+#define EFI_PCI_STATUS_66MZ_CAPABLE                     BIT5   ///< 0x0020\r
+#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE               BIT7   ///< 0x0080\r
+#define EFI_PCI_MASTER_DATA_PARITY_ERROR                BIT8   ///< 0x0100\r
 \r
-#define EFI_PCI_CAPABILITY_PTR                0x34\r
+///\r
+/// defined in PC Card Standard\r
+///\r
 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r
 \r
 #pragma pack(1)\r
-typedef struct {\r
-  UINT16  Signature;    // 0xaa55\r
-  UINT8   Reserved[0x16];\r
-  UINT16  PcirOffset;\r
-} PCI_EXPANSION_ROM_HEADER;\r
-\r
-typedef struct {\r
-  UINT16  Signature;    // 0xaa55\r
-  UINT8   Size512;\r
-  UINT8   InitEntryPoint[3];\r
-  UINT8   Reserved[0x12];\r
-  UINT16  PcirOffset;\r
-} EFI_LEGACY_EXPANSION_ROM_HEADER;\r
-\r
-typedef struct {\r
-  UINT32  Signature;    // "PCIR"\r
-  UINT16  VendorId;\r
-  UINT16  DeviceId;\r
-  UINT16  Reserved0;\r
-  UINT16  Length;\r
-  UINT8   Revision;\r
-  UINT8   ClassCode[3];\r
-  UINT16  ImageLength;\r
-  UINT16  CodeRevision;\r
-  UINT8   CodeType;\r
-  UINT8   Indicator;\r
-  UINT16  Reserved1;\r
-} PCI_DATA_STRUCTURE;\r
-\r
 //\r
 // PCI Capability List IDs and records\r
 //\r
@@ -426,15 +436,13 @@ typedef struct {
 #define EFI_PCI_CAPABILITY_ID_SLOTID  0x04\r
 #define EFI_PCI_CAPABILITY_ID_MSI     0x05\r
 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
-#define EFI_PCI_CAPABILITY_ID_PCIX    0x07\r
-\r
 typedef struct {\r
   UINT8 CapabilityID;\r
   UINT8 NextItemPtr;\r
 } EFI_PCI_CAPABILITY_HDR;\r
 \r
 ///\r
-/// Capability EFI_PCI_CAPABILITY_ID_PMI\r
+/// Capability EFI_PCI_CAPABILITY_ID_PMI, defined in PCI Power Management Interface Specifiction\r
 ///\r
 typedef struct {\r
   EFI_PCI_CAPABILITY_HDR  Hdr;\r
@@ -445,7 +453,7 @@ typedef struct {
 } EFI_PCI_CAPABILITY_PMI;\r
 \r
 ///\r
-/// Capability EFI_PCI_CAPABILITY_ID_AGP\r
+/// Capability EFI_PCI_CAPABILITY_ID_AGP, defined in Accelerated Graphics Port Interface Specification\r
 ///\r
 typedef struct {\r
   EFI_PCI_CAPABILITY_HDR  Hdr;\r
@@ -456,7 +464,7 @@ typedef struct {
 } EFI_PCI_CAPABILITY_AGP;\r
 \r
 ///\r
-/// Capability EFI_PCI_CAPABILITY_ID_VPD\r
+/// Capability EFI_PCI_CAPABILITY_ID_VPD, in PCI2.2 Spec.\r
 ///\r
 typedef struct {\r
   EFI_PCI_CAPABILITY_HDR  Hdr;\r
@@ -465,7 +473,7 @@ typedef struct {
 } EFI_PCI_CAPABILITY_VPD;\r
 \r
 ///\r
-/// Capability EFI_PCI_CAPABILITY_ID_SLOTID\r
+/// Capability EFI_PCI_CAPABILITY_ID_SLOTID, defined in PCI-to-PCI Bridge Architeture Specification\r
 ///\r
 typedef struct {\r
   EFI_PCI_CAPABILITY_HDR  Hdr;\r
@@ -474,7 +482,7 @@ typedef struct {
 } EFI_PCI_CAPABILITY_SLOTID;\r
 \r
 ///\r
-/// Capability EFI_PCI_CAPABILITY_ID_MSI\r
+/// Capability EFI_PCI_CAPABILITY_ID_MSI, defined in PCI2.2\r
 ///\r
 typedef struct {\r
   EFI_PCI_CAPABILITY_HDR  Hdr;\r
@@ -492,7 +500,7 @@ typedef struct {
 } EFI_PCI_CAPABILITY_MSI64;\r
 \r
 ///\r
-/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG\r
+/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, defined in CompactPCI Hot Swap Specification PICMG 2.1, R1.0\r
 ///\r
 typedef struct {\r
   EFI_PCI_CAPABILITY_HDR  Hdr;\r
@@ -501,23 +509,6 @@ typedef struct {
   ///\r
 } EFI_PCI_CAPABILITY_HOTPLUG;\r
 \r
-///\r
-/// Capability EFI_PCI_CAPABILITY_ID_PCIX\r
-///\r
-typedef struct {\r
-  EFI_PCI_CAPABILITY_HDR  Hdr;\r
-  UINT16                  CommandReg;\r
-  UINT32                  StatusReg;\r
-} EFI_PCI_CAPABILITY_PCIX;\r
-\r
-typedef struct {\r
-  EFI_PCI_CAPABILITY_HDR  Hdr;\r
-  UINT16                  SecStatusReg;\r
-  UINT32                  StatusReg;\r
-  UINT32                  SplitTransCtrlRegUp;\r
-  UINT32                  SplitTransCtrlRegDn;\r
-} EFI_PCI_CAPABILITY_PCIX_BRDG;\r
-\r
 #define DEVICE_ID_NOCARE    0xFFFF\r
 \r
 #define PCI_ACPI_UNUSED     0\r
@@ -535,12 +526,11 @@ typedef struct {
 #define PCI_BAR_IDX5        0x05\r
 #define PCI_BAR_ALL         0xFF\r
 \r
-//\r
-// EFI PCI Option ROM definitions\r
-// \r
-\r
-#define EFI_ROOT_BRIDGE_LIST                            'eprb'\r
-#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE       0x0EF1\r
+///\r
+/// EFI PCI Option ROM definitions\r
+/// \r
+#define EFI_ROOT_BRIDGE_LIST                            'eprb'  \r
+#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE       0x0EF1  ///< defined in UEFI Spec.\r
 \r
 typedef struct {\r
   UINT8 Register;\r
@@ -550,10 +540,47 @@ typedef struct {
   UINT8 Reserved[4];\r
 } DEFIO_PCI_ADDR;\r
 \r
+#define PCI_EXPANSION_ROM_HEADER_SIGNATURE              0xaa55\r
+#define PCI_DATA_STRUCTURE_SIGNATURE                    EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')\r
+#define PCI_CODE_TYPE_PCAT_IMAGE                        0x00\r
+#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED         0x0001  ///<defined in UEFI spec.\r
+\r
+typedef struct {\r
+  UINT16  Signature;    ///< 0xaa55\r
+  UINT8   Reserved[0x16];\r
+  UINT16  PcirOffset;\r
+} PCI_EXPANSION_ROM_HEADER;\r
+\r
+typedef struct {\r
+  UINT16  Signature;    ///< 0xaa55\r
+  UINT8   Size512;\r
+  UINT8   InitEntryPoint[3];\r
+  UINT8   Reserved[0x12];\r
+  UINT16  PcirOffset;\r
+} EFI_LEGACY_EXPANSION_ROM_HEADER;\r
+\r
+typedef struct {\r
+  UINT32  Signature;    ///< "PCIR"\r
+  UINT16  VendorId;\r
+  UINT16  DeviceId;\r
+  UINT16  Reserved0;\r
+  UINT16  Length;\r
+  UINT8   Revision;\r
+  UINT8   ClassCode[3];\r
+  UINT16  ImageLength;\r
+  UINT16  CodeRevision;\r
+  UINT8   CodeType;\r
+  UINT8   Indicator;\r
+  UINT16  Reserved1;\r
+} PCI_DATA_STRUCTURE;\r
+\r
+///\r
+/// defined in EFI/UEFI Spec\r
+///\r
 typedef struct {\r
-  UINT16  Signature;    // 0xaa55\r
+  UINT16  Signature;    ///< 0xaa55\r
   UINT16  InitializationSize;\r
-  UINT32  EfiSignature; // 0x0EF1\r
+  UINT32  EfiSignature; ///< 0x0EF1\r
   UINT16  EfiSubsystem;\r
   UINT16  EfiMachineType;\r
   UINT16  CompressionType;\r

diff --git a/MdePkg/Include/IndustryStandard/Pci23.h b/MdePkg/Include/IndustryStandard/Pci23.h
index 6ddd6970cd39bead1269bb2a1e3878615d29bcdc..e1289f75c610127546ead10bf64e07197afd55d6 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Pci23.h
+++ b/MdePkg/Include/IndustryStandard/Pci23.h
@@ -1,7 +1,7 @@
 /** @file\r
   Support for PCI 2.3 standard.\r
 \r
-  Copyright (c) 2006, Intel Corporation                                                         \r
+  Copyright (c) 2006 - 2008, Intel Corporation                                                         \r
   All rights reserved. This program and the accompanying materials                          \r
   are licensed and made available under the terms and conditions of the BSD License         \r
   which accompanies this distribution.  The full text of the license may be found at        \r
@@ -15,10 +15,46 @@
 #ifndef _PCI23_H_\r
 #define _PCI23_H_\r
 \r
+#include <IndustryStandard/Pci22.h>\r
+\r
+///\r
+/// Definitions of PCI class bytes and manipulation macros.\r
+///\r
+#define PCI_IF_EHCI                   0x20\r
 \r
+///\r
+/// defined in PCI Express Spec.\r
+///\r
 #define PCI_EXP_MAX_CONFIG_OFFSET     0x1000\r
-#define EFI_PCI_CAPABILITY_ID_PCIEXP  0x10\r
 \r
-#include <IndustryStandard/Pci22.h>\r
+//\r
+// PCI Capability List IDs and records\r
+//\r
+#define EFI_PCI_CAPABILITY_ID_PCIX    0x07\r
+\r
+#pragma pack(1)\r
+///\r
+/// Capability EFI_PCI_CAPABILITY_ID_PCIX, defined in PCI-X Addendum to the PCI Local Bus Specification\r
+///\r
+typedef struct {\r
+  EFI_PCI_CAPABILITY_HDR  Hdr;\r
+  UINT16                  CommandReg;\r
+  UINT32                  StatusReg;\r
+} EFI_PCI_CAPABILITY_PCIX;\r
+\r
+/// \r
+/// Capability EFI_PCI_CAPABILITY_PCIX_BRDG, defined in PCI-X Addendum to the PCI Local Bus Specification\r
+///\r
+typedef struct {\r
+  EFI_PCI_CAPABILITY_HDR  Hdr;\r
+  UINT16                  SecStatusReg;\r
+  UINT32                  StatusReg;\r
+  UINT32                  SplitTransCtrlRegUp;\r
+  UINT32                  SplitTransCtrlRegDn;\r
+} EFI_PCI_CAPABILITY_PCIX_BRDG;\r
+\r
+#pragma pack()\r
+\r
+#define PCI_CODE_TYPE_EFI_IMAGE       0x03\r
 \r
 #endif\r

diff --git a/MdePkg/Include/IndustryStandard/Pci30.h b/MdePkg/Include/IndustryStandard/Pci30.h
index 0cd37c44bdd7c595237501de570d60e3aa812570..3bcf2327f143e15832727feb1bf8269115642406 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Pci30.h
+++ b/MdePkg/Include/IndustryStandard/Pci30.h
@@ -1,7 +1,7 @@
 /** @file\r
   Support for PCI 3.0 standard.\r
 \r
-  Copyright (c) 2006, Intel Corporation                                                         \r
+  Copyright (c) 2006 - 2008, Intel Corporation                                                         \r
   All rights reserved. This program and the accompanying materials                          \r
   are licensed and made available under the terms and conditions of the BSD License         \r
   which accompanies this distribution.  The full text of the license may be found at        \r
@@ -15,13 +15,28 @@
 #ifndef __PCI30_H__\r
 #define __PCI30_H__\r
 \r
+\r
+#include <IndustryStandard/Pci23.h>\r
+\r
+///\r
+/// Definitions of PCI class bytes and manipulation macros.\r
+///\r
 #define PCI_CLASS_MASS_STORAGE_SATADPA   0x06\r
-#define PCI_CLASS_MASS_STORAGE_AHCI      PCI_CLASS_MASS_STORAGE_SATADPA\r
+#define   PCI_IF_MASS_STORAGE_SATA         0x00\r
+#define   PCI_IF_MASS_STORAGE_AHCI         0x01\r
+\r
+///\r
+/// PCI Capability List IDs and records\r
+///\r
+#define EFI_PCI_CAPABILITY_ID_PCIEXP  0x10\r
 \r
 #pragma pack(1)\r
 \r
+///\r
+/// defined in PCI Firmware Specification\r
+///\r
 typedef struct {\r
-  UINT32  Signature;    // "PCIR"\r
+  UINT32  Signature;    ///< "PCIR"\r
   UINT16  VendorId;\r
   UINT16  DeviceId;\r
   UINT16  DeviceListOffset;\r
@@ -39,7 +54,4 @@ typedef struct {
 \r
 #pragma pack()\r
 \r
-\r
-#include <IndustryStandard/Pci23.h>\r
-\r
 #endif\r

diff --git a/OptionRomPkg/AtapiPassThruDxe/AtapiPassThru.c b/OptionRomPkg/AtapiPassThruDxe/AtapiPassThru.c
index ac12be4ee048aed5d5406620043e568f782d2a3c..f3288eb4ecaeb248dbb1401278583172011885c2 100644 (file)
--- a/OptionRomPkg/AtapiPassThruDxe/AtapiPassThru.c
+++ b/OptionRomPkg/AtapiPassThruDxe/AtapiPassThru.c
@@ -163,7 +163,7 @@ Returns:
     return EFI_UNSUPPORTED;\r
   }\r
 \r
-  if (Pci.Hdr.ClassCode[2] != PCI_CLASS_MASS_STORAGE || Pci.Hdr.ClassCode[1] != PCI_CLASS_IDE) {\r
+  if (Pci.Hdr.ClassCode[2] != PCI_CLASS_MASS_STORAGE || Pci.Hdr.ClassCode[1] != PCI_CLASS_MASS_STORAGE_IDE) {\r
 \r
     Status = EFI_UNSUPPORTED;\r
   }\r