All POWER_MGMT_REGISTER_Q35() macro invocations in OvmfPkg should use the
macros in "Q35MchIch9.h" as arguments.
Cc: Gabriel Somlo <somlo@cmu.edu>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17434
6f19259b-4bc3-4df7-8a09-
765794883524
//\r
#define PMBA_RTE BIT0\r
#define PIIX4_PMIOSE BIT0\r
-#define Q35_ACPI_EN BIT7\r
\r
//\r
// Offset in the Power Management Base Address to the ACPI Timer\r
AcpiEnBit = PIIX4_PMIOSE;\r
break;\r
case INTEL_Q35_MCH_DEVICE_ID:\r
- Pmba = POWER_MGMT_REGISTER_Q35 (0x40);\r
- AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (0x44); // ACPI_CNTL\r
- AcpiEnBit = Q35_ACPI_EN;\r
+ Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
+ AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
+ AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
break;\r
default:\r
DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
//\r
#define PMBA_RTE BIT0\r
#define PIIX4_PMIOSE BIT0\r
-#define Q35_ACPI_EN BIT7\r
\r
//\r
// Offset in the Power Management Base Address to the ACPI Timer\r
AcpiEnBit = PIIX4_PMIOSE;\r
break;\r
case INTEL_Q35_MCH_DEVICE_ID:\r
- Pmba = POWER_MGMT_REGISTER_Q35 (0x40);\r
- AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (0x44); // ACPI_CNTL\r
- AcpiEnBit = Q35_ACPI_EN;\r
+ Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
+ AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
+ AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
break;\r
default:\r
DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
break;\r
case INTEL_Q35_MCH_DEVICE_ID:\r
- Pmba = POWER_MGMT_REGISTER_Q35 (0x40);\r
+ Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
break;\r
default:\r
DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
break;\r
case INTEL_Q35_MCH_DEVICE_ID:\r
- Pmba = POWER_MGMT_REGISTER_Q35 (0x40);\r
+ Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
break;\r
default:\r
DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x63), 0x0a); // D\r
break;\r
case INTEL_Q35_MCH_DEVICE_ID:\r
- Pmba = POWER_MGMT_REGISTER_Q35 (0x40);\r
+ Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
//\r
// 00:1f.0 LPC Bridge (Q35) LNK routing targets\r
//\r
break;\r
case INTEL_Q35_MCH_DEVICE_ID:\r
PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
- Pmba = POWER_MGMT_REGISTER_Q35 (0x40);\r
- AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (0x44); // ACPI_CNTL\r
- AcpiEnBit = BIT7; // Q35_ACPI_EN\r
+ Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
+ AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
+ AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
break;\r
default:\r
DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r