--*/\r
\r
#include "CpuDxe.h"\r
-//FIXME: Remove this ARMv7 specific header\r
-#include <Chipset/ArmV7.h>\r
\r
// First Level Descriptors\r
typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;\r
/** @file\r
\r
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+ Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r
#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))\r
\r
-// Cortex A9 feature bit definitions\r
-#define A9_FEATURE_PARITY (1<<9)\r
-#define A9_FEATURE_AOW (1<<8)\r
-#define A9_FEATURE_EXCL (1<<7)\r
-#define A9_FEATURE_SMP (1<<6)\r
-#define A9_FEATURE_FOZ (1<<3)\r
-#define A9_FEATURE_DPREF (1<<2)\r
-#define A9_FEATURE_HINT (1<<1)\r
-#define A9_FEATURE_FWD (1<<0)\r
-\r
-// SCU register offsets & masks\r
-#define SCU_CONTROL_OFFSET 0x0\r
-#define SCU_CONFIG_OFFSET 0x4\r
-#define SCU_INVALL_OFFSET 0xC\r
-#define SCU_FILT_START_OFFSET 0x40\r
-#define SCU_FILT_END_OFFSET 0x44\r
-#define SCU_SACR_OFFSET 0x50\r
-#define SCU_SSACR_OFFSET 0x54\r
-\r
-#define SMP_GIC_CPUIF_BASE 0x100\r
-#define SMP_GIC_DIST_BASE 0x1000\r
-\r
// CPACR - Coprocessor Access Control Register definitions\r
#define CPACR_CP_DENIED(cp) 0x00\r
#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)\r
#define SCR_FW (1 << 4)\r
#define SCR_AW (1 << 5)\r
\r
-VOID\r
-EFIAPI\r
-ArmEnableSWPInstruction (\r
- VOID\r
- );\r
+// MIDR - Main ID Register definitions\r
+#define ARM_CPU_TYPE_MASK 0xFFF\r
+#define ARM_CPU_TYPE_A15 0xC0F\r
+#define ARM_CPU_TYPE_A9 0xC09\r
+#define ARM_CPU_TYPE_A5 0xC05\r
\r
VOID\r
EFIAPI\r
-ArmWriteNsacr (\r
- IN UINT32 SetWayFormat\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteScr (\r
- IN UINT32 SetWayFormat\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteVMBar (\r
- IN UINT32 SetWayFormat\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteVBar (\r
- IN UINT32 SetWayFormat\r
- );\r
-\r
-UINT32\r
-EFIAPI\r
-ArmReadVBar (\r
- VOID\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteCPACR (\r
- IN UINT32 SetWayFormat\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmEnableVFP (\r
- VOID\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmCallWFI (\r
- VOID\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmInvalidScu (\r
- VOID\r
- );\r
-\r
-UINTN\r
-EFIAPI\r
-ArmGetScuBaseAddress (\r
- VOID\r
- );\r
-\r
-UINT32\r
-EFIAPI\r
-ArmIsScuEnable (\r
- VOID\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteAuxCr (\r
- IN UINT32 Bit\r
- );\r
-\r
-UINT32\r
-EFIAPI\r
-ArmReadAuxCr (\r
+ArmEnableSWPInstruction (\r
VOID\r
);\r
\r
-VOID\r
-EFIAPI\r
-ArmSetAuxCrBit (\r
- IN UINT32 Bits\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmSetupSmpNonSecure (\r
- IN UINTN CoreId\r
- );\r
-\r
UINTN \r
EFIAPI\r
ArmReadCbar (\r
VOID\r
);\r
\r
-VOID\r
-EFIAPI\r
-ArmInvalidateInstructionAndDataTlb (\r
- VOID\r
- );\r
-\r
-\r
-UINTN\r
-EFIAPI\r
-ArmReadMpidr (\r
- VOID\r
- );\r
-\r
UINTN\r
EFIAPI\r
ArmReadTpidrurw (\r
UINTN Value\r
);\r
\r
+UINTN\r
+EFIAPI\r
+ArmReadIdPfr1 (\r
+ VOID\r
+ );\r
+ \r
#endif // __ARM_V7_H__\r
#ifndef __ARM_LIB__
#define __ARM_LIB__
+#ifdef ARM_CPU_ARMv6
+#include <Chipset/ARM1176JZ-S.h>
+#else
+#include <Chipset/ArmV7.h>
+#endif
+
typedef enum {
ARM_CACHE_TYPE_WRITE_BACK,
ARM_CACHE_TYPE_UNKNOWN
VOID
);
+VOID
+EFIAPI
+ArmInvalidateInstructionAndDataTlb (
+ VOID
+ );
+
VOID
EFIAPI
ArmEnableInterrupts (
ArmInstructionSynchronizationBarrier (
VOID
);
-
+
+VOID
+EFIAPI
+ArmWriteVBar (
+ IN UINT32 VectorBase
+ );
+
+UINT32
+EFIAPI
+ArmReadVBar (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteAuxCr (
+ IN UINT32 Bit
+ );
+
+UINT32
+EFIAPI
+ArmReadAuxCr (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmSetAuxCrBit (
+ IN UINT32 Bits
+ );
+
+VOID
+EFIAPI
+ArmCallWFI (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmReadMpidr (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCPACR (
+ IN UINT32 Access
+ );
+
+VOID
+EFIAPI
+ArmEnableVFP (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteNsacr (
+ IN UINT32 SetWayFormat
+ );
+
+VOID
+EFIAPI
+ArmWriteScr (
+ IN UINT32 SetWayFormat
+ );
+
+VOID
+EFIAPI
+ArmWriteVMBar (
+ IN UINT32 VectorMonitorBase
+ );
#endif // __ARM_LIB__
+++ /dev/null
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-#include <AsmMacroIoLib.h>
-
-.text
-.align 2
-
-GCC_ASM_EXPORT(Cp15IdCode)
-GCC_ASM_EXPORT(Cp15CacheInfo)
-GCC_ASM_EXPORT(ArmIsMPCore)
-GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)
-GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)
-GCC_ASM_EXPORT(ArmEnableIrq)
-GCC_ASM_EXPORT(ArmDisableIrq)
-GCC_ASM_EXPORT(ArmGetInterruptState)
-GCC_ASM_EXPORT(ArmEnableFiq)
-GCC_ASM_EXPORT(ArmDisableFiq)
-GCC_ASM_EXPORT(ArmEnableInterrupts)
-GCC_ASM_EXPORT(ArmDisableInterrupts)
-GCC_ASM_EXPORT(ArmGetFiqState)
-GCC_ASM_EXPORT(ArmInvalidateTlb)
-GCC_ASM_EXPORT(ArmSetTTBR0)
-GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
-GCC_ASM_EXPORT(ArmSetDomainAccessControl)
-GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
-GCC_ASM_EXPORT(CPSRMaskInsert)
-GCC_ASM_EXPORT(CPSRRead)
-GCC_ASM_EXPORT(ReadCCSIDR)
-GCC_ASM_EXPORT(ReadCLIDR)
-
-
-
-#------------------------------------------------------------------------------
-
-ASM_PFX(Cp15IdCode):
- mrc p15,0,R0,c0,c0,0
- bx LR
-
-ASM_PFX(Cp15CacheInfo):
- mrc p15,0,R0,c0,c0,1
- bx LR
-
-ASM_PFX(ArmIsMPCore):
- mrc p15,0,R0,c0,c0,5
- // Get Multiprocessing extension (bit31) & U bit (bit30)
- and R0, R0, #0xC0000000
- // if bit30 == 0 then the processor is part of a multiprocessor system)
- and R0, R0, #0x80000000
- bx LR
-
-ASM_PFX(ArmEnableAsynchronousAbort):
- cpsie a
- isb
- bx LR
-
-ASM_PFX(ArmDisableAsynchronousAbort):
- cpsid a
- isb
- bx LR
-
-ASM_PFX(ArmEnableIrq):
- cpsie i
- isb
- bx LR
-
-ASM_PFX(ArmDisableIrq):
- cpsid i
- isb
- bx LR
-
-ASM_PFX(ArmGetInterruptState):
- mrs R0,CPSR
- tst R0,#0x80 @Check if IRQ is enabled.
- moveq R0,#1
- movne R0,#0
- bx LR
-
-ASM_PFX(ArmEnableFiq):
- cpsie f
- isb
- bx LR
-
-ASM_PFX(ArmDisableFiq):
- cpsid f
- isb
- bx LR
-
-ASM_PFX(ArmEnableInterrupts):
- cpsie if
- isb
- bx LR
-
-ASM_PFX(ArmDisableInterrupts):
- cpsid if
- isb
- bx LR
-
-ASM_PFX(ArmGetFiqState):
- mrs R0,CPSR
- tst R0,#0x40 @Check if FIQ is enabled.
- moveq R0,#1
- movne R0,#0
- bx LR
-
-ASM_PFX(ArmInvalidateTlb):
- mov r0,#0
- mcr p15,0,r0,c8,c7,0
- mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
- dsb
- isb
- bx lr
-
-ASM_PFX(ArmSetTTBR0):
- mcr p15,0,r0,c2,c0,0
- isb
- bx lr
-
-ASM_PFX(ArmGetTTBR0BaseAddress):
- mrc p15,0,r0,c2,c0,0
- LoadConstantToReg(0xFFFFC000, r1)
- and r0, r0, r1
- isb
- bx lr
-
-
-ASM_PFX(ArmSetDomainAccessControl):
- mcr p15,0,r0,c3,c0,0
- isb
- bx lr
-
-//
-//VOID
-//ArmUpdateTranslationTableEntry (
-// IN VOID *TranslationTableEntry // R0
-// IN VOID *MVA // R1
-// );
-ASM_PFX(ArmUpdateTranslationTableEntry):
- mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA
- dsb
- mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
- mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
- dsb
- isb
- bx lr
-
-ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
- stmfd sp!, {r4-r12, lr} @ save all the banked registers
- mov r3, sp @ copy the stack pointer into a non-banked register
- mrs r2, cpsr @ read the cpsr
- bic r2, r2, r0 @ clear mask in the cpsr
- and r1, r1, r0 @ clear bits outside the mask in the input
- orr r2, r2, r1 @ set field
- msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
- isb
- mov sp, r3 @ restore stack pointer
- ldmfd sp!, {r4-r12, lr} @ restore registers
- bx lr @ return (hopefully thumb-safe!)
-
-ASM_PFX(CPSRRead):
- mrs r0, cpsr
- bx lr
-
-// UINT32
-// ReadCCSIDR (
-// IN UINT32 CSSELR
-// )
-ASM_PFX(ReadCCSIDR):
- mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
- isb
- mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
- bx lr
-
-// UINT32
-// ReadCLIDR (
-// IN UINT32 CSSELR
-// )
-ASM_PFX(ReadCLIDR):
- mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
- bx lr
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
+++ /dev/null
-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//------------------------------------------------------------------------------
-
-
- EXPORT Cp15IdCode
- EXPORT Cp15CacheInfo
- EXPORT ArmIsMPCore
- EXPORT ArmEnableAsynchronousAbort
- EXPORT ArmDisableAsynchronousAbort
- EXPORT ArmEnableIrq
- EXPORT ArmDisableIrq
- EXPORT ArmGetInterruptState
- EXPORT ArmEnableFiq
- EXPORT ArmDisableFiq
- EXPORT ArmEnableInterrupts
- EXPORT ArmDisableInterrupts
- EXPORT ArmGetFiqState
- EXPORT ArmInvalidateTlb
- EXPORT ArmSetTTBR0
- EXPORT ArmGetTTBR0BaseAddress
- EXPORT ArmSetDomainAccessControl
- EXPORT ArmUpdateTranslationTableEntry
- EXPORT CPSRMaskInsert
- EXPORT CPSRRead
- EXPORT ReadCCSIDR
- EXPORT ReadCLIDR
-
- AREA ArmLibSupport, CODE, READONLY
-
-
-//------------------------------------------------------------------------------
-
-Cp15IdCode
- mrc p15,0,R0,c0,c0,0
- bx LR
-
-Cp15CacheInfo
- mrc p15,0,R0,c0,c0,1
- bx LR
-
-ArmIsMPCore
- mrc p15,0,R0,c0,c0,5
- // Get Multiprocessing extension (bit31) & U bit (bit30)
- and R0, R0, #0xC0000000
- // if bit30 == 0 then the processor is part of a multiprocessor system)
- and R0, R0, #0x80000000
- bx LR
-
-ArmEnableAsynchronousAbort
- cpsie a
- isb
- bx LR
-
-ArmDisableAsynchronousAbort
- cpsid a
- isb
- bx LR
-
-ArmEnableIrq
- cpsie i
- isb
- bx LR
-
-ArmDisableIrq
- cpsid i
- isb
- bx LR
-
-ArmEnableFiq
- cpsie f
- isb
- bx LR
-
-ArmDisableFiq
- cpsid f
- isb
- bx LR
-
-ArmEnableInterrupts
- cpsie if
- isb
- bx LR
-
-ArmDisableInterrupts
- cpsid if
- isb
- bx LR
-
-ArmGetInterruptState
- mrs R0,CPSR
- tst R0,#0x80 ;Check if IRQ is enabled.
- moveq R0,#1
- movne R0,#0
- bx LR
-
-ArmGetFiqState
- mrs R0,CPSR
- tst R0,#0x40 ;Check if FIQ is enabled.
- moveq R0,#1
- movne R0,#0
- bx LR
-
-ArmInvalidateTlb
- mov r0,#0
- mcr p15,0,r0,c8,c7,0
- mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp
- dsb
- isb
- bx lr
-
-ArmSetTTBR0
- mcr p15,0,r0,c2,c0,0
- isb
- bx lr
-
-ArmGetTTBR0BaseAddress
- mrc p15,0,r0,c2,c0,0
- ldr r1, = 0xFFFFC000
- and r0, r0, r1
- isb
- bx lr
-
-
-ArmSetDomainAccessControl
- mcr p15,0,r0,c3,c0,0
- isb
- bx lr
-
-//
-//VOID
-//ArmUpdateTranslationTableEntry (
-// IN VOID *TranslationTableEntry // R0
-// IN VOID *MVA // R1
-// );
-ArmUpdateTranslationTableEntry
- mcr p15,0,R0,c7,c14,1 ; DCCIMVAC Clean data cache by MVA
- dsb
- mcr p15,0,R1,c8,c7,1 ; TLBIMVA TLB Invalidate MVA
- mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp
- dsb
- isb
- bx lr
-
-CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
- stmfd sp!, {r4-r12, lr} ; save all the banked registers
- mov r3, sp ; copy the stack pointer into a non-banked register
- mrs r2, cpsr ; read the cpsr
- bic r2, r2, r0 ; clear mask in the cpsr
- and r1, r1, r0 ; clear bits outside the mask in the input
- orr r2, r2, r1 ; set field
- msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
- isb
- mov sp, r3 ; restore stack pointer
- ldmfd sp!, {r4-r12, lr} ; restore registers
- bx lr ; return (hopefully thumb-safe!)
-
-CPSRRead
- mrs r0, cpsr
- bx lr
-
-
-// UINT32
-// ReadCCSIDR (
-// IN UINT32 CSSELR
-// )
-ReadCCSIDR
- mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
- isb
- mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
- bx lr
-
-
-// UINT32
-// ReadCLIDR (
-// IN UINT32 CSSELR
-// )
-ReadCLIDR
- mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
- bx lr
-
-END
--- /dev/null
+#------------------------------------------------------------------------------ \r
+#\r
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+\r
+.text\r
+.align 2\r
+\r
+GCC_ASM_EXPORT(ArmIsMpCore)\r
+GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)\r
+GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)\r
+GCC_ASM_EXPORT(ArmEnableIrq)\r
+GCC_ASM_EXPORT(ArmDisableIrq)\r
+GCC_ASM_EXPORT(ArmEnableFiq)\r
+GCC_ASM_EXPORT(ArmDisableFiq)\r
+GCC_ASM_EXPORT(ArmEnableInterrupts)\r
+GCC_ASM_EXPORT(ArmDisableInterrupts)\r
+GCC_ASM_EXPORT(ReadCCSIDR)\r
+GCC_ASM_EXPORT(ReadCLIDR)\r
+\r
+#------------------------------------------------------------------------------\r
+\r
+ASM_PFX(ArmIsMpCore):\r
+ mrc p15,0,R0,c0,c0,5\r
+ // Get Multiprocessing extension (bit31) & U bit (bit30)\r
+ and R0, R0, #0xC0000000\r
+ // if bit30 == 0 then the processor is part of a multiprocessor system)\r
+ and R0, R0, #0x80000000\r
+ bx LR\r
+\r
+ASM_PFX(ArmEnableAsynchronousAbort):\r
+ cpsie a\r
+ isb\r
+ bx LR\r
+\r
+ASM_PFX(ArmDisableAsynchronousAbort):\r
+ cpsid a\r
+ isb\r
+ bx LR\r
+\r
+ASM_PFX(ArmEnableIrq):\r
+ cpsie i\r
+ isb\r
+ bx LR\r
+\r
+ASM_PFX(ArmDisableIrq):\r
+ cpsid i\r
+ isb\r
+ bx LR\r
+\r
+ASM_PFX(ArmEnableFiq):\r
+ cpsie f\r
+ isb\r
+ bx LR\r
+\r
+ASM_PFX(ArmDisableFiq):\r
+ cpsid f\r
+ isb\r
+ bx LR\r
+\r
+ASM_PFX(ArmEnableInterrupts):\r
+ cpsie if\r
+ isb\r
+ bx LR\r
+\r
+ASM_PFX(ArmDisableInterrupts):\r
+ cpsid if\r
+ isb\r
+ bx LR\r
+ \r
+// UINT32 \r
+// ReadCCSIDR (\r
+// IN UINT32 CSSELR\r
+// ) \r
+ASM_PFX(ReadCCSIDR):\r
+ mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)\r
+ isb\r
+ mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)\r
+ bx lr\r
+ \r
+// UINT32 \r
+// ReadCLIDR (\r
+// IN UINT32 CSSELR\r
+// ) \r
+ASM_PFX(ReadCLIDR):\r
+ mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register\r
+ bx lr\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
--- /dev/null
+//------------------------------------------------------------------------------ \r
+//\r
+// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+ EXPORT ArmIsMpCore\r
+ EXPORT ArmEnableAsynchronousAbort\r
+ EXPORT ArmDisableAsynchronousAbort\r
+ EXPORT ArmEnableIrq\r
+ EXPORT ArmDisableIrq\r
+ EXPORT ArmEnableFiq\r
+ EXPORT ArmDisableFiq\r
+ EXPORT ArmEnableInterrupts\r
+ EXPORT ArmDisableInterrupts\r
+ EXPORT ReadCCSIDR\r
+ EXPORT ReadCLIDR\r
+ \r
+ AREA ArmLibSupportV7, CODE, READONLY\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+ArmIsMpCore\r
+ mrc p15,0,R0,c0,c0,5\r
+ // Get Multiprocessing extension (bit31) & U bit (bit30)\r
+ and R0, R0, #0xC0000000\r
+ // if bit30 == 0 then the processor is part of a multiprocessor system)\r
+ and R0, R0, #0x80000000\r
+ bx LR\r
+\r
+ArmEnableAsynchronousAbort\r
+ cpsie a\r
+ isb\r
+ bx LR\r
+\r
+ArmDisableAsynchronousAbort\r
+ cpsid a\r
+ isb\r
+ bx LR\r
+\r
+ArmEnableIrq\r
+ cpsie i\r
+ isb\r
+ bx LR\r
+\r
+ArmDisableIrq\r
+ cpsid i\r
+ isb\r
+ bx LR\r
+\r
+ArmEnableFiq\r
+ cpsie f\r
+ isb\r
+ bx LR\r
+\r
+ArmDisableFiq\r
+ cpsid f\r
+ isb\r
+ bx LR\r
+\r
+ArmEnableInterrupts\r
+ cpsie if\r
+ isb\r
+ bx LR\r
+\r
+ArmDisableInterrupts\r
+ cpsid if\r
+ isb\r
+ bx LR\r
+ \r
+// UINT32 \r
+// ReadCCSIDR (\r
+// IN UINT32 CSSELR\r
+// ) \r
+ReadCCSIDR\r
+ mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)\r
+ isb\r
+ mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)\r
+ bx lr\r
+ \r
+// UINT32 \r
+// ReadCLIDR (\r
+// IN UINT32 CSSELR\r
+// ) \r
+ReadCLIDR\r
+ mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register\r
+ bx lr\r
+ \r
+END\r
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
}
-VOID
-EFIAPI
-ArmSetAuxCrBit (
- IN UINT32 Bits
- )
-{
- UINT32 val = ArmReadAuxCr();
- val |= Bits;
- ArmWriteAuxCr(val);
-}
-/** @file
-
- Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __ARM_V7_LIB_H__
-#define __ARM_V7_LIB_H__
-
-
-VOID
-EFIAPI
-ArmDrainWriteBuffer (
- VOID
- );
-
-VOID
-EFIAPI
-ArmInvalidateDataCacheEntryBySetWay (
- IN UINT32 SetWayFormat
- );
-
-VOID
-EFIAPI
-ArmCleanDataCacheEntryBySetWay (
- IN UINT32 SetWayFormat
- );
-
-VOID
-EFIAPI
-ArmCleanInvalidateDataCacheEntryBySetWay (
- IN UINT32 SetWayFormat
- );
-
-VOID
-EFIAPI
-ArmEnableAsynchronousAbort (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmDisableAsynchronousAbort (
- VOID
- );
-
-VOID
-EFIAPI
-ArmEnableIrq (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmDisableIrq (
- VOID
- );
-
-VOID
-EFIAPI
-ArmEnableFiq (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmDisableFiq (
- VOID
- );
-
-#endif // __ARM_V7_LIB_H__
-
+/** @file\r
+\r
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __ARM_V7_LIB_H__\r
+#define __ARM_V7_LIB_H__\r
+\r
+\r
+VOID\r
+EFIAPI\r
+ArmDrainWriteBuffer (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmInvalidateDataCacheEntryBySetWay (\r
+ IN UINT32 SetWayFormat\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanDataCacheEntryBySetWay (\r
+ IN UINT32 SetWayFormat\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanInvalidateDataCacheEntryBySetWay (\r
+ IN UINT32 SetWayFormat\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmEnableAsynchronousAbort (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmDisableAsynchronousAbort (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmEnableIrq (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmDisableIrq (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmEnableFiq (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmDisableFiq (\r
+ VOID\r
+ );\r
+\r
+#endif // __ARM_V7_LIB_H__\r
+\r
#/** @file\r
-# Semihosting serail port lib\r
#\r
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
LIBRARY_CLASS = ArmLib\r
\r
[Sources.common]\r
- ArmLibSupport.S | GCC\r
- ArmLibSupport.asm | RVCT\r
+ ArmLibSupportV7.S | GCC\r
+ ArmLibSupportV7.asm | RVCT\r
+\r
+ ../Common/ArmLibSupport.S | GCC\r
+ ../Common/ArmLibSupport.asm | RVCT\r
../Common/ArmLib.c\r
\r
ArmV7Support.S | GCC\r
ArmV7Support.asm | RVCT\r
-\r
+ \r
ArmV7Lib.c\r
ArmV7Mmu.c\r
\r
LIBRARY_CLASS = ArmLib\r
\r
[Sources.common]\r
- ArmLibSupport.S | GCC\r
- ArmLibSupport.asm | RVCT\r
+ ArmLibSupportV7.S | GCC\r
+ ArmLibSupportV7.asm | RVCT\r
+\r
+ ../Common/ArmLibSupport.S | GCC\r
+ ../Common/ArmLibSupport.asm | RVCT\r
../Common/ArmLib.c\r
\r
ArmV7Support.S | GCC\r
ArmV7Support.asm | RVCT\r
-\r
+ \r
ArmV7Lib.c\r
ArmV7Mmu.c\r
\r
LIBRARY_CLASS = ArmLib\r
\r
[Sources.common]\r
- ArmLibSupport.S | GCC\r
- ArmLibSupport.asm | RVCT\r
+ ArmLibSupportV7.S | GCC\r
+ ArmLibSupportV7.asm | RVCT\r
+\r
+ ../Common/ArmLibSupport.S | GCC\r
+ ../Common/ArmLibSupport.asm | RVCT\r
../Common/ArmLib.c\r
\r
ArmV7Support.S | GCC\r
IN UINT32 PhysicalBase,\r
IN UINT32 RemainLength,\r
IN ARM_MEMORY_REGION_ATTRIBUTES Attributes\r
- ) {\r
+ )\r
+{\r
UINT32* PageEntry;\r
UINT32 Pages;\r
UINT32 Index;\r
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;\r
} else {\r
// Case: Physical address aligned on the Section Size (1MB) && the length does not fill a section\r
- PopulateLevel2PageTable(SectionEntry++,PhysicalBase,RemainLength,MemoryRegion->Attributes);\r
+ PopulateLevel2PageTable (SectionEntry++, PhysicalBase, RemainLength, MemoryRegion->Attributes);\r
\r
// It must be the last entry\r
break;\r
}\r
} else {\r
// Case: Physical address NOT aligned on the Section Size (1MB)\r
- PopulateLevel2PageTable(SectionEntry++,PhysicalBase,RemainLength,MemoryRegion->Attributes);\r
+ PopulateLevel2PageTable (SectionEntry++, PhysicalBase, RemainLength, MemoryRegion->Attributes);\r
// Aligned the address\r
PhysicalBase = (PhysicalBase + TT_DESCRIPTOR_SECTION_SIZE) & ~(TT_DESCRIPTOR_SECTION_SIZE-1);\r
\r
UINT32 TTBRAttributes;\r
\r
// Allocate pages for translation table.\r
- TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SECTION_SIZE + TRANSLATION_TABLE_SECTION_ALIGNMENT));\r
+ TranslationTable = (UINTN)AllocatePages (EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SECTION_SIZE + TRANSLATION_TABLE_SECTION_ALIGNMENT));\r
TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK;\r
\r
if (TranslationTableBase != NULL) {\r
\r
ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);\r
\r
- ArmCleanInvalidateDataCache();\r
- ArmInvalidateInstructionCache();\r
- ArmInvalidateTlb();\r
+ ArmCleanInvalidateDataCache ();\r
+ ArmInvalidateInstructionCache ();\r
+ ArmInvalidateTlb ();\r
\r
- ArmDisableDataCache();\r
+ ArmDisableDataCache ();\r
ArmDisableInstructionCache();\r
- ArmDisableMmu();\r
+ ArmDisableMmu ();\r
\r
// Make sure nothing sneaked into the cache\r
- ArmCleanInvalidateDataCache();\r
- ArmInvalidateInstructionCache();\r
+ ArmCleanInvalidateDataCache ();\r
+ ArmInvalidateInstructionCache ();\r
\r
TranslationTableAttribute = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
while (MemoryTable->Length != 0) {\r
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-.text
-.align 2
-
-GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
-GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
-GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
-GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
-GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
-GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
-GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
-GCC_ASM_EXPORT (ArmDrainWriteBuffer)
-GCC_ASM_EXPORT (ArmEnableMmu)
-GCC_ASM_EXPORT (ArmDisableMmu)
-GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
-GCC_ASM_EXPORT (ArmMmuEnabled)
-GCC_ASM_EXPORT (ArmEnableDataCache)
-GCC_ASM_EXPORT (ArmDisableDataCache)
-GCC_ASM_EXPORT (ArmEnableInstructionCache)
-GCC_ASM_EXPORT (ArmDisableInstructionCache)
-GCC_ASM_EXPORT (ArmEnableSWPInstruction)
-GCC_ASM_EXPORT (ArmEnableBranchPrediction)
-GCC_ASM_EXPORT (ArmDisableBranchPrediction)
-GCC_ASM_EXPORT (ArmSetLowVectors)
-GCC_ASM_EXPORT (ArmSetHighVectors)
-GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
-GCC_ASM_EXPORT (ArmDataMemoryBarrier)
-GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
-GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
-GCC_ASM_EXPORT (ArmWriteNsacr)
-GCC_ASM_EXPORT (ArmWriteScr)
-GCC_ASM_EXPORT (ArmWriteVMBar)
-GCC_ASM_EXPORT (ArmWriteVBar)
-GCC_ASM_EXPORT (ArmWriteCPACR)
-GCC_ASM_EXPORT (ArmEnableVFP)
-GCC_ASM_EXPORT (ArmCallWFI)
-GCC_ASM_EXPORT (ArmWriteAuxCr)
-GCC_ASM_EXPORT (ArmReadAuxCr)
-GCC_ASM_EXPORT (ArmReadCbar)
-GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)
-GCC_ASM_EXPORT (ArmReadMpidr)
-GCC_ASM_EXPORT (ArmReadTpidrurw)
-GCC_ASM_EXPORT (ArmWriteTpidrurw)
-
-.set DC_ON, (0x1<<2)
-.set IC_ON, (0x1<<12)
-.set CTRL_M_BIT, (1 << 0)
-.set CTRL_C_BIT, (1 << 2)
-.set CTRL_B_BIT, (1 << 7)
-.set CTRL_I_BIT, (1 << 12)
-
-
-ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
- mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
- dsb
- isb
- bx lr
-
-ASM_PFX(ArmCleanDataCacheEntryByMVA):
- mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
- dsb
- isb
- bx lr
-
-
-ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
- mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
- dsb
- isb
- bx lr
-
-
-ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
- mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
- dsb
- isb
- bx lr
-
-
-ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
- mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
- dsb
- isb
- bx lr
-
-
-ASM_PFX(ArmCleanDataCacheEntryBySetWay):
- mcr p15, 0, r0, c7, c10, 2 @ Clean this line
- dsb
- isb
- bx lr
-
-ASM_PFX(ArmInvalidateInstructionCache):
- mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
- dsb
- isb
- bx LR
-
-ASM_PFX(ArmEnableMmu):
- mrc p15,0,R0,c1,c0,0
- orr R0,R0,#1
- mcr p15,0,R0,c1,c0,0
- dsb
- isb
- bx LR
-
-
-ASM_PFX(ArmDisableMmu):
- mrc p15,0,R0,c1,c0,0
- bic R0,R0,#1
- mcr p15,0,R0,c1,c0,0 @Disable MMU
-
- mcr p15,0,R0,c8,c7,0 @Invalidate TLB
- mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array
- dsb
- isb
- bx LR
-
-ASM_PFX(ArmDisableCachesAndMmu):
- mrc p15, 0, r0, c1, c0, 0 @ Get control register
- bic r0, r0, #CTRL_M_BIT @ Disable MMU
- bic r0, r0, #CTRL_C_BIT @ Disable D Cache
- bic r0, r0, #CTRL_I_BIT @ Disable I Cache
- mcr p15, 0, r0, c1, c0, 0 @ Write control register
- dsb
- isb
- bx LR
-
-ASM_PFX(ArmMmuEnabled):
- mrc p15,0,R0,c1,c0,0
- and R0,R0,#1
- bx LR
-
-ASM_PFX(ArmEnableDataCache):
- ldr R1,=DC_ON
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data
- orr R0,R0,R1 @Set C bit
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data
- dsb
- isb
- bx LR
-
-ASM_PFX(ArmDisableDataCache):
- ldr R1,=DC_ON
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data
- bic R0,R0,R1 @Clear C bit
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data
- dsb
- isb
- bx LR
-
-ASM_PFX(ArmEnableInstructionCache):
- ldr R1,=IC_ON
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data
- orr R0,R0,R1 @Set I bit
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data
- dsb
- isb
- bx LR
-
-ASM_PFX(ArmDisableInstructionCache):
- ldr R1,=IC_ON
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data
- bic R0,R0,R1 @Clear I bit.
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data
- dsb
- isb
- bx LR
-
-ASM_PFX(ArmEnableSWPInstruction):
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #0x00000400
- mcr p15, 0, r0, c1, c0, 0
- isb
- bx LR
-
-ASM_PFX(ArmEnableBranchPrediction):
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #0x00000800
- mcr p15, 0, r0, c1, c0, 0
- dsb
- isb
- bx LR
-
-ASM_PFX(ArmDisableBranchPrediction):
- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00000800
- mcr p15, 0, r0, c1, c0, 0
- dsb
- isb
- bx LR
-
-ASM_PFX(ArmSetLowVectors):
- mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
- bic r0, r0, #0x00002000 @ clear V bit
- mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
- isb
- bx LR
-
-ASM_PFX(ArmSetHighVectors):
- mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
- orr r0, r0, #0x00002000 @ clear V bit
- mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
- isb
- bx LR
-
-ASM_PFX(ArmV7AllDataCachesOperation):
- stmfd SP!,{r4-r12, LR}
- mov R1, R0 @ Save Function call in R1
- mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR
- ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC)
- mov R3, R3, LSR #23 @ Cache level value (naturally aligned)
- beq L_Finished
- mov R10, #0
-
-Loop1:
- add R2, R10, R10, LSR #1 @ Work out 3xcachelevel
- mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level
- and R12, R12, #7 @ get those 3 bits alone
- cmp R12, #2
- blt L_Skip @ no cache or only instruction cache at this level
- mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
- isb @ isb to sync the change to the CacheSizeID reg
- mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
- and R2, R12, #0x7 @ extract the line length field
- add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
-@ ldr R4, =0x3FF
- mov R4, #0x400
- sub R4, R4, #1
- ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)
- clz R5, R4 @ R5 is the bit position of the way size increment
-@ ldr R7, =0x00007FFF
- mov R7, #0x00008000
- sub R7, R7, #1
- ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)
-
-Loop2:
- mov R9, R4 @ R9 working copy of the max way size (right aligned)
-
-Loop3:
- orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11
- orr R0, R0, R7, LSL R2 @ factor in the index number
-
- blx R1
-
- subs R9, R9, #1 @ decrement the way number
- bge Loop3
- subs R7, R7, #1 @ decrement the index
- bge Loop2
-L_Skip:
- add R10, R10, #2 @ increment the cache number
- cmp R3, R10
- bgt Loop1
-
-L_Finished:
- dsb
- ldmfd SP!, {r4-r12, lr}
- bx LR
-
-ASM_PFX(ArmDataMemoryBarrier):
- dmb
- bx LR
-
-ASM_PFX(ArmDataSyncronizationBarrier):
-ASM_PFX(ArmDrainWriteBuffer):
- dsb
- bx LR
-
-ASM_PFX(ArmInstructionSynchronizationBarrier):
- isb
- bx LR
-
-ASM_PFX(ArmWriteNsacr):
- mcr p15, 0, r0, c1, c1, 2
- bx lr
-
-ASM_PFX(ArmWriteScr):
- mcr p15, 0, r0, c1, c1, 0
- bx lr
-
-ASM_PFX(ArmWriteAuxCr):
- mcr p15, 0, r0, c1, c0, 1
- bx lr
-
-ASM_PFX(ArmReadAuxCr):
- mrc p15, 0, r0, c1, c0, 1
- bx lr
-
-ASM_PFX(ArmWriteVMBar):
- mcr p15, 0, r0, c12, c0, 1
- bx lr
-
-ASM_PFX(ArmWriteVBar):
- # Set the Address of the Vector Table in the VBAR register
- mcr p15, 0, r0, c12, c0, 0
- # Ensure the SCTLR.V bit is clear
- mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
- bic r0, r0, #0x00002000 @ clear V bit
- mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
- isb
- bx lr
-
-ASM_PFX(ArmWriteCPACR):
- mcr p15, 0, r0, c1, c0, 2
- bx lr
-
-ASM_PFX(ArmEnableVFP):
- # Read CPACR (Coprocessor Access Control Register)
- mrc p15, 0, r0, c1, c0, 2
- # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
- orr r0, r0, #0x00f00000
- # Write back CPACR (Coprocessor Access Control Register)
- mcr p15, 0, r0, c1, c0, 2
- # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
- mov r0, #0x40000000
- mcr p10,#0x7,r0,c8,c0,#0
- bx lr
-
-ASM_PFX(ArmCallWFI):
- wfi
- bx lr
-
-#Note: Return 0 in Uniprocessor implementation
-ASM_PFX(ArmReadCbar):
- mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register
- bx lr
-
-ASM_PFX(ArmInvalidateInstructionAndDataTlb):
- mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB
- dsb
- bx lr
-
-ASM_PFX(ArmReadMpidr):
- mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
- bx lr
-
-ASM_PFX(ArmReadTpidrurw):
- mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW
- bx lr
-
-ASM_PFX(ArmWriteTpidrurw):
- mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW
- bx lr
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
+#------------------------------------------------------------------------------ \r
+#\r
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+.text\r
+.align 2\r
+\r
+GCC_ASM_EXPORT (ArmInvalidateInstructionCache)\r
+GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)\r
+GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)\r
+GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)\r
+GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)\r
+GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)\r
+GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)\r
+GCC_ASM_EXPORT (ArmDrainWriteBuffer)\r
+GCC_ASM_EXPORT (ArmEnableMmu)\r
+GCC_ASM_EXPORT (ArmDisableMmu)\r
+GCC_ASM_EXPORT (ArmDisableCachesAndMmu)\r
+GCC_ASM_EXPORT (ArmMmuEnabled)\r
+GCC_ASM_EXPORT (ArmEnableDataCache)\r
+GCC_ASM_EXPORT (ArmDisableDataCache)\r
+GCC_ASM_EXPORT (ArmEnableInstructionCache)\r
+GCC_ASM_EXPORT (ArmDisableInstructionCache)\r
+GCC_ASM_EXPORT (ArmEnableSWPInstruction)\r
+GCC_ASM_EXPORT (ArmEnableBranchPrediction)\r
+GCC_ASM_EXPORT (ArmDisableBranchPrediction)\r
+GCC_ASM_EXPORT (ArmSetLowVectors)\r
+GCC_ASM_EXPORT (ArmSetHighVectors)\r
+GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)\r
+GCC_ASM_EXPORT (ArmDataMemoryBarrier)\r
+GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)\r
+GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)\r
+GCC_ASM_EXPORT (ArmWriteVBar)\r
+GCC_ASM_EXPORT (ArmEnableVFP)\r
+GCC_ASM_EXPORT (ArmCallWFI)\r
+GCC_ASM_EXPORT (ArmReadCbar)\r
+GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)\r
+GCC_ASM_EXPORT (ArmReadMpidr)\r
+GCC_ASM_EXPORT (ArmReadTpidrurw)\r
+GCC_ASM_EXPORT (ArmWriteTpidrurw)\r
+GCC_ASM_EXPORT (ArmIsArchTimerImplemented)\r
+GCC_ASM_EXPORT (ArmReadIdPfr1)\r
+\r
+.set DC_ON, (0x1<<2)\r
+.set IC_ON, (0x1<<12)\r
+.set CTRL_M_BIT, (1 << 0)\r
+.set CTRL_C_BIT, (1 << 2)\r
+.set CTRL_B_BIT, (1 << 7)\r
+.set CTRL_I_BIT, (1 << 12)\r
+\r
+\r
+ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
+ mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line \r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
+ mcr p15, 0, r0, c7, c10, 1 @clean single data cache line \r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+\r
+ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r
+ mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line\r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+\r
+ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):\r
+ mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line \r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+\r
+ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):\r
+ mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line \r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+\r
+ASM_PFX(ArmCleanDataCacheEntryBySetWay):\r
+ mcr p15, 0, r0, c7, c10, 2 @ Clean this line \r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+ASM_PFX(ArmInvalidateInstructionCache):\r
+ mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ASM_PFX(ArmEnableMmu):\r
+ mrc p15,0,R0,c1,c0,0\r
+ orr R0,R0,#1\r
+ mcr p15,0,R0,c1,c0,0\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+\r
+ASM_PFX(ArmDisableMmu):\r
+ mrc p15,0,R0,c1,c0,0\r
+ bic R0,R0,#1\r
+ mcr p15,0,R0,c1,c0,0 @Disable MMU\r
+\r
+ mcr p15,0,R0,c8,c7,0 @Invalidate TLB\r
+ mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ASM_PFX(ArmDisableCachesAndMmu):\r
+ mrc p15, 0, r0, c1, c0, 0 @ Get control register\r
+ bic r0, r0, #CTRL_M_BIT @ Disable MMU\r
+ bic r0, r0, #CTRL_C_BIT @ Disable D Cache\r
+ bic r0, r0, #CTRL_I_BIT @ Disable I Cache\r
+ mcr p15, 0, r0, c1, c0, 0 @ Write control register\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ASM_PFX(ArmMmuEnabled):\r
+ mrc p15,0,R0,c1,c0,0\r
+ and R0,R0,#1\r
+ bx LR \r
+\r
+ASM_PFX(ArmEnableDataCache):\r
+ ldr R1,=DC_ON\r
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
+ orr R0,R0,R1 @Set C bit\r
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
+ dsb\r
+ isb\r
+ bx LR\r
+ \r
+ASM_PFX(ArmDisableDataCache):\r
+ ldr R1,=DC_ON\r
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
+ bic R0,R0,R1 @Clear C bit\r
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ASM_PFX(ArmEnableInstructionCache):\r
+ ldr R1,=IC_ON\r
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
+ orr R0,R0,R1 @Set I bit\r
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
+ dsb\r
+ isb\r
+ bx LR\r
+ \r
+ASM_PFX(ArmDisableInstructionCache):\r
+ ldr R1,=IC_ON\r
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
+ bic R0,R0,R1 @Clear I bit.\r
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ASM_PFX(ArmEnableSWPInstruction):\r
+ mrc p15, 0, r0, c1, c0, 0\r
+ orr r0, r0, #0x00000400\r
+ mcr p15, 0, r0, c1, c0, 0\r
+ isb\r
+ bx LR\r
+\r
+ASM_PFX(ArmEnableBranchPrediction):\r
+ mrc p15, 0, r0, c1, c0, 0\r
+ orr r0, r0, #0x00000800\r
+ mcr p15, 0, r0, c1, c0, 0\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ASM_PFX(ArmDisableBranchPrediction):\r
+ mrc p15, 0, r0, c1, c0, 0\r
+ bic r0, r0, #0x00000800\r
+ mcr p15, 0, r0, c1, c0, 0\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ASM_PFX(ArmSetLowVectors):\r
+ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
+ bic r0, r0, #0x00002000 @ clear V bit\r
+ mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
+ isb\r
+ bx LR\r
+\r
+ASM_PFX(ArmSetHighVectors):\r
+ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
+ orr r0, r0, #0x00002000 @ clear V bit\r
+ mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
+ isb\r
+ bx LR\r
+\r
+ASM_PFX(ArmV7AllDataCachesOperation):\r
+ stmfd SP!,{r4-r12, LR}\r
+ mov R1, R0 @ Save Function call in R1\r
+ mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR\r
+ ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC)\r
+ mov R3, R3, LSR #23 @ Cache level value (naturally aligned)\r
+ beq L_Finished\r
+ mov R10, #0\r
+\r
+Loop1: \r
+ add R2, R10, R10, LSR #1 @ Work out 3xcachelevel\r
+ mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level\r
+ and R12, R12, #7 @ get those 3 bits alone\r
+ cmp R12, #2\r
+ blt L_Skip @ no cache or only instruction cache at this level\r
+ mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
+ isb @ isb to sync the change to the CacheSizeID reg \r
+ mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)\r
+ and R2, R12, #0x7 @ extract the line length field\r
+ add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)\r
+@ ldr R4, =0x3FF\r
+ mov R4, #0x400\r
+ sub R4, R4, #1\r
+ ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)\r
+ clz R5, R4 @ R5 is the bit position of the way size increment\r
+@ ldr R7, =0x00007FFF\r
+ mov R7, #0x00008000\r
+ sub R7, R7, #1\r
+ ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)\r
+\r
+Loop2: \r
+ mov R9, R4 @ R9 working copy of the max way size (right aligned)\r
+\r
+Loop3: \r
+ orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11\r
+ orr R0, R0, R7, LSL R2 @ factor in the index number\r
+\r
+ blx R1\r
+\r
+ subs R9, R9, #1 @ decrement the way number\r
+ bge Loop3\r
+ subs R7, R7, #1 @ decrement the index\r
+ bge Loop2\r
+L_Skip: \r
+ add R10, R10, #2 @ increment the cache number\r
+ cmp R3, R10\r
+ bgt Loop1\r
+ \r
+L_Finished:\r
+ dsb\r
+ ldmfd SP!, {r4-r12, lr}\r
+ bx LR\r
+\r
+ASM_PFX(ArmDataMemoryBarrier):\r
+ dmb\r
+ bx LR\r
+ \r
+ASM_PFX(ArmDataSyncronizationBarrier):\r
+ASM_PFX(ArmDrainWriteBuffer):\r
+ dsb\r
+ bx LR\r
+ \r
+ASM_PFX(ArmInstructionSynchronizationBarrier):\r
+ isb\r
+ bx LR\r
+\r
+ASM_PFX(ArmWriteVBar):\r
+ # Set the Address of the Vector Table in the VBAR register\r
+ mcr p15, 0, r0, c12, c0, 0 \r
+ # Ensure the SCTLR.V bit is clear\r
+ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
+ bic r0, r0, #0x00002000 @ clear V bit\r
+ mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
+ isb\r
+ bx lr\r
+\r
+ASM_PFX(ArmEnableVFP):\r
+ # Read CPACR (Coprocessor Access Control Register)\r
+ mrc p15, 0, r0, c1, c0, 2\r
+ # Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
+ orr r0, r0, #0x00f00000\r
+ # Write back CPACR (Coprocessor Access Control Register)\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
+ mov r0, #0x40000000\r
+ mcr p10,#0x7,r0,c8,c0,#0\r
+ bx lr\r
+\r
+ASM_PFX(ArmCallWFI):\r
+ wfi\r
+ bx lr\r
+\r
+#Note: Return 0 in Uniprocessor implementation\r
+ASM_PFX(ArmReadCbar):\r
+ mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register\r
+ bx lr\r
+\r
+ASM_PFX(ArmInvalidateInstructionAndDataTlb):\r
+ mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB\r
+ dsb\r
+ bx lr\r
+\r
+ASM_PFX(ArmReadMpidr):\r
+ mrc p15, 0, r0, c0, c0, 5 @ read MPIDR\r
+ bx lr\r
+ \r
+ASM_PFX(ArmReadTpidrurw):\r
+ mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW\r
+ bx lr\r
+\r
+ASM_PFX(ArmWriteTpidrurw):\r
+ mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW\r
+ bx lr\r
+\r
+ASM_PFX(ArmIsArchTimerImplemented):\r
+ mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1\r
+ and r0, r0, #0x000F0000\r
+ bx lr\r
+\r
+ASM_PFX(ArmReadIdPfr1):\r
+ mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register\r
+ bx lr\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//------------------------------------------------------------------------------
-
- EXPORT ArmInvalidateInstructionCache
- EXPORT ArmInvalidateDataCacheEntryByMVA
- EXPORT ArmCleanDataCacheEntryByMVA
- EXPORT ArmCleanInvalidateDataCacheEntryByMVA
- EXPORT ArmInvalidateDataCacheEntryBySetWay
- EXPORT ArmCleanDataCacheEntryBySetWay
- EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
- EXPORT ArmDrainWriteBuffer
- EXPORT ArmEnableMmu
- EXPORT ArmDisableMmu
- EXPORT ArmDisableCachesAndMmu
- EXPORT ArmMmuEnabled
- EXPORT ArmEnableDataCache
- EXPORT ArmDisableDataCache
- EXPORT ArmEnableInstructionCache
- EXPORT ArmDisableInstructionCache
- EXPORT ArmEnableSWPInstruction
- EXPORT ArmEnableBranchPrediction
- EXPORT ArmDisableBranchPrediction
- EXPORT ArmSetLowVectors
- EXPORT ArmSetHighVectors
- EXPORT ArmV7AllDataCachesOperation
- EXPORT ArmDataMemoryBarrier
- EXPORT ArmDataSyncronizationBarrier
- EXPORT ArmInstructionSynchronizationBarrier
- EXPORT ArmWriteNsacr
- EXPORT ArmWriteScr
- EXPORT ArmWriteVMBar
- EXPORT ArmWriteVBar
- EXPORT ArmReadVBar
- EXPORT ArmWriteCPACR
- EXPORT ArmEnableVFP
- EXPORT ArmCallWFI
- EXPORT ArmWriteAuxCr
- EXPORT ArmReadAuxCr
- EXPORT ArmReadCbar
- EXPORT ArmInvalidateInstructionAndDataTlb
- EXPORT ArmReadMpidr
- EXPORT ArmReadTpidrurw
- EXPORT ArmWriteTpidrurw
-
- AREA ArmCacheLib, CODE, READONLY
- PRESERVE8
-
-DC_ON EQU ( 0x1:SHL:2 )
-IC_ON EQU ( 0x1:SHL:12 )
-CTRL_M_BIT EQU (1 << 0)
-CTRL_C_BIT EQU (1 << 2)
-CTRL_B_BIT EQU (1 << 7)
-CTRL_I_BIT EQU (1 << 12)
-
-
-ArmInvalidateDataCacheEntryByMVA
- mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
- dsb
- isb
- bx lr
-
-
-ArmCleanDataCacheEntryByMVA
- mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
- dsb
- isb
- bx lr
-
-
-ArmCleanInvalidateDataCacheEntryByMVA
- mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
- dsb
- isb
- bx lr
-
-
-ArmInvalidateDataCacheEntryBySetWay
- mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
- dsb
- isb
- bx lr
-
-
-ArmCleanInvalidateDataCacheEntryBySetWay
- mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
- dsb
- isb
- bx lr
-
-
-ArmCleanDataCacheEntryBySetWay
- mcr p15, 0, r0, c7, c10, 2 ; Clean this line
- dsb
- isb
- bx lr
-
-
-ArmInvalidateInstructionCache
- mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
- isb
- bx LR
-
-ArmEnableMmu
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
- orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
- dsb
- isb
- bx LR
-
-ArmMmuEnabled
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
- and R0,R0,#1
- bx LR
-
-ArmDisableMmu
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
- bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
-
- mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
- mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
- dsb
- isb
- bx LR
-
-ArmDisableCachesAndMmu
- mrc p15, 0, r0, c1, c0, 0 ; Get control register
- bic r0, r0, #CTRL_M_BIT ; Disable MMU
- bic r0, r0, #CTRL_C_BIT ; Disable D Cache
- bic r0, r0, #CTRL_I_BIT ; Disable I Cache
- mcr p15, 0, r0, c1, c0, 0 ; Write control register
- dsb
- isb
- bx LR
-
-ArmEnableDataCache
- ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
- orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
- dsb
- isb
- bx LR
-
-ArmDisableDataCache
- ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
- bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
- isb
- bx LR
-
-ArmEnableInstructionCache
- ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
- orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
- dsb
- isb
- bx LR
-
-ArmDisableInstructionCache
- ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
- mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
- BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
- mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
- isb
- bx LR
-
-ArmEnableSWPInstruction
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #0x00000400
- mcr p15, 0, r0, c1, c0, 0
- isb
- bx LR
-
-ArmEnableBranchPrediction
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
- orr r0, r0, #0x00000800 ;
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
- isb
- bx LR
-
-ArmDisableBranchPrediction
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
- bic r0, r0, #0x00000800 ;
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
- isb
- bx LR
-
-ArmSetLowVectors
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
- bic r0, r0, #0x00002000 ; clear V bit
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
- isb
- bx LR
-
-ArmSetHighVectors
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
- orr r0, r0, #0x00002000 ; clear V bit
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
- isb
- bx LR
-
-ArmV7AllDataCachesOperation
- stmfd SP!,{r4-r12, LR}
- mov R1, R0 ; Save Function call in R1
- mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
- ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
- mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
- beq Finished
- mov R10, #0
-
-Loop1
- add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
- mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
- and R12, R12, #7 ; get those 3 bits alone
- cmp R12, #2
- blt Skip ; no cache or only instruction cache at this level
- mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
- isb ; isb to sync the change to the CacheSizeID reg
- mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
- and R2, R12, #&7 ; extract the line length field
- add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
- ldr R4, =0x3FF
- ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
- clz R5, R4 ; R5 is the bit position of the way size increment
- ldr R7, =0x00007FFF
- ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
-
-Loop2
- mov R9, R4 ; R9 working copy of the max way size (right aligned)
-
-Loop3
- orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
- orr R0, R0, R7, LSL R2 ; factor in the index number
-
- blx R1
-
- subs R9, R9, #1 ; decrement the way number
- bge Loop3
- subs R7, R7, #1 ; decrement the index
- bge Loop2
-Skip
- add R10, R10, #2 ; increment the cache number
- cmp R3, R10
- bgt Loop1
-
-Finished
- dsb
- ldmfd SP!, {r4-r12, lr}
- bx LR
-
-
-ArmDataMemoryBarrier
- dmb
- bx LR
-
-ArmDataSyncronizationBarrier
-ArmDrainWriteBuffer
- dsb
- bx LR
-
-ArmInstructionSynchronizationBarrier
- isb
- bx LR
-
-ArmWriteNsacr
- mcr p15, 0, r0, c1, c1, 2
- bx lr
-
-ArmWriteScr
- mcr p15, 0, r0, c1, c1, 0
- bx lr
-
-ArmWriteAuxCr
- mcr p15, 0, r0, c1, c0, 1
- bx lr
-
-ArmReadAuxCr
- mrc p15, 0, r0, c1, c0, 1
- bx lr
-
-ArmWriteVMBar
- mcr p15, 0, r0, c12, c0, 1
- bx lr
-
-ArmWriteVBar
- // Set the Address of the Vector Table in the VBAR register
- mcr p15, 0, r0, c12, c0, 0
- // Ensure the SCTLR.V bit is clear
- mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
- bic r0, r0, #0x00002000 ; clear V bit
- mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
- isb
- bx lr
-
-ArmReadVBar
- mrc p15, 0, r0, c12, c0, 0
- bx lr
-
-ArmWriteCPACR
- mcr p15, 0, r0, c1, c0, 2
- bx lr
-
-ArmEnableVFP
- // Read CPACR (Coprocessor Access Control Register)
- mrc p15, 0, r0, c1, c0, 2
- // Enable VPF access (Full Access to CP10, CP11) (V* instructions)
- orr r0, r0, #0x00f00000
- // Write back CPACR (Coprocessor Access Control Register)
- mcr p15, 0, r0, c1, c0, 2
- // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
- mov r0, #0x40000000
- mcr p10,#0x7,r0,c8,c0,#0
- bx lr
-
-ArmCallWFI
- wfi
- bx lr
-
-//Note: Return 0 in Uniprocessor implementation
-ArmReadCbar
- mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
- bx lr
-
-ArmInvalidateInstructionAndDataTlb
- mcr p15, 0, r0, c8, c7, 0 ; Invalidate Inst TLB and Data TLB
- dsb
- bx lr
-
-ArmReadMpidr
- mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
- bx lr
-
-ArmReadTpidrurw
- mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW
- bx lr
-
-ArmWriteTpidrurw
- mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW
- bx lr
-
- END
-
+//------------------------------------------------------------------------------ \r
+//\r
+// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+ EXPORT ArmInvalidateInstructionCache\r
+ EXPORT ArmInvalidateDataCacheEntryByMVA\r
+ EXPORT ArmCleanDataCacheEntryByMVA\r
+ EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r
+ EXPORT ArmInvalidateDataCacheEntryBySetWay\r
+ EXPORT ArmCleanDataCacheEntryBySetWay\r
+ EXPORT ArmCleanInvalidateDataCacheEntryBySetWay\r
+ EXPORT ArmDrainWriteBuffer\r
+ EXPORT ArmEnableMmu\r
+ EXPORT ArmDisableMmu\r
+ EXPORT ArmDisableCachesAndMmu\r
+ EXPORT ArmMmuEnabled\r
+ EXPORT ArmEnableDataCache\r
+ EXPORT ArmDisableDataCache\r
+ EXPORT ArmEnableInstructionCache\r
+ EXPORT ArmDisableInstructionCache\r
+ EXPORT ArmEnableSWPInstruction\r
+ EXPORT ArmEnableBranchPrediction\r
+ EXPORT ArmDisableBranchPrediction\r
+ EXPORT ArmSetLowVectors\r
+ EXPORT ArmSetHighVectors\r
+ EXPORT ArmV7AllDataCachesOperation\r
+ EXPORT ArmDataMemoryBarrier\r
+ EXPORT ArmDataSyncronizationBarrier\r
+ EXPORT ArmInstructionSynchronizationBarrier\r
+ EXPORT ArmWriteVBar\r
+ EXPORT ArmEnableVFP\r
+ EXPORT ArmCallWFI\r
+ EXPORT ArmReadCbar\r
+ EXPORT ArmInvalidateInstructionAndDataTlb\r
+ EXPORT ArmReadMpidr\r
+ EXPORT ArmReadTpidrurw\r
+ EXPORT ArmWriteTpidrurw\r
+ EXPORT ArmIsArchTimerImplemented\r
+ EXPORT ArmReadIdPfr1\r
+\r
+ AREA ArmV7Support, CODE, READONLY\r
+ PRESERVE8\r
+\r
+DC_ON EQU ( 0x1:SHL:2 )\r
+IC_ON EQU ( 0x1:SHL:12 )\r
+CTRL_M_BIT EQU (1 << 0)\r
+CTRL_C_BIT EQU (1 << 2)\r
+CTRL_B_BIT EQU (1 << 7)\r
+CTRL_I_BIT EQU (1 << 12)\r
+\r
+\r
+ArmInvalidateDataCacheEntryByMVA\r
+ mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line \r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+ArmCleanDataCacheEntryByMVA\r
+ mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line \r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+\r
+ArmCleanInvalidateDataCacheEntryByMVA\r
+ mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line\r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+\r
+ArmInvalidateDataCacheEntryBySetWay\r
+ mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line \r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+\r
+ArmCleanInvalidateDataCacheEntryBySetWay\r
+ mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line \r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+\r
+ArmCleanDataCacheEntryBySetWay\r
+ mcr p15, 0, r0, c7, c10, 2 ; Clean this line \r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+\r
+ArmInvalidateInstructionCache\r
+ mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache\r
+ isb\r
+ bx LR\r
+\r
+ArmEnableMmu\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU\r
+ mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ArmDisableMmu\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU\r
+ mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
+\r
+ mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB\r
+ mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ArmDisableCachesAndMmu\r
+ mrc p15, 0, r0, c1, c0, 0 ; Get control register\r
+ bic r0, r0, #CTRL_M_BIT ; Disable MMU\r
+ bic r0, r0, #CTRL_C_BIT ; Disable D Cache\r
+ bic r0, r0, #CTRL_I_BIT ; Disable I Cache\r
+ mcr p15, 0, r0, c1, c0, 0 ; Write control register\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ArmMmuEnabled\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ and R0,R0,#1\r
+ bx LR\r
+\r
+ArmEnableDataCache\r
+ ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled\r
+ mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ dsb\r
+ isb\r
+ bx LR\r
+ \r
+ArmDisableDataCache\r
+ ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled\r
+ mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ArmEnableInstructionCache\r
+ ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled\r
+ mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ dsb\r
+ isb\r
+ bx LR\r
+ \r
+ArmDisableInstructionCache\r
+ ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
+ mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled\r
+ mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ isb\r
+ bx LR\r
+\r
+ArmEnableSWPInstruction\r
+ mrc p15, 0, r0, c1, c0, 0\r
+ orr r0, r0, #0x00000400\r
+ mcr p15, 0, r0, c1, c0, 0\r
+ isb\r
+ bx LR\r
+\r
+ArmEnableBranchPrediction\r
+ mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ orr r0, r0, #0x00000800 ;\r
+ mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ArmDisableBranchPrediction\r
+ mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ bic r0, r0, #0x00000800 ;\r
+ mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ dsb\r
+ isb\r
+ bx LR\r
+\r
+ArmSetLowVectors\r
+ mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ bic r0, r0, #0x00002000 ; clear V bit\r
+ mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ isb\r
+ bx LR\r
+\r
+ArmSetHighVectors\r
+ mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ orr r0, r0, #0x00002000 ; clear V bit\r
+ mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ isb\r
+ bx LR\r
+\r
+ArmV7AllDataCachesOperation\r
+ stmfd SP!,{r4-r12, LR}\r
+ mov R1, R0 ; Save Function call in R1\r
+ mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR\r
+ ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)\r
+ mov R3, R3, LSR #23 ; Cache level value (naturally aligned)\r
+ beq Finished\r
+ mov R10, #0\r
+\r
+Loop1 \r
+ add R2, R10, R10, LSR #1 ; Work out 3xcachelevel\r
+ mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level\r
+ and R12, R12, #7 ; get those 3 bits alone\r
+ cmp R12, #2\r
+ blt Skip ; no cache or only instruction cache at this level\r
+ mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
+ isb ; isb to sync the change to the CacheSizeID reg \r
+ mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)\r
+ and R2, R12, #&7 ; extract the line length field\r
+ add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)\r
+ ldr R4, =0x3FF\r
+ ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)\r
+ clz R5, R4 ; R5 is the bit position of the way size increment\r
+ ldr R7, =0x00007FFF\r
+ ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)\r
+\r
+Loop2 \r
+ mov R9, R4 ; R9 working copy of the max way size (right aligned)\r
+\r
+Loop3 \r
+ orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11\r
+ orr R0, R0, R7, LSL R2 ; factor in the index number\r
+\r
+ blx R1\r
+\r
+ subs R9, R9, #1 ; decrement the way number\r
+ bge Loop3\r
+ subs R7, R7, #1 ; decrement the index\r
+ bge Loop2\r
+Skip \r
+ add R10, R10, #2 ; increment the cache number\r
+ cmp R3, R10\r
+ bgt Loop1\r
+ \r
+Finished\r
+ dsb\r
+ ldmfd SP!, {r4-r12, lr}\r
+ bx LR\r
+\r
+ArmDataMemoryBarrier\r
+ dmb\r
+ bx LR\r
+ \r
+ArmDataSyncronizationBarrier\r
+ArmDrainWriteBuffer\r
+ dsb\r
+ bx LR\r
+ \r
+ArmInstructionSynchronizationBarrier\r
+ isb\r
+ bx LR\r
+\r
+ArmWriteVBar\r
+ // Set the Address of the Vector Table in the VBAR register\r
+ mcr p15, 0, r0, c12, c0, 0 \r
+ // Ensure the SCTLR.V bit is clear\r
+ mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
+ bic r0, r0, #0x00002000 ; clear V bit\r
+ mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
+ isb\r
+ bx lr\r
+\r
+ArmEnableVFP\r
+ // Read CPACR (Coprocessor Access Control Register)\r
+ mrc p15, 0, r0, c1, c0, 2\r
+ // Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
+ orr r0, r0, #0x00f00000\r
+ // Write back CPACR (Coprocessor Access Control Register)\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
+ mov r0, #0x40000000\r
+ mcr p10,#0x7,r0,c8,c0,#0\r
+ bx lr\r
+\r
+ArmCallWFI\r
+ wfi\r
+ bx lr\r
+\r
+//Note: Return 0 in Uniprocessor implementation\r
+ArmReadCbar\r
+ mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register\r
+ bx lr\r
+\r
+ArmInvalidateInstructionAndDataTlb\r
+ mcr p15, 0, r0, c8, c7, 0 ; Invalidate Inst TLB and Data TLB\r
+ dsb\r
+ bx lr\r
+\r
+ArmReadMpidr\r
+ mrc p15, 0, r0, c0, c0, 5 ; read MPIDR\r
+ bx lr\r
+\r
+ArmReadTpidrurw\r
+ mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW\r
+ bx lr\r
+\r
+ArmWriteTpidrurw\r
+ mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW\r
+ bx lr\r
+\r
+ArmIsArchTimerImplemented\r
+ mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1\r
+ and r0, r0, #0x000F0000\r
+ bx lr\r
+\r
+ArmReadIdPfr1\r
+ mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register\r
+ bx lr\r
+\r
+ END\r
{\r
return (ARM_PROCESSOR_MODE)(CPSRRead() & (UINT32)ARM_PROCESSOR_MODE_MASK);\r
}\r
+\r
+VOID\r
+EFIAPI\r
+ArmSetAuxCrBit (\r
+ IN UINT32 Bits\r
+ )\r
+{\r
+ UINT32 val = ArmReadAuxCr();\r
+ val |= Bits;\r
+ ArmWriteAuxCr(val);\r
+}\r
+\r
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-#include <AsmMacroIoLib.h>
-
-.text
-.align 2
-GCC_ASM_EXPORT(Cp15IdCode)
-GCC_ASM_EXPORT(Cp15CacheInfo)
-GCC_ASM_EXPORT(ArmEnableInterrupts)
-GCC_ASM_EXPORT(ArmDisableInterrupts)
-GCC_ASM_EXPORT(ArmGetInterruptState)
-GCC_ASM_EXPORT(ArmEnableFiq)
-GCC_ASM_EXPORT(ArmDisableFiq)
-GCC_ASM_EXPORT(ArmGetFiqState)
-GCC_ASM_EXPORT(ArmInvalidateTlb)
-GCC_ASM_EXPORT(ArmSetTTBR0)
-GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
-GCC_ASM_EXPORT(ArmSetDomainAccessControl)
-GCC_ASM_EXPORT(CPSRMaskInsert)
-GCC_ASM_EXPORT(CPSRRead)
-
-#------------------------------------------------------------------------------
-
-ASM_PFX(Cp15IdCode):
- mrc p15,0,R0,c0,c0,0
- bx LR
-
-ASM_PFX(Cp15CacheInfo):
- mrc p15,0,R0,c0,c0,1
- bx LR
-
-ASM_PFX(ArmEnableInterrupts):
- mrs R0,CPSR
- bic R0,R0,#0x80 @Enable IRQ interrupts
- msr CPSR_c,R0
- bx LR
-
-ASM_PFX(ArmDisableInterrupts):
- mrs R0,CPSR
- orr R1,R0,#0x80 @Disable IRQ interrupts
- msr CPSR_c,R1
- tst R0,#0x80
- moveq R0,#1
- movne R0,#0
- bx LR
-
-ASM_PFX(ArmGetInterruptState):
- mrs R0,CPSR
- tst R0,#0x80 @Check if IRQ is enabled.
- moveq R0,#1
- movne R0,#0
- bx LR
-
-ASM_PFX(ArmEnableFiq):
- mrs R0,CPSR
- bic R0,R0,#0x40 @Enable FIQ interrupts
- msr CPSR_c,R0
- bx LR
-
-ASM_PFX(ArmDisableFiq):
- mrs R0,CPSR
- orr R1,R0,#0x40 @Disable FIQ interrupts
- msr CPSR_c,R1
- tst R0,#0x80
- moveq R0,#1
- movne R0,#0
- bx LR
-
-ASM_PFX(ArmGetFiqState):
- mrs R0,CPSR
- tst R0,#0x80 @Check if FIQ is enabled.
- moveq R0,#1
- movne R0,#0
- bx LR
-
-ASM_PFX(ArmInvalidateTlb):
- mov r0,#0
- mcr p15,0,r0,c8,c7,0
- bx lr
-
-ASM_PFX(ArmSetTTBR0):
- mcr p15,0,r0,c2,c0,0
- bx lr
-
-ASM_PFX(ArmGetTTBR0BaseAddress):
- mrc p15,0,r0,c2,c0,0
- LoadConstantToReg(0xFFFFC000, r1) @ and r0, r0, #0xFFFFC000
- and r0, r0, r1
- bx lr
-
-
-ASM_PFX(ArmSetDomainAccessControl):
- mcr p15,0,r0,c3,c0,0
- bx lr
-
-ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
- stmfd sp!, {r4-r12, lr} @ save all the banked registers
- mov r3, sp @ copy the stack pointer into a non-banked register
- mrs r2, cpsr @ read the cpsr
- bic r2, r2, r0 @ clear mask in the cpsr
- and r1, r1, r0 @ clear bits outside the mask in the input
- orr r2, r2, r1 @ set field
- msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
- mov sp, r3 @ restore stack pointer
- ldmfd sp!, {r4-r12, lr} @ restore registers
- bx lr @ return (hopefully thumb-safe!)
-
-ASM_PFX(CPSRRead):
- mrs r0, cpsr
- bx lr
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
+#------------------------------------------------------------------------------ \r
+#\r
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+\r
+#ifdef ARM_CPU_ARMv6\r
+// No memory barriers for ARMv6\r
+#define isb\r
+#define dsb\r
+#endif\r
+\r
+.text\r
+.align 2\r
+GCC_ASM_EXPORT(Cp15IdCode)\r
+GCC_ASM_EXPORT(Cp15CacheInfo)\r
+GCC_ASM_EXPORT(ArmGetInterruptState)\r
+GCC_ASM_EXPORT(ArmGetFiqState)\r
+GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)\r
+GCC_ASM_EXPORT(ArmSetTTBR0)\r
+GCC_ASM_EXPORT(ArmSetDomainAccessControl)\r
+GCC_ASM_EXPORT(CPSRMaskInsert)\r
+GCC_ASM_EXPORT(CPSRRead)\r
+GCC_ASM_EXPORT(ArmWriteCPACR)\r
+GCC_ASM_EXPORT(ArmWriteAuxCr)\r
+GCC_ASM_EXPORT(ArmReadAuxCr)\r
+GCC_ASM_EXPORT(ArmInvalidateTlb)\r
+GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)\r
+GCC_ASM_EXPORT(ArmWriteNsacr)\r
+GCC_ASM_EXPORT(ArmWriteScr)\r
+GCC_ASM_EXPORT(ArmWriteVMBar)\r
+\r
+#------------------------------------------------------------------------------\r
+\r
+ASM_PFX(Cp15IdCode):\r
+ mrc p15,0,R0,c0,c0,0\r
+ bx LR\r
+\r
+ASM_PFX(Cp15CacheInfo):\r
+ mrc p15,0,R0,c0,c0,1\r
+ bx LR\r
+\r
+ASM_PFX(ArmGetInterruptState):\r
+ mrs R0,CPSR\r
+ tst R0,#0x80 @Check if IRQ is enabled.\r
+ moveq R0,#1\r
+ movne R0,#0\r
+ bx LR\r
+\r
+ASM_PFX(ArmGetFiqState):\r
+ mrs R0,CPSR\r
+ tst R0,#0x40 @Check if FIQ is enabled.\r
+ moveq R0,#1\r
+ movne R0,#0\r
+ bx LR\r
+\r
+ASM_PFX(ArmSetDomainAccessControl):\r
+ mcr p15,0,r0,c3,c0,0\r
+ bx lr\r
+\r
+ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert\r
+ stmfd sp!, {r4-r12, lr} @ save all the banked registers\r
+ mov r3, sp @ copy the stack pointer into a non-banked register\r
+ mrs r2, cpsr @ read the cpsr\r
+ bic r2, r2, r0 @ clear mask in the cpsr\r
+ and r1, r1, r0 @ clear bits outside the mask in the input\r
+ orr r2, r2, r1 @ set field\r
+ msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)\r
+ isb\r
+ mov sp, r3 @ restore stack pointer\r
+ ldmfd sp!, {r4-r12, lr} @ restore registers\r
+ bx lr @ return (hopefully thumb-safe!) @ return (hopefully thumb-safe!)\r
+\r
+ASM_PFX(CPSRRead):\r
+ mrs r0, cpsr\r
+ bx lr\r
+\r
+ASM_PFX(ArmWriteCPACR):\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ bx lr\r
+\r
+ASM_PFX(ArmWriteAuxCr):\r
+ mcr p15, 0, r0, c1, c0, 1\r
+ bx lr\r
+\r
+ASM_PFX(ArmReadAuxCr):\r
+ mrc p15, 0, r0, c1, c0, 1\r
+ bx lr \r
+\r
+ASM_PFX(ArmSetTTBR0):\r
+ mcr p15,0,r0,c2,c0,0\r
+ isb\r
+ bx lr\r
+\r
+ASM_PFX(ArmGetTTBR0BaseAddress):\r
+ mrc p15,0,r0,c2,c0,0\r
+ LoadConstantToReg(0xFFFFC000, r1)\r
+ and r0, r0, r1\r
+ isb\r
+ bx lr\r
+\r
+//\r
+//VOID\r
+//ArmUpdateTranslationTableEntry (\r
+// IN VOID *TranslationTableEntry // R0\r
+// IN VOID *MVA // R1\r
+// );\r
+ASM_PFX(ArmUpdateTranslationTableEntry):\r
+ mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA\r
+ dsb\r
+ mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA \r
+ mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+ASM_PFX(ArmInvalidateTlb):\r
+ mov r0,#0\r
+ mcr p15,0,r0,c8,c7,0\r
+ mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+ASM_PFX(ArmWriteNsacr):\r
+ mcr p15, 0, r0, c1, c1, 2\r
+ bx lr\r
+\r
+ASM_PFX(ArmWriteScr):\r
+ mcr p15, 0, r0, c1, c1, 0\r
+ bx lr\r
+\r
+ASM_PFX(ArmWriteVMBar):\r
+ mcr p15, 0, r0, c12, c0, 1\r
+ bx lr\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//------------------------------------------------------------------------------
-
-#include <AsmMacroIoLib.h>
-
- INCLUDE AsmMacroIoLib.inc
-
- EXPORT Cp15IdCode
- EXPORT Cp15CacheInfo
- EXPORT ArmIsMPCore
- EXPORT ArmEnableInterrupts
- EXPORT ArmDisableInterrupts
- EXPORT ArmGetInterruptState
- EXPORT ArmEnableFiq
- EXPORT ArmDisableFiq
- EXPORT ArmGetFiqState
- EXPORT ArmInvalidateTlb
- EXPORT ArmSetTTBR0
- EXPORT ArmGetTTBR0BaseAddress
- EXPORT ArmSetDomainAccessControl
- EXPORT CPSRMaskInsert
- EXPORT CPSRRead
-
- AREA ArmLibSupport, CODE, READONLY
-
-Cp15IdCode
- mrc p15,0,R0,c0,c0,0
- bx LR
-
-Cp15CacheInfo
- mrc p15,0,R0,c0,c0,1
- bx LR
-
-ArmIsMPCore
- mrc p15,0,R0,c0,c0,5
- // Get Multiprocessing extension (bit31) & U bit (bit30)
- and R0, R0, #0xC0000000
- // if bit30 == 0 then the processor is part of a multiprocessor system)
- and R0, R0, #0x80000000
- bx LR
-
-ArmEnableInterrupts
- mrs R0,CPSR
- bic R0,R0,#0x80 ;Enable IRQ interrupts
- msr CPSR_c,R0
- bx LR
-
-ArmDisableInterrupts
- mrs R0,CPSR
- orr R1,R0,#0x80 ;Disable IRQ interrupts
- msr CPSR_c,R1
- tst R0,#0x80
- moveq R0,#1
- movne R0,#0
- bx LR
-
-ArmGetInterruptState
- mrs R0,CPSR
- tst R0,#0x80 ;Check if IRQ is enabled.
- moveq R0,#1
- movne R0,#0
- bx LR
-
-ArmEnableFiq
- mrs R0,CPSR
- bic R0,R0,#0x40 ;Enable IRQ interrupts
- msr CPSR_c,R0
- bx LR
-
-ArmDisableFiq
- mrs R0,CPSR
- orr R1,R0,#0x40 ;Disable IRQ interrupts
- msr CPSR_c,R1
- tst R0,#0x40
- moveq R0,#1
- movne R0,#0
- bx LR
-
-ArmGetFiqState
- mrs R0,CPSR
- tst R0,#0x40 ;Check if IRQ is enabled.
- moveq R0,#1
- movne R0,#0
- bx LR
-
-ArmInvalidateTlb
- mov r0,#0
- mcr p15,0,r0,c8,c7,0
- bx lr
-
-ArmSetTTBR0
- mcr p15,0,r0,c2,c0,0
- bx lr
-
-ArmGetTTBR0BaseAddress
- mrc p15,0,r0,c2,c0,0
- LoadConstantToReg(0xFFFFC000,r1) // and r0, r0, #0xFFFFC000
- and r0, r0, r1
- bx lr
-
-ArmSetDomainAccessControl
- mcr p15,0,r0,c3,c0,0
- bx lr
-
-CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
- stmfd sp!, {r4-r12, lr} ; save all the banked registers
- mov r3, sp ; copy the stack pointer into a non-banked register
- mrs r2, cpsr ; read the cpsr
- bic r2, r2, r0 ; clear mask in the cpsr
- and r1, r1, r0 ; clear bits outside the mask in the input
- orr r2, r2, r1 ; set field
- msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
- mov sp, r3 ; restore stack pointer
- ldmfd sp!, {r4-r12, lr} ; restore registers
- bx lr ; return (hopefully thumb-safe!)
-
-CPSRRead
- mrs r0, cpsr
- bx lr
-
- END
-
-
+//------------------------------------------------------------------------------ \r
+//\r
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+ \r
+ INCLUDE AsmMacroIoLib.inc\r
+\r
+#ifdef ARM_CPU_ARMv6\r
+// No memory barriers for ARMv6\r
+#define isb\r
+#define dsb\r
+#endif\r
+\r
+ EXPORT Cp15IdCode\r
+ EXPORT Cp15CacheInfo\r
+ EXPORT ArmGetInterruptState\r
+ EXPORT ArmGetFiqState\r
+ EXPORT ArmGetTTBR0BaseAddress\r
+ EXPORT ArmSetTTBR0\r
+ EXPORT ArmSetDomainAccessControl\r
+ EXPORT CPSRMaskInsert\r
+ EXPORT CPSRRead\r
+ EXPORT ArmWriteCPACR\r
+ EXPORT ArmWriteAuxCr\r
+ EXPORT ArmReadAuxCr\r
+ EXPORT ArmInvalidateTlb\r
+ EXPORT ArmUpdateTranslationTableEntry\r
+ EXPORT ArmWriteNsacr\r
+ EXPORT ArmWriteScr\r
+ EXPORT ArmWriteVMBar\r
+\r
+ AREA ArmLibSupport, CODE, READONLY\r
+\r
+Cp15IdCode\r
+ mrc p15,0,R0,c0,c0,0\r
+ bx LR\r
+\r
+Cp15CacheInfo\r
+ mrc p15,0,R0,c0,c0,1\r
+ bx LR\r
+\r
+ArmGetInterruptState\r
+ mrs R0,CPSR\r
+ tst R0,#0x80 // Check if IRQ is enabled.\r
+ moveq R0,#1\r
+ movne R0,#0\r
+ bx LR\r
+\r
+ArmGetFiqState\r
+ mrs R0,CPSR\r
+ tst R0,#0x40 // Check if FIQ is enabled.\r
+ moveq R0,#1\r
+ movne R0,#0\r
+ bx LR\r
+\r
+ArmSetDomainAccessControl\r
+ mcr p15,0,r0,c3,c0,0\r
+ bx lr\r
+\r
+CPSRMaskInsert // on entry, r0 is the mask and r1 is the field to insert\r
+ stmfd sp!, {r4-r12, lr} // save all the banked registers\r
+ mov r3, sp // copy the stack pointer into a non-banked register\r
+ mrs r2, cpsr // read the cpsr\r
+ bic r2, r2, r0 // clear mask in the cpsr\r
+ and r1, r1, r0 // clear bits outside the mask in the input\r
+ orr r2, r2, r1 // set field\r
+ msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch)\r
+ isb\r
+ mov sp, r3 // restore stack pointer\r
+ ldmfd sp!, {r4-r12, lr} // restore registers\r
+ bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)\r
+\r
+CPSRRead\r
+ mrs r0, cpsr\r
+ bx lr\r
+\r
+ArmWriteCPACR\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ bx lr\r
+\r
+ArmWriteAuxCr\r
+ mcr p15, 0, r0, c1, c0, 1\r
+ bx lr\r
+\r
+ArmReadAuxCr\r
+ mrc p15, 0, r0, c1, c0, 1\r
+ bx lr \r
+\r
+ArmSetTTBR0\r
+ mcr p15,0,r0,c2,c0,0\r
+ isb\r
+ bx lr\r
+\r
+ArmGetTTBR0BaseAddress\r
+ mrc p15,0,r0,c2,c0,0\r
+ LoadConstantToReg(0xFFFFC000, r1)\r
+ and r0, r0, r1\r
+ isb\r
+ bx lr\r
+\r
+//\r
+//VOID\r
+//ArmUpdateTranslationTableEntry (\r
+// IN VOID *TranslationTableEntry // R0\r
+// IN VOID *MVA // R1\r
+// );\r
+ArmUpdateTranslationTableEntry\r
+ mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA\r
+ dsb\r
+ mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA\r
+ mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+ArmInvalidateTlb\r
+ mov r0,#0\r
+ mcr p15,0,r0,c8,c7,0\r
+ mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+ArmWriteNsacr\r
+ mcr p15, 0, r0, c1, c1, 2\r
+ bx lr\r
+\r
+ArmWriteScr\r
+ mcr p15, 0, r0, c1, c1, 0\r
+ bx lr\r
+\r
+ArmWriteVMBar\r
+ mcr p15, 0, r0, c12, c0, 1\r
+ bx lr\r
+ \r
+ END\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/PcdLib.h>\r
\r
-#include <Chipset/ArmV7.h>\r
-\r
VOID\r
BuildMemoryTypeInformationHob (\r
VOID\r
\r
#include <Ppi/ArmMpCoreInfo.h>\r
\r
-#include <Chipset/ArmV7.h>\r
-\r
#include "PrePeiCore.h"\r
\r
/*\r
*\r
**/\r
\r
-#include <Chipset/ArmV7.h>\r
-\r
#include "PrePeiCore.h"\r
\r
VOID\r
#include <Library/SerialPortLib.h>\r
\r
#include <Ppi/ArmGlobalVariable.h>\r
-#include <Chipset/ArmV7.h>\r
\r
#include "PrePeiCore.h"\r
\r
#include "PrePi.h"\r
\r
#include <Library/ArmGicLib.h>\r
-#include <Chipset/ArmV7.h>\r
\r
VOID\r
PrimaryMain (\r
#include <Library/SerialPortLib.h>\r
#include <Library/ArmPlatformLib.h>\r
\r
-#include <Chipset/ArmV7.h>\r
-\r
#define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1);\r
\r
// Vector Table for PrePi Phase\r
projects / mirror_edk2.git / commitdiff