Add SDHCI controller defines, this is useful as the version in the
register does not explictly map to a specification version. For example
vesion 4.10 of the specification is version 0x04.
https://bugzilla.tianocore.org/show_bug.cgi?id=1233
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
return Status;\r
}\r
\r
- if ((ControllerVer & 0xFF) == 2) {\r
+ if ((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_300) {\r
S18r = TRUE;\r
- } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {\r
+ } else if (((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_100) || ((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_200)) {\r
S18r = FALSE;\r
} else {\r
ASSERT (FALSE);\r
//\r
// Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.\r
//\r
- if ((ControllerVer & 0xFF) == 2) {\r
+ if ((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_300) {\r
ASSERT (Divisor <= 0x3FF);\r
ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);\r
} else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {\r
UINT32 Hs400:1; // bit 63\r
} SD_MMC_HC_SLOT_CAP;\r
\r
+//\r
+// SD Host controller version\r
+//\r
+#define SD_MMC_HC_CTRL_VER_100 0x00\r
+#define SD_MMC_HC_CTRL_VER_200 0x01\r
+#define SD_MMC_HC_CTRL_VER_300 0x02\r
+#define SD_MMC_HC_CTRL_VER_400 0x03\r
+#define SD_MMC_HC_CTRL_VER_410 0x04\r
+#define SD_MMC_HC_CTRL_VER_420 0x05\r
+\r
/**\r
Dump the content of SD/MMC host controller's Capability Register.\r
\r