)\r
{\r
/*// Make the SCU accessible in Non Secure world\r
- if (IS_PRIMARY_CORE(MpId)) {\r
+ if (ArmPlatformIsPrimaryCore (MpId)) {\r
ScuBase = ArmGetScuBaseAddress();\r
\r
// Allow NS access to SCU register\r
[Sources.common]\r
ArmCortexA15Lib.c\r
\r
-[FeaturePcd]\r
-\r
[FixedPcd]\r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
- gArmTokenSpaceGuid.PcdArmPrimaryCore\r
-\r
gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz\r
#include <Base.h>\r
#include <Library/ArmLib.h>\r
#include <Library/ArmCpuLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PcdLib.h>\r
\r
INTN ScuBase;\r
\r
// Make the SCU accessible in Non Secure world\r
- if (IS_PRIMARY_CORE(MpId)) {\r
+ if (ArmPlatformIsPrimaryCore (MpId)) {\r
ScuBase = ArmGetScuBaseAddress();\r
\r
// Allow NS access to SCU register\r
#/* @file\r
-# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
# \r
# This program and the accompanying materials \r
# are licensed and made available under the terms and conditions of the BSD License \r
[Packages]\r
MdePkg/MdePkg.dec\r
ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
\r
[LibraryClasses]\r
ArmLib\r
+ ArmPlatformLib\r
IoLib\r
PcdLib\r
\r
ArmCortexA9Helper.asm | RVCT\r
ArmCortexA9Helper.S | GCC\r
\r
-[FeaturePcd]\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
- gArmTokenSpaceGuid.PcdArmPrimaryCore\r
/** @file\r
*\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
* \r
* This program and the accompanying materials \r
* are licensed and made available under the terms and conditions of the BSD License \r
\r
#include <Base.h>\r
#include <Library/ArmLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/ArmGicLib.h>\r
}\r
\r
// Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r
- if (IS_PRIMARY_CORE(MpId)) {\r
+ if (ArmPlatformIsPrimaryCore (MpId)) {\r
// Ensure all GIC interrupts are Non-Secure\r
for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) {\r
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
\r
[Packages]\r
ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
\r
[LibraryClasses]\r
ArmLib\r
+ ArmPlatformLib\r
DebugLib\r
IoLib\r
PcdLib\r
\r
-[FixedPcd.common]\r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
- gArmTokenSpaceGuid.PcdArmPrimaryCore\r
\r
// Convert the (ClusterId,CoreId) into a Core Position\r
// We assume there are 4 cores per cluster\r
-#define GetCorePositionFromMpId(Pos, MpId, Tmp) \\r
- lsr Pos, MpId, #6 ; \\r
- and Tmp, MpId, #3 ; \\r
+// Note: 0xFFFF is the magic value for ARM_CORE_MASK | ARM_CLUSTER_MASK\r
+#define GetCorePositionFromMpId(Pos, MpId, Tmp) \\r
+ ldr Tmp, =0xFFFF \\r
+ and MpId, Tmp \\r
+ lsr Pos, MpId, #6 ; \\r
+ and Tmp, MpId, #3 ; \\r
add Pos, Pos, Tmp\r
\r
// Reserve a region at the top of the Primary Core stack\r
\r
#define LoadConstantToReg(Data, Reg) \\r
ldr Reg, =Data\r
- \r
-#define GetCorePositionFromMpId(Pos, MpId, Tmp) \\r
- lsr Pos, MpId, #6 ; \\r
- and Tmp, MpId, #3 ; \\r
+\r
+// Convert the (ClusterId,CoreId) into a Core Position\r
+// We assume there are 4 cores per cluster\r
+// Note: 0xFFFF is the magic value for ARM_CORE_MASK | ARM_CLUSTER_MASK\r
+#define GetCorePositionFromMpId(Pos, MpId, Tmp) \\r
+ ldr Tmp, =0xFFFF ; \\r
+ and MpId, Tmp ; \\r
+ lsr Pos, MpId, #6 ; \\r
+ and Tmp, MpId, #3 ; \\r
add Pos, Pos, Tmp\r
\r
#define SetPrimaryStack(StackTop, GlobalSize, Tmp) \\r
\r
MACRO\r
GetCorePositionFromMpId $Pos, $MpId, $Tmp\r
+ ;Note: The ARM macro does not support the pre-processing. 0xFF and (0xFF << 8) are the values of\r
+ ; ARM_CORE_MASK and ARM_CLUSTER_MASK \r
+ mov $Tmp, #(0xFF :OR: (0xFF << 8))\r
+ and $MpId, $Tmp\r
lsr $Pos, $MpId, #6\r
and $Tmp, $MpId, #3\r
add $Pos, $Pos, $Tmp\r
//\r
// ARM MP Core IDs\r
//\r
-#define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))\r
#define ARM_CORE_MASK 0xFF\r
#define ARM_CLUSTER_MASK (0xFF << 8)\r
#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
IN UINTN MpId\r
)\r
{\r
- if (!IS_PRIMARY_CORE(MpId)) {\r
+ if (!ArmPlatformIsPrimaryCore (MpId)) {\r
return RETURN_SUCCESS;\r
}\r
\r
--- /dev/null
+//\r
+// Copyright (c) 2012, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Library/ArmLib.h>\r
+\r
+.text \r
+.align 3\r
+\r
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
+\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
+\r
+//UINTN\r
+//ArmPlatformGetCorePosition (\r
+// IN UINTN MpId\r
+// );\r
+ASM_PFX(ArmPlatformGetCorePosition):\r
+ and r1, r0, #ARM_CORE_MASK\r
+ and r0, r0, #ARM_CLUSTER_MASK\r
+ add r0, r1, r0, LSR #7\r
+ bx lr\r
+\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ASM_PFX(ArmPlatformIsPrimaryCore):\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)\r
+ ldr r1, [r1]\r
+ and r0, r0, r1\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)\r
+ ldr r1, [r1]\r
+ cmp r0, r1\r
+ moveq r0, #1\r
+ movne r0, #0\r
+ bx lr\r
--- /dev/null
+//\r
+// Copyright (c) 2012, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Library/ArmLib.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+\r
+ EXPORT ArmPlatformGetCorePosition\r
+ EXPORT ArmPlatformIsPrimaryCore\r
+\r
+ IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore\r
+ IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask\r
+ \r
+ PRESERVE8\r
+ AREA ArmPlatformNullHelper, CODE, READONLY\r
+\r
+//UINTN\r
+//ArmPlatformGetCorePosition (\r
+// IN UINTN MpId\r
+// );\r
+ArmPlatformGetCorePosition FUNCTION\r
+ and r1, r0, #ARM_CORE_MASK\r
+ and r0, r0, #ARM_CLUSTER_MASK\r
+ add r0, r1, r0, LSR #7\r
+ bx lr\r
+ ENDFUNC\r
+\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ArmPlatformIsPrimaryCore FUNCTION\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)\r
+ ldr r1, [r1]\r
+ and r0, r0, r1\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)\r
+ ldr r1, [r1]\r
+ cmp r0, r1\r
+ moveq r0, #1\r
+ movne r0, #0\r
+ bx lr\r
+ ENDFUNC\r
+\r
+ END\r
+\r
[Sources.common]\r
ArmRealViewEb.c\r
ArmRealViewEbMem.c\r
+ ArmRealViewEbHelper.asm | RVCT\r
+ ArmRealViewEbHelper.S | GCC\r
\r
[FeaturePcd]\r
gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
\r
[Sources.common]\r
ArmRealViewEb.c\r
+ ArmRealViewEbHelper.asm | RVCT\r
+ ArmRealViewEbHelper.S | GCC\r
\r
[FeaturePcd]\r
gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
\r
#include <Library/IoLib.h>\r
#include <Library/ArmLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
#include <Library/ArmPlatformSecLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
)\r
{\r
// If it is not the primary core then there is nothing to do\r
- if (!IS_PRIMARY_CORE(MpId)) {\r
+ if (!ArmPlatformIsPrimaryCore (MpId)) {\r
return RETURN_SUCCESS;\r
}\r
\r
[LibraryClasses]\r
IoLib\r
ArmLib\r
+ ArmPlatformLib\r
\r
[Sources.common]\r
ArmRealViewEbSec.c\r
[FixedPcd]\r
gArmTokenSpaceGuid.PcdFvBaseAddress\r
\r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
- gArmTokenSpaceGuid.PcdArmPrimaryCore\r
gArmTokenSpaceGuid.PcdSystemMemoryBase\r
gArmTokenSpaceGuid.PcdSystemMemorySize\r
gArmTokenSpaceGuid.PcdFvBaseAddress\r
-\r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
- gArmTokenSpaceGuid.PcdArmPrimaryCore\r
IN UINTN MpId\r
)\r
{\r
- if (!IS_PRIMARY_CORE(MpId)) {\r
+ if (!ArmPlatformIsPrimaryCore (MpId)) {\r
return RETURN_SUCCESS;\r
}\r
\r
//\r
-// Copyright (c) 2012, ARM Limited. All rights reserved.\r
+// Copyright (c) 2012-2013, ARM Limited. All rights reserved.\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
//\r
//\r
\r
+#include <AsmMacroIoLib.h>\r
#include <Library/ArmLib.h>\r
\r
+#include <ArmPlatform.h>\r
+\r
.text \r
.align 3\r
\r
GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
\r
//UINTN\r
//ArmPlatformGetCorePosition (\r
add r0, r1, r0, LSR #7\r
bx lr\r
\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ASM_PFX(ArmPlatformIsPrimaryCore):\r
+ // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48\r
+ // with cpu_id[0:3] and cluster_id[4:7]\r
+ LoadConstantToReg (ARM_CTA15A7_SCC_CFGREG48, r1)\r
+ ldr r1, [r1]\r
+ lsr r1, #24\r
+\r
+ // Shift the SCC value to get the cluster ID at the offset #8\r
+ lsl r2, r1, #4\r
+ and r2, r2, #0xF00\r
+\r
+ // Keep only the cpu ID from the original SCC\r
+ and r1, r1, #0x0F\r
+ // Add the Cluster ID to the Cpu ID\r
+ orr r1, r1, r2\r
+\r
+ // Keep the Cluster ID and Core ID from the MPID\r
+ LoadConstantToReg (ARM_CLUSTER_MASK | ARM_CORE_MASK, r2)\r
+ and r0, r0, r2\r
+\r
+ // Compare mpid and boot cpu from ARM_SCC_CFGREG48\r
+ cmp r0, r1\r
+ moveq r0, #1\r
+ movne r0, #0\r
+ bx lr\r
+\r
//\r
-// Copyright (c) 2012, ARM Limited. All rights reserved.\r
+// Copyright (c) 2012-2013, ARM Limited. All rights reserved.\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
//\r
//\r
\r
+#include <AsmMacroIoLib.h>\r
#include <Library/ArmLib.h>\r
\r
+#include <ArmPlatform.h>\r
+\r
INCLUDE AsmMacroIoLib.inc\r
\r
EXPORT ArmPlatformGetCorePosition\r
+ EXPORT ArmPlatformIsPrimaryCore\r
\r
PRESERVE8\r
AREA CTA15A7Helper, CODE, READONLY\r
bx lr\r
ENDFUNC\r
\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ArmPlatformIsPrimaryCore FUNCTION\r
+ // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48\r
+ // with cpu_id[0:3] and cluster_id[4:7]\r
+ LoadConstantToReg (ARM_CTA15A7_SCC_CFGREG48, r1)\r
+ ldr r1, [r1]\r
+ lsr r1, #24\r
+\r
+ // Shift the SCC value to get the cluster ID at the offset #8\r
+ lsl r2, r1, #4\r
+ and r2, r2, #0xF00\r
+\r
+ // Keep only the cpu ID from the original SCC\r
+ and r1, r1, #0x0F\r
+ // Add the Cluster ID to the Cpu ID\r
+ orr r1, r1, r2\r
+\r
+ // Keep the Cluster ID and Core ID from the MPID\r
+ LoadConstantToReg (ARM_CLUSTER_MASK | ARM_CORE_MASK, r2)\r
+ and r0, r0, r2\r
+\r
+ // Compare mpid and boot cpu from ARM_SCC_CFGREG48\r
+ cmp r0, r1\r
+ moveq r0, #1\r
+ movne r0, #0\r
+ bx lr\r
+ ENDFUNC\r
+\r
END\r
[Sources.common]\r
CTA9x4.c\r
CTA9x4Mem.c\r
+ CTA9x4Helper.S | GCC\r
+ CTA9x4Helper.asm | RVCT\r
\r
[FeaturePcd]\r
gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
\r
[Sources.common]\r
CTA9x4.c\r
+ CTA9x4Helper.S | GCC\r
+ CTA9x4Helper.asm | RVCT\r
\r
[FeaturePcd]\r
gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
IN UINTN MpId\r
)\r
{\r
- if (!IS_PRIMARY_CORE(MpId)) {\r
+ if (!ArmPlatformIsPrimaryCore (MpId)) {\r
return RETURN_SUCCESS;\r
}\r
\r
--- /dev/null
+#\r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#\r
+\r
+#include <AsmMacroIoLib.h>\r
+\r
+.text\r
+.align 2\r
+\r
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
+\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
+\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ASM_PFX(ArmPlatformIsPrimaryCore):\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)\r
+ ldr r1, [r1]\r
+ and r0, r0, r1\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)\r
+ ldr r1, [r1]\r
+ cmp r0, r1\r
+ moveq r0, #1\r
+ movne r0, #0\r
+ bx lr\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
--- /dev/null
+//\r
+// Copyright (c) 2013, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+\r
+#include <AutoGen.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+\r
+ EXPORT ArmPlatformIsPrimaryCore\r
+\r
+ IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore\r
+ IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask\r
+\r
+ AREA CTA9x4Helper, CODE, READONLY\r
+\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ArmPlatformIsPrimaryCore FUNCTION\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)\r
+ ldr r1, [r1]\r
+ and r0, r0, r1\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)\r
+ ldr r1, [r1]\r
+ cmp r0, r1\r
+ moveq r0, #1\r
+ movne r0, #0\r
+ bx lr\r
+ ENDFUNC\r
+\r
+ END\r
#\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
# \r
# This program and the accompanying materials \r
# are licensed and made available under the terms and conditions of the BSD License \r
# which accompanies this distribution. The full text of the license may be found at \r
-# http:#opensource.org/licenses/bsd-license.php \r
+# http://opensource.org/licenses/bsd-license.php\r
#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
#include <Base.h>\r
#include <Library/PcdLib.h>\r
#include <AutoGen.h>\r
-#.include AsmMacroIoLib.inc\r
\r
#include <Chipset/ArmCortexA9.h>\r
\r
.align 2\r
\r
GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)\r
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
+\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
\r
# IN None\r
# OUT r0 = SCU Base Address\r
ldmfd SP!, {r1-r2}\r
bx lr\r
\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ASM_PFX(ArmPlatformIsPrimaryCore):\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)\r
+ ldr r1, [r1]\r
+ and r0, r0, r1\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)\r
+ ldr r1, [r1]\r
+ cmp r0, r1\r
+ moveq r0, #1\r
+ movne r0, #0\r
+ bx lr\r
+\r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED \r
//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
// \r
// This program and the accompanying materials \r
// are licensed and made available under the terms and conditions of the BSD License \r
INCLUDE AsmMacroIoLib.inc\r
\r
EXPORT ArmGetCpuCountPerCluster\r
- \r
+ EXPORT ArmPlatformIsPrimaryCore\r
+\r
+ IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore\r
+ IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask\r
+\r
AREA RTSMHelper, CODE, READONLY\r
\r
// IN None\r
// OUT r0 = SCU Base Address\r
-ArmGetScuBaseAddress\r
+ArmGetScuBaseAddress FUNCTION\r
// Read Configuration Base Address Register. ArmCBar cannot be called to get\r
// the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
// offset 0x0000 from the Private Memory Region.\r
mrc p15, 4, r0, c15, c0, 0\r
bx lr\r
+ ENDFUNC\r
\r
// IN None\r
// OUT r0 = number of cores present in the system\r
-ArmGetCpuCountPerCluster\r
+ArmGetCpuCountPerCluster FUNCTION\r
stmfd SP!, {r1-r2}\r
\r
// Read CP15 MIDR\r
add r0, r0, #1\r
ldmfd SP!, {r1-r2}\r
bx lr\r
+ ENDFUNC\r
+\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ArmPlatformIsPrimaryCore FUNCTION\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)\r
+ ldr r1, [r1]\r
+ and r0, r0, r1\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)\r
+ ldr r1, [r1]\r
+ cmp r0, r1\r
+ moveq r0, #1\r
+ movne r0, #0\r
+ bx lr\r
+ ENDFUNC\r
\r
END\r
IN UINTN MpId\r
)\r
{\r
- if (!IS_PRIMARY_CORE(MpId)) {\r
+ if (!ArmPlatformIsPrimaryCore (MpId)) {\r
return RETURN_SUCCESS;\r
}\r
\r
)\r
{\r
// Nothing to do\r
- if (!IS_PRIMARY_CORE(MpId)) {\r
+ if (!ArmPlatformIsPrimaryCore (MpId)) {\r
return;\r
}\r
\r
)\r
{\r
// If it is not the primary core then there is nothing to do\r
- if (!IS_PRIMARY_CORE(MpId)) {\r
+ if (!ArmPlatformIsPrimaryCore (MpId)) {\r
return RETURN_SUCCESS;\r
}\r
\r
+++ /dev/null
-#\r
-# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http:#opensource.org/licenses/bsd-license.php \r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-#\r
-#\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/PcdLib.h>\r
-#include <AutoGen.h>\r
-#.include AsmMacroIoLib.inc\r
-\r
-#include <Chipset/ArmCortexA9.h>\r
-\r
-.text\r
-.align 2\r
-\r
-GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)\r
-\r
-# IN None\r
-# OUT r0 = SCU Base Address\r
-ASM_PFX(ArmGetScuBaseAddress):\r
- # Read Configuration Base Address Register. ArmCBar cannot be called to get\r
- # the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
- # offset 0x0000 from the Private Memory Region.\r
- mrc p15, 4, r0, c15, c0, 0\r
- bx lr\r
-\r
-# IN None\r
-# OUT r0 = number of cores present in the system\r
-ASM_PFX(ArmGetCpuCountPerCluster):\r
- stmfd SP!, {r1-r2}\r
-\r
- # Read CP15 MIDR\r
- mrc p15, 0, r1, c0, c0, 0\r
-\r
- # Check if the CPU is A15\r
- mov r1, r1, LSR #4\r
- LoadConstantToReg (ARM_CPU_TYPE_MASK, r0)\r
- and r1, r1, r0\r
-\r
- LoadConstantToReg (ARM_CPU_TYPE_A15, r0)\r
- cmp r1, r0\r
- beq _Read_cp15_reg\r
-\r
-_CPU_is_not_A15:\r
- mov r2, lr @ Save link register\r
- bl ArmGetScuBaseAddress @ Read SCU Base Address\r
- mov lr, r2 @ Restore link register val\r
- ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] @ Read SCU Config reg to get CPU count\r
- b _Return\r
-\r
-_Read_cp15_reg:\r
- mrc p15, 1, r0, c9, c0, 2 @ Read C9 register of CP15 to get CPU count\r
- lsr r0, #24\r
-\r
-_Return:\r
- and r0, r0, #3\r
- # Add '1' to the number of CPU on the Cluster\r
- add r0, r0, #1\r
- ldmfd SP!, {r1-r2}\r
- bx lr\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED \r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-// \r
-// This program and the accompanying materials \r
-// are licensed and made available under the terms and conditions of the BSD License \r
-// which accompanies this distribution. The full text of the license may be found at \r
-// http://opensource.org/licenses/bsd-license.php \r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#include <Chipset/ArmCortexA9.h>\r
-\r
-#include <AutoGen.h>\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
-\r
- EXPORT ArmGetCpuCountPerCluster\r
- \r
- AREA RTSMHelper, CODE, READONLY\r
-\r
-// IN None\r
-// OUT r0 = SCU Base Address\r
-ArmGetScuBaseAddress\r
- // Read Configuration Base Address Register. ArmCBar cannot be called to get\r
- // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
- // offset 0x0000 from the Private Memory Region.\r
- mrc p15, 4, r0, c15, c0, 0\r
- bx lr\r
-\r
-// IN None\r
-// OUT r0 = number of cores present in the system\r
-ArmGetCpuCountPerCluster\r
- stmfd SP!, {r1-r2}\r
-\r
- // Read CP15 MIDR\r
- mrc p15, 0, r1, c0, c0, 0\r
-\r
- // Check if the CPU is A15\r
- mov r1, r1, LSR #4\r
- mov r0, #ARM_CPU_TYPE_MASK\r
- and r1, r1, r0\r
-\r
- mov r0, #ARM_CPU_TYPE_A15\r
- cmp r1, r0\r
- beq _Read_cp15_reg\r
-\r
-_CPU_is_not_A15\r
- mov r2, lr ; Save link register\r
- bl ArmGetScuBaseAddress ; Read SCU Base Address\r
- mov lr, r2 ; Restore link register val\r
- ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] ; Read SCU Config reg to get CPU count\r
- b _Return\r
-\r
-_Read_cp15_reg\r
- mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get CPU count\r
- lsr r0, #24\r
-\r
-\r
-_Return\r
- and r0, r0, #3\r
- // Add '1' to the number of CPU on the Cluster\r
- add r0, r0, #1\r
- ldmfd SP!, {r1-r2}\r
- bx lr\r
-\r
- END\r
[Sources.ARM]\r
Arm/RTSMBoot.asm | RVCT\r
Arm/RTSMBoot.S | GCC\r
- Arm/RTSMHelper.asm | RVCT\r
- Arm/RTSMHelper.S | GCC\r
\r
[FeaturePcd]\r
gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
)\r
{\r
// If it is not the primary core then there is nothing to do\r
- if (!IS_PRIMARY_CORE(MpId)) {\r
+ if (!ArmPlatformIsPrimaryCore (MpId)) {\r
return RETURN_SUCCESS;\r
}\r
\r
UINT64 NumberOfBytes;\r
} ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR;\r
\r
+/**\r
+ Return the core position from the value of its MpId register\r
+\r
+ This function returns the core position from the position 0 in the processor.\r
+ This function might be called from assembler before any stack is set.\r
+\r
+ @return Return the core position\r
+\r
+**/\r
UINTN\r
ArmPlatformGetCorePosition (\r
IN UINTN MpId\r
);\r
\r
+/**\r
+ Return a non-zero value if the callee is the primary core\r
+\r
+ This function returns a non-zero value if the callee is the primary core.\r
+ The primary core is the core responsible to initialize the hardware and run UEFI.\r
+ This function might be called from assembler before any stack is set.\r
+\r
+ @return Return a non-zero value if the callee is the primary core.\r
+\r
+**/\r
+UINTN\r
+ArmPlatformIsPrimaryCore (\r
+ IN UINTN MpId\r
+ );\r
+\r
/**\r
Return the current Boot Mode\r
\r
//\r
//\r
\r
+#include <AsmMacroIoLib.h>\r
#include <Library/ArmLib.h>\r
\r
.text \r
.align 3\r
\r
GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
+\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
\r
//UINTN\r
//ArmPlatformGetCorePosition (\r
add r0, r1, r0, LSR #7\r
bx lr\r
\r
+\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ASM_PFX(ArmPlatformIsPrimaryCore):\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)\r
+ ldr r1, [r1]\r
+ and r0, r0, r1\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)\r
+ ldr r1, [r1]\r
+ cmp r0, r1\r
+ moveq r0, #1\r
+ movne r0, #0\r
+ bx lr\r
INCLUDE AsmMacroIoLib.inc\r
\r
EXPORT ArmPlatformGetCorePosition\r
+ EXPORT ArmPlatformIsPrimaryCore\r
\r
+ IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore\r
+ IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask\r
+ \r
PRESERVE8\r
AREA ArmPlatformNullHelper, CODE, READONLY\r
\r
bx lr\r
ENDFUNC\r
\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ArmPlatformIsPrimaryCore FUNCTION\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)\r
+ ldr r1, [r1]\r
+ and r0, r0, r1\r
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)\r
+ ldr r1, [r1]\r
+ cmp r0, r1\r
+ moveq r0, #1\r
+ movne r0, #0\r
+ bx lr\r
+ ENDFUNC\r
+\r
END\r
\r
IN UINTN MpId\r
)\r
{\r
- if (!IS_PRIMARY_CORE(MpId)) {\r
+ if (!ArmPlatformIsPrimaryCore (MpId)) {\r
return RETURN_SUCCESS;\r
}\r
\r
)\r
{\r
// Secondary cores might have to set the Secure SGIs into the GICD_IGROUPR0\r
- if (!IS_PRIMARY_CORE(MpId)) {\r
+ if (!ArmPlatformIsPrimaryCore (MpId)) {\r
return;\r
}\r
\r
)\r
{\r
// If it is not the primary core then there is nothing to do\r
- if (!IS_PRIMARY_CORE(MpId)) {\r
+ if (!ArmPlatformIsPrimaryCore (MpId)) {\r
return RETURN_SUCCESS;\r
}\r
\r
\r
#include <Library/ArmLib.h>\r
#include <Library/ArmGicLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
#include <Library/ArmPlatformSecLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
// Warning: This code assumes the DRAM has already been initialized by ArmPlatformSecLib\r
//\r
\r
- if (IS_PRIMARY_CORE(MpId)) {\r
+ if (ArmPlatformIsPrimaryCore (MpId)) {\r
UINTN* StartAddress = (UINTN*)PcdGet32(PcdFvBaseAddress);\r
\r
// Patch the DRAM to make an infinite loop at the start address\r
// Warning: This code assumes the DRAM has already been initialized by ArmPlatformSecLib\r
//\r
\r
- if (IS_PRIMARY_CORE(MpId)) {\r
+ if (ArmPlatformIsPrimaryCore (MpId)) {\r
// Signal the secondary cores they can jump to PEI phase\r
ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
\r
\r
[Packages]\r
MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
ArmPkg/ArmPkg.dec\r
ArmPlatformPkg/ArmPlatformPkg.dec\r
\r
[LibraryClasses]\r
+ ArmPlatformLib\r
DebugLib\r
PcdLib\r
ArmGicLib\r
\r
[FixedPcd]\r
gArmTokenSpaceGuid.PcdFvBaseAddress\r
- \r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
- gArmTokenSpaceGuid.PcdArmPrimaryCore\r
\r
gArmTokenSpaceGuid.PcdGicDistributorBase\r
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
// \r
// This program and the accompanying materials \r
// are licensed and made available under the terms and conditions of the BSD License \r
.align 3\r
\r
GCC_ASM_IMPORT(CEntryPoint)\r
+GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r
GCC_ASM_IMPORT(ArmReadMpidr)\r
GCC_ASM_EXPORT(_ModuleEntryPoint)\r
\r
ASM_PFX(_ModuleEntryPoint):\r
// Identify CPU ID\r
bl ASM_PFX(ArmReadMpidr)\r
- // Get ID of this CPU in Multicore system\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
- and r5, r0, r1\r
- \r
+ // Keep a copy of the MpId register value\r
+ mov r5, r0\r
+\r
+ // Is it the Primary Core ?\r
+ bl ASM_PFX(ArmPlatformIsPrimaryCore)\r
+\r
// Get the top of the primary stacks (and the base of the secondary stacks)\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresStackBase), r1)\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
add r1, r1, r2\r
\r
- // Is it the Primary Core ?\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
- cmp r5, r3\r
+ // r0 is equal to 1 if I am the primary core\r
+ cmp r0, #1\r
beq _SetupPrimaryCoreStack\r
\r
_SetupSecondaryCoreStack:\r
//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
// \r
// This program and the accompanying materials \r
// are licensed and made available under the terms and conditions of the BSD License \r
INCLUDE AsmMacroIoLib.inc\r
\r
IMPORT CEntryPoint\r
+ IMPORT ArmPlatformIsPrimaryCore\r
IMPORT ArmReadMpidr\r
EXPORT _ModuleEntryPoint\r
\r
_ModuleEntryPoint\r
// Identify CPU ID\r
bl ArmReadMpidr\r
- // Get ID of this CPU in Multicore system\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
- and r5, r0, r1\r
+ // Keep a copy of the MpId register value\r
+ mov r5, r0\r
\r
+ // Is it the Primary Core ?\r
+ bl ArmPlatformIsPrimaryCore\r
+\r
// Get the top of the primary stacks (and the base of the secondary stacks)\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresStackBase), r1)\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
add r1, r1, r2\r
\r
- // Is it the Primary Core ?\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
- cmp r5, r3\r
+ // r0 is equal to 1 if I am the primary core\r
+ cmp r0, #1\r
beq _SetupPrimaryCoreStack\r
\r
_SetupSecondaryCoreStack\r
//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r
\r
// If not primary Jump to Secondary Main\r
- if (IS_PRIMARY_CORE(MpId)) {\r
+ if (ArmPlatformIsPrimaryCore (MpId)) {\r
// Initialize the Debug Agent for Source Level Debugging\r
InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r
SaveAndSetDebugTimerInterrupt (TRUE);\r
gArmTokenSpaceGuid.PcdFvBaseAddress\r
gArmTokenSpaceGuid.PcdFvSize\r
\r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
gArmTokenSpaceGuid.PcdArmPrimaryCore\r
gArmTokenSpaceGuid.PcdGicPrimaryCoreId\r
\r
gArmTokenSpaceGuid.PcdFvBaseAddress\r
gArmTokenSpaceGuid.PcdFvSize\r
\r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
- gArmTokenSpaceGuid.PcdArmPrimaryCore\r
-\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase\r
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize\r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize\r
.align 3\r
\r
GCC_ASM_IMPORT(CEntryPoint)\r
+GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r
GCC_ASM_IMPORT(ArmReadMpidr)\r
GCC_ASM_IMPORT(ArmPlatformStackSet)\r
GCC_ASM_EXPORT(_ModuleEntryPoint)\r
ASM_PFX(_ModuleEntryPoint):\r
// Get ID of this CPU in Multicore system\r
bl ASM_PFX(ArmReadMpidr)\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
- and r6, r0, r1\r
+ // Keep a copy of the MpId register value\r
+ mov r6, r0\r
\r
_SetSVCMode:\r
// Enter SVC mode, Disable FIQ and IRQ\r
bl ASM_PFX(ArmPlatformStackSet)\r
\r
// Is it the Primary Core ?\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r4)\r
- cmp r6, r4\r
+ mov r0, r6\r
+ bl ASM_PFX(ArmPlatformIsPrimaryCore)\r
+ cmp r0, #1\r
bne _PrepareArguments\r
\r
_ReserveGlobalVariable:\r
INCLUDE AsmMacroIoLib.inc\r
\r
IMPORT CEntryPoint\r
+ IMPORT ArmPlatformIsPrimaryCore\r
IMPORT ArmReadMpidr\r
IMPORT ArmPlatformStackSet\r
\r
_ModuleEntryPoint\r
// Get ID of this CPU in Multicore system\r
bl ArmReadMpidr\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
- and r6, r0, r1\r
+ // Keep a copy of the MpId register value\r
+ mov r6, r0\r
\r
_SetSVCMode\r
// Enter SVC mode, Disable FIQ and IRQ\r
bl ArmPlatformStackSet\r
\r
// Is it the Primary Core ?\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r4)\r
- cmp r6, r4\r
+ mov r0, r6\r
+ bl ArmPlatformIsPrimaryCore\r
+ cmp r0, #1\r
bne _PrepareArguments\r
\r
_ReserveGlobalVariable\r
\r
gArmPlatformTokenSpaceGuid.PcdCoreCount\r
gArmPlatformTokenSpaceGuid.PcdClusterCount\r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
gArmTokenSpaceGuid.PcdArmPrimaryCore\r
gArmTokenSpaceGuid.PcdGicPrimaryCoreId\r
\r
\r
gArmPlatformTokenSpaceGuid.PcdCoreCount\r
gArmPlatformTokenSpaceGuid.PcdClusterCount\r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
- gArmTokenSpaceGuid.PcdArmPrimaryCore\r
\r
gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize\r
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize\r
// Initialize the platform specific controllers\r
ArmPlatformInitialize (MpId);\r
\r
- if (IS_PRIMARY_CORE(MpId) && PerformanceMeasurementEnabled ()) {\r
+ if (ArmPlatformIsPrimaryCore (MpId) && PerformanceMeasurementEnabled ()) {\r
// Initialize the Timer Library to setup the Timer HW controller\r
TimerConstructor ();\r
// We cannot call yet the PerformanceLib because the HOB List has not been initialized\r
\r
// Define the Global Variable region when we are not running in XIP\r
if (!IS_XIP()) {\r
- if (IS_PRIMARY_CORE(MpId)) {\r
+ if (ArmPlatformIsPrimaryCore (MpId)) {\r
mGlobalVariableBase = GlobalVariableBase;\r
if (ArmIsMpCore()) {\r
// Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)\r
}\r
\r
// If not primary Jump to Secondary Main\r
- if (IS_PRIMARY_CORE(MpId)) {\r
+ if (ArmPlatformIsPrimaryCore (MpId)) {\r
// Goto primary Main.\r
PrimaryMain (UefiMemoryBase, StacksBase, GlobalVariableBase, StartTimeStamp);\r
} else {\r
#========================================================================================\r
-# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
# \r
# This program and the accompanying materials \r
# are licensed and made available under the terms and conditions of the BSD License \r
# which accompanies this distribution. The full text of the license may be found at \r
-# http:#opensource.org/licenses/bsd-license.php \r
+# http://opensource.org/licenses/bsd-license.php\r
#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
//\r
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
// \r
// This program and the accompanying materials \r
// are licensed and made available under the terms and conditions of the BSD License \r
.align 3\r
\r
GCC_ASM_IMPORT(CEntryPoint)\r
+GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r
GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r
GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)\r
GCC_ASM_IMPORT(ArmDisableInterrupts)\r
_IdentifyCpu:\r
// Identify CPU ID\r
bl ASM_PFX(ArmReadMpidr)\r
- // Get ID of this CPU in Multicore system\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
- and r5, r0, r1\r
+ // Keep a copy of the MpId register value\r
+ mov r9, r0\r
\r
// Is it the Primary Core ?\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
- cmp r5, r3\r
+ bl ASM_PFX(ArmPlatformIsPrimaryCore)\r
+ cmp r0, #1\r
// Only the primary core initialize the memory (SMC)\r
beq _InitMem\r
\r
// Initialize Init Boot Memory\r
bl ASM_PFX(ArmPlatformSecBootMemoryInit)\r
\r
- // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)\r
-\r
_SetupPrimaryCoreStack:\r
// Get the top of the primary stacks (and the base of the secondary stacks)\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
add r1, r1, r2\r
\r
// Get the Core Position (ClusterId * 4) + CoreId\r
- GetCorePositionFromMpId(r0, r5, r2)\r
+ GetCorePositionFromMpId(r0, r9, r2)\r
// The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
add r0, r0, #1\r
\r
// Jump to SEC C code\r
// r0 = mp_id\r
// r1 = Boot Mode\r
- mov r0, r5\r
+ mov r0, r9\r
mov r1, r10\r
blx r3\r
\r
//\r
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
// \r
// This program and the accompanying materials \r
// are licensed and made available under the terms and conditions of the BSD License \r
INCLUDE AsmMacroIoLib.inc\r
\r
IMPORT CEntryPoint\r
+ IMPORT ArmPlatformIsPrimaryCore\r
IMPORT ArmPlatformSecBootAction\r
IMPORT ArmPlatformSecBootMemoryInit\r
IMPORT ArmDisableInterrupts\r
_IdentifyCpu \r
// Identify CPU ID\r
bl ArmReadMpidr\r
- // Get ID of this CPU in Multicore system\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
- and r5, r0, r1\r
+ // Keep a copy of the MpId register value\r
+ mov r9, r0\r
\r
// Is it the Primary Core ?\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
- cmp r5, r3\r
+ bl ArmPlatformIsPrimaryCore\r
+ cmp r0, #1\r
// Only the primary core initialize the memory (SMC)\r
beq _InitMem\r
\r
// Initialize Init Boot Memory\r
bl ArmPlatformSecBootMemoryInit\r
\r
- // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)\r
-\r
_SetupPrimaryCoreStack\r
// Get the top of the primary stacks (and the base of the secondary stacks)\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
add r1, r1, r2\r
\r
// Get the Core Position (ClusterId * 4) + CoreId\r
- GetCorePositionFromMpId(r0, r5, r2)\r
+ GetCorePositionFromMpId(r0, r9, r2)\r
// The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
add r0, r0, #1\r
\r
// Jump to SEC C code\r
// r0 = mp_id\r
// r1 = Boot Mode\r
- mov r0, r5\r
+ mov r0, r9\r
mov r1, r10\r
blx r3\r
ENDFUNC\r
ArmPlatformSecInitialize (MpId);\r
\r
// Primary CPU clears out the SCU tag RAMs, secondaries wait\r
- if (IS_PRIMARY_CORE(MpId) && (SecBootMode == ARM_SEC_COLD_BOOT)) {\r
+ if (ArmPlatformIsPrimaryCore (MpId) && (SecBootMode == ARM_SEC_COLD_BOOT)) {\r
if (ArmIsMpCore()) {\r
// Signal for the initial memory is configured (event: BOOT_MEM_INIT)\r
ArmCallSEV ();\r
// Enter Monitor Mode\r
enter_monitor_mode ((UINTN)TrustedWorldInitialization, MpId, SecBootMode, (VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * (GET_CORE_POS(MpId) + 1))));\r
} else {\r
- if (IS_PRIMARY_CORE(MpId)) {\r
+ if (ArmPlatformIsPrimaryCore (MpId)) {\r
SerialPrint ("Trust Zone Configuration is disabled\n\r");\r
}\r
\r
\r
// Setup the Trustzone Chipsets\r
if (SecBootMode == ARM_SEC_COLD_BOOT) {\r
- if (IS_PRIMARY_CORE(MpId)) {\r
+ if (ArmPlatformIsPrimaryCore (MpId)) {\r
if (ArmIsMpCore()) {\r
// Signal the secondary core the Security settings is done (event: EVENT_SECURE_INIT)\r
ArmCallSEV ();\r
[LibraryClasses]\r
ArmCpuLib\r
ArmLib\r
+ ArmPlatformLib\r
ArmPlatformSecLib\r
ArmTrustedMonitorLib\r
BaseLib\r
gArmTokenSpaceGuid.PcdArmNsacr\r
gArmTokenSpaceGuid.PcdArmNonSecModeTransition\r
\r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
- gArmTokenSpaceGuid.PcdArmPrimaryCore\r
- \r
gArmTokenSpaceGuid.PcdSecureFvBaseAddress\r
gArmTokenSpaceGuid.PcdSecureFvSize\r
\r
gArmTokenSpaceGuid.PcdFvBaseAddress\r
- \r
+\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase\r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize\r
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize\r
#include <Base.h>\r
#include <Library/ArmLib.h>\r
#include <Library/ArmCpuLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
#include <Library/ArmPlatformSecLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
--- /dev/null
+#\r
+# Copyright (c) 2012, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <AutoGen.h>\r
+\r
+.text\r
+.align 2\r
+\r
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
+\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ASM_PFX(ArmPlatformIsPrimaryCore):\r
+ // BeagleBoard has a single core. We must always return 1.\r
+ mov r0, #1\r
+ bx lr\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED \r
--- /dev/null
+//\r
+// Copyright (c) 2012, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+\r
+#include <AutoGen.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+\r
+ EXPORT ArmPlatformIsPrimaryCore\r
+\r
+ AREA BeagleBoardHelper, CODE, READONLY\r
+\r
+//UINTN\r
+//ArmPlatformIsPrimaryCore (\r
+// IN UINTN MpId\r
+// );\r
+ArmPlatformIsPrimaryCore FUNCTION\r
+ // BeagleBoard has a single core. We must always return 1.\r
+ mov r0, #1\r
+ bx lr\r
+ ENDFUNC\r
+\r
+ END\r
+\r
BeagleBoardMem.c\r
PadConfiguration.c\r
Clock.c\r
+ BeagleBoardHelper.S | GCC\r
+ BeagleBoardHelper.asm | RVCT\r
\r
[Protocols]\r
\r
projects / mirror_edk2.git / commitdiff