//\r
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+// Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// Get ID of this CPU in Multicore system\r
bl ASM_PFX(ArmReadMpidr)\r
// Keep a copy of the MpId register value\r
- mov r6, r0\r
+ mov r8, r0\r
\r
_SetSVCMode:\r
// Enter SVC mode, Disable FIQ and IRQ\r
// Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment\r
// one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the\r
// top of the memory space)\r
- adds r7, r1, #1\r
+ adds r9, r1, #1\r
bcs _SetupOverflowStack\r
\r
_SetupAlignedStack:\r
- mov r1, r7\r
+ mov r1, r9\r
b _GetBaseUefiMemory\r
\r
_SetupOverflowStack:\r
// Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE\r
// aligned (4KB)\r
- LoadConstantToReg (EFI_PAGE_MASK, r7)\r
- and r7, r7, r1\r
- sub r1, r1, r7\r
+ LoadConstantToReg (EFI_PAGE_MASK, r9)\r
+ and r9, r9, r1\r
+ sub r1, r1, r9\r
\r
_GetBaseUefiMemory:\r
// Calculate the Base of the UEFI Memory\r
- sub r7, r1, r4\r
+ sub r9, r1, r4\r
\r
_GetStackBase:\r
// r1 = The top of the Mpcore Stacks\r
// Stack for the primary core = PrimaryCoreStack\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
- sub r8, r1, r2\r
+ sub r10, r1, r2\r
\r
// Stack for the secondary core = Number of Cores - 1\r
LoadConstantToReg (FixedPcdGet32(PcdCoreCount), r0)\r
sub r0, r0, #1\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r1)\r
mul r1, r1, r0\r
- sub r8, r8, r1\r
+ sub r10, r10, r1\r
\r
- // r8 = The base of the MpCore Stacks (primary stack & secondary stacks)\r
- mov r0, r8\r
- mov r1, r6\r
+ // r10 = The base of the MpCore Stacks (primary stack & secondary stacks)\r
+ mov r0, r10\r
+ mov r1, r8\r
//ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3)\r
bl ASM_PFX(ArmPlatformStackSet)\r
\r
// Is it the Primary Core ?\r
- mov r0, r6\r
+ mov r0, r8\r
bl ASM_PFX(ArmPlatformIsPrimaryCore)\r
cmp r0, #1\r
bne _PrepareArguments\r
InitializePrimaryStack(r0, r1)\r
\r
_PrepareArguments:\r
- mov r0, r6\r
- mov r1, r7\r
- mov r2, r8\r
+ mov r0, r8\r
+ mov r1, r9\r
+ mov r2, r10\r
mov r3, sp\r
\r
// Move sec startup address into a data register\r
//\r
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+// Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// Get ID of this CPU in Multicore system\r
bl ArmReadMpidr\r
// Keep a copy of the MpId register value\r
- mov r6, r0\r
+ mov r8, r0\r
\r
_SetSVCMode\r
// Enter SVC mode, Disable FIQ and IRQ\r
// Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment\r
// one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the\r
// top of the memory space)\r
- adds r7, r1, #1\r
+ adds r9, r1, #1\r
bcs _SetupOverflowStack\r
\r
_SetupAlignedStack\r
- mov r1, r7\r
+ mov r1, r9\r
b _GetBaseUefiMemory\r
\r
_SetupOverflowStack\r
// Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE\r
// aligned (4KB)\r
- LoadConstantToReg (EFI_PAGE_MASK, r7)\r
- and r7, r7, r1\r
- sub r1, r1, r7\r
+ LoadConstantToReg (EFI_PAGE_MASK, r9)\r
+ and r9, r9, r1\r
+ sub r1, r1, r9\r
\r
_GetBaseUefiMemory\r
// Calculate the Base of the UEFI Memory\r
- sub r7, r1, r4\r
+ sub r9, r1, r4\r
\r
_GetStackBase\r
// r1 = The top of the Mpcore Stacks\r
// Stack for the primary core = PrimaryCoreStack\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
- sub r8, r1, r2\r
+ sub r10, r1, r2\r
\r
// Stack for the secondary core = Number of Cores - 1\r
LoadConstantToReg (FixedPcdGet32(PcdCoreCount), r0)\r
sub r0, r0, #1\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r1)\r
mul r1, r1, r0\r
- sub r8, r8, r1\r
+ sub r10, r10, r1\r
\r
- // r8 = The base of the MpCore Stacks (primary stack & secondary stacks)\r
- mov r0, r8\r
- mov r1, r6\r
+ // r10 = The base of the MpCore Stacks (primary stack & secondary stacks)\r
+ mov r0, r10\r
+ mov r1, r8\r
//ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3)\r
bl ArmPlatformStackSet\r
\r
// Is it the Primary Core ?\r
- mov r0, r6\r
+ mov r0, r8\r
bl ArmPlatformIsPrimaryCore\r
cmp r0, #1\r
bne _PrepareArguments\r
InitializePrimaryStack r0, r1\r
\r
_PrepareArguments\r
- mov r0, r6\r
- mov r1, r7\r
- mov r2, r8\r
+ mov r0, r8\r
+ mov r1, r9\r
+ mov r2, r10\r
mov r3, sp\r
\r
// Move sec startup address into a data register\r