ArmPkg: Fix typo in comment and trailing spaces

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15378 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index f11243f236058b81b42b245a47f260ac279a80ff..5efef7c9d61bd7a02313718cdb6ee1415ab8c282 100644 (file)
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -2,7 +2,7 @@
 # ARM processor package.\r
 #\r
 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
 #\r
 #    This program and the accompanying materials\r
 #    are licensed and made available under the terms and conditions of the BSD License\r
@@ -38,7 +38,7 @@
   UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h\r
   DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r
   ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r
-  \r
+\r
 [Guids.common]\r
   gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r
 \r
@@ -64,10 +64,10 @@
   # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r
   # it has been configured by the CPU DXE\r
   gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r
-  \r
+\r
   # Define if the Power State Coordination Interface (PSCI) is supported by the Platform Trusted Firmware\r
   gArmTokenSpaceGuid.PcdArmPsciSupport|FALSE|BOOLEAN|0x00000033\r
-  \r
+\r
 [PcdsFixedAtBuild.common]\r
   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r
 \r
@@ -79,9 +79,9 @@
   gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003\r
   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004\r
   gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r
-  \r
+\r
   #\r
-  # ARM General Interrupt Controller\r
+  # ARM Generic Interrupt Controller\r
   #\r
   gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C\r
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r
@@ -102,10 +102,10 @@
   gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
   gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D\r
   gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
- \r
+\r
   #\r
   # ARM Hypervisor Firmware PCDs\r
-  #  \r
+  #\r
   gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A\r
   gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B\r
   gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C\r
@@ -113,21 +113,21 @@
 \r
   # System Memory (DRAM): These PCDs define the region of in-built system memory\r
   # Some platforms can get DRAM extensions, these additional regions will be declared\r
-  # to UEFI by ArmPLatformPlib   \r
+  # to UEFI by ArmPlatformLib\r
   gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r
   gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r
 \r
   # Use ClusterId + CoreId to identify the PrimaryCore\r
   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r
-  # The Primary Core is ClusterId[0] & CoreId[0] \r
+  # The Primary Core is ClusterId[0] & CoreId[0]\r
   gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r
 \r
   #\r
   # ARM L2x0 PCDs\r
   #\r
   gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B\r
-  \r
-  # \r
+\r
+  #\r
   # BdsLib\r
   #\r
   gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E\r
@@ -139,7 +139,7 @@
   #\r
   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r
   # ARM Architectural Timer Interrupt(GIC PPI) number\r
-  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035  \r
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035\r
   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r
 \r
 [PcdsFixedAtBuild.ARM]\r
@@ -207,8 +207,8 @@
 \r
   # By default we do transition to EL2 non-secure mode with Stack for EL2.\r
   #        Mode Description              Bits\r
-  # NS EL2 SP2 all interupts disabled =  0x3c9\r
-  # NS EL1 SP1 all interupts disabled =  0x3c5\r
+  # NS EL2 SP2 all interrupts disabled =  0x3c9\r
+  # NS EL1 SP1 all interrupts disabled =  0x3c5\r
   # Other modes include using SP0 or switching to Aarch32, but these are\r
   # not currently supported.\r
   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r