UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmiCr3" with PatchInstructionX86()

Rename the variable to "gPatchSmiCr3" so that its association with
PatchInstructionX86() is clear from the declaration, change its type to
X86_ASSEMBLY_PATCH_LABEL, and patch it with PatchInstructionX86(). This
lets us remove the binary (DB) encoding of some instructions in
"SmiEntry.nasm".

Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
index 0ea3c1e4498dbc1f434267c53abea02eb3dc828c..0023cb328d6a6e52943560058a789bf0b39272ae 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
@@ -44,7 +44,7 @@ extern ASM_PFX(CpuSmmDebugExit)
 \r
 global ASM_PFX(gcSmiHandlerTemplate)\r
 global ASM_PFX(gcSmiHandlerSize)\r
-global ASM_PFX(gSmiCr3)\r
+global ASM_PFX(gPatchSmiCr3)\r
 global ASM_PFX(gPatchSmiStack)\r
 global ASM_PFX(gPatchSmbase)\r
 global ASM_PFX(mXdSupported)\r
@@ -93,8 +93,8 @@ ASM_PFX(gPatchSmiStack):
     jmp     ProtFlatMode\r
 \r
 ProtFlatMode:\r
-    DB      0xb8                        ; mov eax, imm32\r
-ASM_PFX(gSmiCr3): DD 0\r
+    mov eax, strict dword 0               ; source operand will be patched\r
+ASM_PFX(gPatchSmiCr3):\r
     mov     cr3, eax\r
 ;\r
 ; Need to test for CR4 specific bit support\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
index f0c289254330d3949a0f00dcd3fcc98818c13b9f..5c2eb9ab6a1e28c1e56b60940eca492883ef9b64 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
@@ -107,7 +107,7 @@ typedef struct {
 ///\r
 X86_ASSEMBLY_PATCH_LABEL gPatchSmbase;\r
 X86_ASSEMBLY_PATCH_LABEL gPatchSmiStack;\r
-extern UINT32            gSmiCr3;\r
+X86_ASSEMBLY_PATCH_LABEL gPatchSmiCr3;\r
 extern volatile UINT8    gcSmiHandlerTemplate[];\r
 extern CONST UINT16      gcSmiHandlerSize;\r
 \r
@@ -719,7 +719,7 @@ InstallSmiHandler (
   //\r
   CpuSmiStack = (UINT32)((UINTN)SmiStack + StackSize - sizeof (UINTN));\r
   PatchInstructionX86 (gPatchSmiStack, CpuSmiStack, 4);\r
-  gSmiCr3               = Cr3;\r
+  PatchInstructionX86 (gPatchSmiCr3, Cr3, 4);\r
   PatchInstructionX86 (gPatchSmbase, SmBase, 4);\r
   gSmiHandlerIdtr.Base  = IdtBase;\r
   gSmiHandlerIdtr.Limit = (UINT16)(IdtSize - 1);\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index 9cfa8e7fc8f49c56057d2502a2b095e2e35d9701..9971ae6f064a8023e4fd0047492fbfd89fa8a3b4 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -56,7 +56,7 @@ extern ASM_PFX(CpuSmmDebugExit)
 global ASM_PFX(gPatchSmbase)\r
 global ASM_PFX(mXdSupported)\r
 global ASM_PFX(gPatchSmiStack)\r
-global ASM_PFX(gSmiCr3)\r
+global ASM_PFX(gPatchSmiCr3)\r
 global ASM_PFX(gcSmiHandlerTemplate)\r
 global ASM_PFX(gcSmiHandlerSize)\r
 \r
@@ -102,8 +102,8 @@ ASM_PFX(gPatchSmiStack):
 \r
 BITS 64\r
 ProtFlatMode:\r
-    DB      0xb8                        ; mov eax, offset gSmiCr3\r
-ASM_PFX(gSmiCr3): DD 0\r
+    mov eax, strict dword 0               ; source operand will be patched\r
+ASM_PFX(gPatchSmiCr3):\r
     mov     cr3, rax\r
     mov     eax, 0x668                   ; as cr4.PGE is not set here, refresh cr3\r
     mov     cr4, rax                    ; in PreModifyMtrrs() to flush TLB.\r