IntelFsp2WrapperPkg: Update BaseFspWrapperApiLib to pass XCODE5 build

XCODE5 doesn't support absolute addressing in the assembly code.
This change uses lea instruction to get the address.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>

diff --git a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/Thunk64To32.nasm b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/Thunk64To32.nasm
index bcc6d70a7383c068841976bb9f15e3b593aacb02..a6ad6cf48790bb80bdbde881202de4b27918fb99 100644 (file)
--- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/Thunk64To32.nasm
+++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/Thunk64To32.nasm
@@ -1,5 +1,5 @@
 ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -81,7 +81,7 @@ ASM_PFX(AsmExecute32BitCode):
     ;\r
     mov     rax, dword 0x10              ; load long mode selector\r
     shl     rax, 32\r
-    mov     r9,  ReloadCS          ;Assume the ReloadCS is under 4G\r
+    lea     r9,  [ReloadCS]          ;Assume the ReloadCS is under 4G\r
     or      rax, r9\r
     push    rax\r
     ;\r
@@ -95,7 +95,7 @@ ASM_PFX(AsmExecute32BitCode):
     ; save the 32-bit function entry and the return address into stack which will be\r
     ; retrieve in compatibility mode.\r
     ;\r
-    mov     rax, ReturnBack   ;Assume the ReloadCS is under 4G\r
+    lea     rax, [ReturnBack]   ;Assume the ReloadCS is under 4G\r
     shl     rax, 32\r
     or      rax, rcx\r
     push    rax\r
@@ -110,7 +110,7 @@ ASM_PFX(AsmExecute32BitCode):
     ;\r
     mov     rcx, dword 0x8               ; load compatible mode selector\r
     shl     rcx, 32\r
-    mov     rdx, Compatible ; assume address < 4G\r
+    lea     rdx, [Compatible] ; assume address < 4G\r
     or      rcx, rdx\r
     push    rcx\r
     retf\r
@@ -208,7 +208,7 @@ ReloadCS:
     ;\r
     pop     r9                 ; get  CS\r
     shl     r9,  32            ; rcx[32..47] <- Cs\r
-    mov     rcx, .0\r
+    lea     rcx, [.0]\r
     or      rcx, r9\r
     push    rcx\r
     retf\r