--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <ArmPlatform.h>\r
+#include <AutoGen.h>\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)\r
+\r
+/**\r
+ Initialize the memory where the initial stacks will reside\r
+\r
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
+ In some platform, this region is already initialized and the implementation of this function can\r
+ do nothing. This memory can also represent the Secure RAM.\r
+ This function is called before the satck has been set up. Its implementation must ensure the stack\r
+ pointer is not used (probably required to use assembly language)\r
+\r
+**/\r
+ASM_PFX(ArmPlatformInitializeBootMemory):\r
+ // The SMC does not need to be initialized for RTSM\r
+ bx lr\r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <ArmPlatform.h>\r
+#include <AutoGen.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+\r
+ EXPORT ArmPlatformInitializeBootMemory\r
+\r
+ PRESERVE8\r
+ AREA CTA9x4BootMode, CODE, READONLY\r
+\r
+/**\r
+ Initialize the memory where the initial stacks will reside\r
+\r
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
+ In some platform, this region is already initialized and the implementation of this function can\r
+ do nothing. This memory can also represent the Secure RAM.\r
+ This function is called before the satck has been set up. Its implementation must ensure the stack\r
+ pointer is not used (probably required to use assembly language)\r
+\r
+**/\r
+ArmPlatformInitializeBootMemory\r
+ // The SMC does not need to be initialized for RTSM\r
+ bx lr\r
#include <AsmMacroIoLib.h>\r
#include <Base.h>\r
#include <Library/PcdLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
#include <ArmPlatform.h>\r
#include <AutoGen.h>\r
\r
-#Start of Code section\r
.text\r
.align 3\r
\r
-GCC_ASM_EXPORT(ArmPlatformIsMemoryInitialized)\r
GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)\r
\r
/**\r
tst r0, #0x200\r
bx lr\r
\r
-/**\r
- Initialize the memory where the initial stacks will reside\r
-\r
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
- In some platform, this region is already initialized and the implementation of this function can\r
- do nothing. This memory can also represent the Secure RAM.\r
- This function is called before the satck has been set up. Its implementation must ensure the stack\r
- pointer is not used (probably required to use assembly language)\r
-\r
-**/\r
-ASM_PFX(ArmPlatformInitializeBootMemory):\r
- // The SMC does not need to be initialized for RTSM\r
- bx lr\r
-\r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
\ No newline at end of file
//\r
// Copyright (c) 2011, ARM Limited. All rights reserved.\r
-// \r
-// This program and the accompanying materials \r
-// are licensed and made available under the terms and conditions of the BSD License \r
-// which accompanies this distribution. The full text of the license may be found at \r
-// http://opensource.org/licenses/bsd-license.php \r
//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
//\r
\r
#include <AsmMacroIoLib.h>\r
#include <Base.h>\r
#include <Library/PcdLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
#include <ArmPlatform.h>\r
#include <AutoGen.h>\r
\r
INCLUDE AsmMacroIoLib.inc\r
\r
EXPORT ArmPlatformIsMemoryInitialized\r
- EXPORT ArmPlatformInitializeBootMemory\r
\r
PRESERVE8\r
AREA ArmRealViewEbHelper, CODE, READONLY\r
and r0, r0, #0x200\r
tst r0, #0x200\r
bx lr\r
- \r
-/**\r
- Initialize the memory where the initial stacks will reside\r
-\r
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
- In some platform, this region is already initialized and the implementation of this function can\r
- do nothing. This memory can also represent the Secure RAM.\r
- This function is called before the satck has been set up. Its implementation must ensure the stack\r
- pointer is not used (probably required to use assembly language)\r
-\r
-**/\r
-ArmPlatformInitializeBootMemory\r
- // The SMC does not need to be initialized for RTSM\r
- bx lr\r
- \r
END\r
ArmRealViewEb.c\r
ArmRealViewEbHelper.asm | RVCT\r
ArmRealViewEbHelper.S | GCC\r
+ ArmRealViewEbBoot.asm | RVCT\r
+ ArmRealViewEbBoot.S | GCC\r
\r
[Protocols]\r
\r
ArmLib
ArmTrustZoneLib
MemoryAllocationLib
- PL354SmcLib
PL341DmcLib
PL301AxiLib
L2X0CacheLib
[Sources.common]
CTA9x4.c
CTA9x4Mem.c
+ CTA9x4Helper.asm | RVCT
+ CTA9x4Helper.S | GCC
[Protocols]
L2X0CacheLib\r
PL301AxiLib\r
PL341DmcLib\r
- PL354SmcLib\r
+ PL35xSmcLib\r
SerialPortLib\r
\r
[Sources.common]\r
CTA9x4.c\r
CTA9x4Helper.asm | RVCT\r
CTA9x4Helper.S | GCC\r
+ CTA9x4Boot.asm | RVCT\r
+ CTA9x4Boot.S | GCC\r
\r
[Protocols]\r
\r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Drivers/PL35xSmc.h>\r
+#include <ArmPlatform.h>\r
+#include <AutoGen.h>\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)\r
+GCC_ASM_IMPORT(PL35xSmcInitialize)\r
+\r
+//\r
+// For each Chip Select: ChipSelect / SetCycle / SetOpMode\r
+//\r
+VersatileExpressSmcConfiguration:\r
+ // NOR Flash 0\r
+ .word PL350_SMC_DIRECT_CMD_ADDR_CS(0)\r
+ .word PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)\r
+ .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV\r
+\r
+ // NOR Flash 1\r
+ .word PL350_SMC_DIRECT_CMD_ADDR_CS(4)\r
+ .word PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)\r
+ .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV\r
+\r
+ // SRAM\r
+ .word PL350_SMC_DIRECT_CMD_ADDR_CS(2)\r
+ .word PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)\r
+ .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_ADV\r
+\r
+ // Usb/Eth/VRAM\r
+ .word PL350_SMC_DIRECT_CMD_ADDR_CS(3)\r
+ .word PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6)\r
+ .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC\r
+\r
+ // Memory Mapped Peripherals\r
+ .word PL350_SMC_DIRECT_CMD_ADDR_CS(7)\r
+ .word PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)\r
+ .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC\r
+\r
+ // VRAM\r
+ .word PL350_SMC_DIRECT_CMD_ADDR_CS(1)\r
+ .word 0x00049249\r
+ .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC\r
+VersatileExpressSmcConfigurationEnd:\r
+\r
+/**\r
+ Initialize the memory where the initial stacks will reside\r
+\r
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
+ In some platform, this region is already initialized and the implementation of this function can\r
+ do nothing. This memory can also represent the Secure RAM.\r
+ This function is called before the satck has been set up. Its implementation must ensure the stack\r
+ pointer is not used (probably required to use assembly language)\r
+\r
+**/\r
+ASM_PFX(ArmPlatformInitializeBootMemory):\r
+ mov r5, lr\r
+\r
+ //\r
+ // Initialize PL354 SMC\r
+ //\r
+ LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)\r
+ ldr r2, =VersatileExpressSmcConfiguration\r
+ ldr r3, =VersatileExpressSmcConfigurationEnd\r
+ blx ASM_PFX(PL35xSmcInitialize)\r
+\r
+ //\r
+ // Page mode setup for VRAM\r
+ //\r
+ LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)\r
+\r
+ // Read current state\r
+ ldr r0, [r2, #0]\r
+ ldr r0, [r2, #0]\r
+ ldr r0, = 0x00000000\r
+ str r0, [r2, #0]\r
+ ldr r0, [r2, #0]\r
+\r
+ // Enable page mode\r
+ ldr r0, [r2, #0]\r
+ ldr r0, [r2, #0]\r
+ ldr r0, = 0x00000000\r
+ str r0, [r2, #0]\r
+ ldr r0, = 0x00900090\r
+ str r0, [r2, #0]\r
+\r
+ // Confirm page mode enabled\r
+ ldr r0, [r2, #0]\r
+ ldr r0, [r2, #0]\r
+ ldr r0, = 0x00000000\r
+ str r0, [r2, #0]\r
+ ldr r0, [r2, #0]\r
+\r
+ bx r5\r
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Base.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Drivers/PL35xSmc.h>\r
+#include <ArmPlatform.h>\r
+#include <AutoGen.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+\r
+ EXPORT ArmPlatformInitializeBootMemory\r
+ IMPORT PL35xSmcInitialize\r
+\r
+ PRESERVE8\r
+ AREA CTA9x4BootMode, CODE, READONLY\r
+\r
+//\r
+// For each Chip Select: ChipSelect / SetCycle / SetOpMode\r
+//\r
+VersatileExpressSmcConfiguration\r
+ // NOR Flash 0\r
+ DCD PL350_SMC_DIRECT_CMD_ADDR_CS(0)\r
+ DCD PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)\r
+ DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV\r
+\r
+ // NOR Flash 1\r
+ DCD PL350_SMC_DIRECT_CMD_ADDR_CS(4)\r
+ DCD PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)\r
+ DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV\r
+\r
+ // SRAM\r
+ DCD PL350_SMC_DIRECT_CMD_ADDR_CS(2)\r
+ DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)\r
+ DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_ADV\r
+\r
+ // Usb/Eth/VRAM\r
+ DCD PL350_SMC_DIRECT_CMD_ADDR_CS(3)\r
+ DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6)\r
+ DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC\r
+\r
+ // Memory Mapped Peripherals\r
+ DCD PL350_SMC_DIRECT_CMD_ADDR_CS(7)\r
+ DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)\r
+ DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC\r
+\r
+ // VRAM\r
+ DCD PL350_SMC_DIRECT_CMD_ADDR_CS(1)\r
+ DCD 0x00049249\r
+ DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC\r
+VersatileExpressSmcConfigurationEnd\r
+\r
+/**\r
+ Initialize the memory where the initial stacks will reside\r
+\r
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
+ In some platform, this region is already initialized and the implementation of this function can\r
+ do nothing. This memory can also represent the Secure RAM.\r
+ This function is called before the satck has been set up. Its implementation must ensure the stack\r
+ pointer is not used (probably required to use assembly language)\r
+\r
+**/\r
+ArmPlatformInitializeBootMemory\r
+ mov r5, lr\r
+\r
+ //\r
+ // Initialize PL354 SMC\r
+ //\r
+ LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)\r
+ ldr r2, =VersatileExpressSmcConfiguration\r
+ ldr r3, =VersatileExpressSmcConfigurationEnd\r
+ blx PL35xSmcInitialize\r
+\r
+ //\r
+ // Page mode setup for VRAM\r
+ //\r
+ LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)\r
+\r
+ // Read current state\r
+ ldr r0, [r2, #0]\r
+ ldr r0, [r2, #0]\r
+ ldr r0, = 0x00000000\r
+ str r0, [r2, #0]\r
+ ldr r0, [r2, #0]\r
+\r
+ // Enable page mode\r
+ ldr r0, [r2, #0]\r
+ ldr r0, [r2, #0]\r
+ ldr r0, = 0x00000000\r
+ str r0, [r2, #0]\r
+ ldr r0, = 0x00900090\r
+ str r0, [r2, #0]\r
+\r
+ // Confirm page mode enabled\r
+ ldr r0, [r2, #0]\r
+ ldr r0, [r2, #0]\r
+ ldr r0, = 0x00000000\r
+ str r0, [r2, #0]\r
+ ldr r0, [r2, #0]\r
+\r
+ bx r5\r
#include <Base.h>\r
#include <Library/PcdLib.h>\r
#include <Library/ArmPlatformLib.h>\r
-#include <Drivers/PL354Smc.h>\r
+#include <ArmPlatform.h>\r
#include <AutoGen.h>\r
\r
.text\r
.align 3\r
\r
GCC_ASM_EXPORT(ArmPlatformIsMemoryInitialized)\r
-GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)\r
-.extern ASM_PFX(SMCInitializeNOR)\r
-.extern ASM_PFX(SMCInitializeSRAM)\r
-.extern ASM_PFX(SMCInitializePeripherals)\r
-.extern ASM_PFX(SMCInitializeVRAM)\r
\r
/**\r
Called at the early stage of the Boot phase to know if the memory has already been initialized\r
tst r0, #0x40000000\r
bx lr\r
\r
-/**\r
- Initialize the memory where the initial stacks will reside\r
-\r
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
- In some platform, this region is already initialized and the implementation of this function can\r
- do nothing. This memory can also represent the Secure RAM.\r
- This function is called before the satck has been set up. Its implementation must ensure the stack\r
- pointer is not used (probably required to use assembly language)\r
-\r
-**/\r
-ASM_PFX(ArmPlatformInitializeBootMemory):\r
- mov r5, lr\r
-\r
- //\r
- // Initialize PL354 SMC\r
- //\r
- LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)\r
-\r
- // NOR Flash 0\r
- LoadConstantToReg (PL354_SMC_DIRECT_CMD_ADDR_CS(0,0), r2)\r
- blx ASM_PFX(SMCInitializeNOR)\r
-\r
- // NOR Flash 1\r
- LoadConstantToReg (PL354_SMC_DIRECT_CMD_ADDR_CS(1,0), r2)\r
- blx ASM_PFX(SMCInitializeNOR)\r
-\r
- // Setup SRAM\r
- blx ASM_PFX(SMCInitializeSRAM)\r
-\r
- // Memory Mapped Peripherals\r
- blx ASM_PFX(SMCInitializePeripherals)\r
-\r
- // Initialize VRAM\r
- //TODO: Check if we really must inititialize Video SRAM in UEFI. Does Linux can do it ? Does the Video driver can do it ?\r
- // It will be faster (only initialize if required) and easier (remove assembly code because of a stack available) to move this initialization.\r
- LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)\r
- blx ASM_PFX(SMCInitializeVRAM)\r
-\r
- bx r5\r
-\r
-.end\r
//\r
// Copyright (c) 2011, ARM Limited. All rights reserved.\r
-// \r
-// This program and the accompanying materials \r
-// are licensed and made available under the terms and conditions of the BSD License \r
-// which accompanies this distribution. The full text of the license may be found at \r
-// http://opensource.org/licenses/bsd-license.php \r
//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
//\r
\r
#include <AsmMacroIoLib.h>\r
#include <Base.h>\r
#include <Library/PcdLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
#include <ArmPlatform.h>\r
-#include <Drivers/PL354Smc.h>\r
#include <AutoGen.h>\r
\r
INCLUDE AsmMacroIoLib.inc\r
- \r
- EXPORT ArmPlatformIsMemoryInitialized\r
+\r
EXPORT ArmPlatformInitializeBootMemory\r
- IMPORT SMCInitializeNOR\r
- IMPORT SMCInitializeSRAM\r
- IMPORT SMCInitializePeripherals\r
- IMPORT SMCInitializeVRAM\r
- \r
+\r
PRESERVE8\r
AREA CTA9x4Helper, CODE, READONLY\r
\r
tst r0, #0x40000000\r
bx lr\r
\r
-/**\r
- Initialize the memory where the initial stacks will reside\r
-\r
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
- In some platform, this region is already initialized and the implementation of this function can\r
- do nothing. This memory can also represent the Secure RAM.\r
- This function is called before the satck has been set up. Its implementation must ensure the stack\r
- pointer is not used (probably required to use assembly language)\r
-\r
-**/\r
-ArmPlatformInitializeBootMemory\r
- mov r5, lr\r
-\r
- //\r
- // Initialize PL354 SMC\r
- //\r
- LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)\r
-\r
- // NOR Flash 0\r
- mov r2, PL354_SMC_DIRECT_CMD_ADDR_CS(0,0)\r
- blx SMCInitializeNOR\r
-\r
- // NOR Flash 1\r
- mov r2, PL354_SMC_DIRECT_CMD_ADDR_CS(1,0)\r
- blx SMCInitializeNOR\r
-\r
- // Setup SRAM\r
- blx SMCInitializeSRAM\r
-\r
- // Memory Mapped Peripherals\r
- blx SMCInitializePeripherals\r
-\r
- // Initialize VRAM\r
- //TODO: Check if we really must inititialize Video SRAM in UEFI. Does Linux can do it ? Does the Video driver can do it ?\r
- // It will be faster (only initialize if required) and easier (remove assembly code because of a stack available) to move this initialization.\r
- LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)\r
- blx SMCInitializeVRAM\r
-\r
- bx r5\r
-\r
- END\r
#Maintain 8 byte alignment\r
.align 3\r
\r
+GCC_ASM_EXPORT(PL35xSmcInitialize)\r
\r
-GCC_ASM_EXPORT(SMCInitializeNOR)\r
-GCC_ASM_EXPORT(SMCInitializeSRAM)\r
-GCC_ASM_EXPORT(SMCInitializePeripherals)\r
-GCC_ASM_EXPORT(SMCInitializeVRAM)\r
-\r
-\r
-# CS0 CS0-Interf0 NOR1 flash on the motherboard\r
-# CS1 CS1-Interf0 Reserved for the motherboard\r
-# CS2 CS2-Interf0 SRAM on the motherboard\r
-# CS3 CS3-Interf0 memory-mapped Ethernet and USB controllers on the motherboard\r
-# CS4 CS0-Interf1 NOR2 flash on the motherboard\r
-# CS5 CS1-Interf1 memory-mapped peripherals\r
-# CS6 CS2-Interf1 memory-mapped peripherals\r
-# CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.\r
-\r
-// IN r1 SmcBase\r
-// IN r2 ChipSelect\r
+// IN r1 Smc Base Address\r
+// IN r2 Smc Configuration Start Address\r
+// IN r3 Smc Configuration End Address\r
// NOTE: This code is been called before any stack has been setup. It means some registers\r
// could be overwritten (case of 'r0')\r
-ASM_PFX(SMCInitializeNOR):\r
-#\r
-# Setup NOR1 (CS0-Interface0)\r
-#\r
-\r
- # Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
- #Read cycle timeout = 0xA (0:3)\r
- #Write cycle timeout = 0x3(7:4)\r
- #OE Assertion Delay = 0x9(11:8)\r
- #WE Assertion delay = 0x3(15:12)\r
- #Page cycle timeout = 0x2(19:16) \r
- LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- # Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
- # 0x00000002 = MemoryWidth: 32bit\r
- # 0x00000028 = ReadMemoryBurstLength:continuous\r
- # 0x00000280 = WriteMemoryBurstLength:continuous\r
- # 0x00000800 = Set Address Valid\r
- LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
-\r
- # Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
- # 0x00000000 = ChipSelect0-Interface 0\r
- # 0x00400000 = CmdTypes: UpdateRegs\r
- LoadConstantToReg (0x00400000,r0) @ldr r0, = 0x00400000\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
- \r
- bx lr\r
-\r
-ASM_PFX(SMCInitializeSRAM):\r
-#\r
-# Setup SRAM (CS2-Interface0)\r
-#\r
- LoadConstantToReg (0x00027158,r0) @ldr r0, = 0x00027158\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
-\r
- # 0x00000002 = MemoryWidth: 32bit\r
- # 0x00000800 = Set Address Valid\r
- LoadConstantToReg (0x00000802,r0) @ldr r0, = 0x00000802\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- # 0x01000000 = ChipSelect2-Interface 0\r
- # 0x00400000 = CmdTypes: UpdateRegs\r
- LoadConstantToReg (0x01400000,r0) @ldr r0, = 0x01400000\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
-\r
- bx lr\r
+ASM_PFX(PL35xSmcInitialize):\r
+ // While (SmcConfigurationStart < SmcConfigurationEnd)\r
+ cmp r2, r3\r
+ blxge lr\r
\r
-ASM_PFX(SMCInitializePeripherals):\r
-#\r
-# USB/Eth/VRAM (CS3-Interface0)\r
-#\r
- LoadConstantToReg (0x000CD2AA,r0) @ldr r0, = 0x000CD2AA\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- # 0x00000002 = MemoryWidth: 32bit\r
- # 0x00000004 = Memory reads are synchronous\r
- # 0x00000040 = Memory writes are synchronous\r
- LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- # 0x01800000 = ChipSelect3-Interface 0\r
- # 0x00400000 = CmdTypes: UpdateRegs\r
- LoadConstantToReg (0x01C00000,r0) @ldr r0, = 0x01C00000\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
+ // Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
+ ldr r0, [r2, #0x4]\r
+ str r0, [r1, #PL350_SMC_SET_CYCLES_OFFSET]\r
\r
-#\r
-# Setup NOR3 (CS0-Interface1)\r
-#\r
- LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- # 0x00000002 = MemoryWidth: 32bit\r
- # 0x00000028 = ReadMemoryBurstLength:continuous\r
- # 0x00000280 = WriteMemoryBurstLength:continuous\r
- # 0x00000800 = Set Address Valid\r
- LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- # 0x02000000 = ChipSelect0-Interface 1\r
- # 0x00400000 = CmdTypes: UpdateRegs\r
- LoadConstantToReg (0x02400000,r0) @ldr r0, = 0x02400000\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
- \r
-#\r
-# Setup Peripherals (CS3-Interface1)\r
-#\r
- LoadConstantToReg (0x00025156,r0) @ldr r0, = 0x00025156\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- # 0x00000002 = MemoryWidth: 32bit\r
- # 0x00000004 = Memory reads are synchronous\r
- # 0x00000040 = Memory writes are synchronous\r
- LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- # 0x03800000 = ChipSelect3-Interface 1\r
- # 0x00400000 = CmdTypes: UpdateRegs\r
- LoadConstantToReg (0x03C00000,r0) @ldr r0, = 0x03C00000\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
- bx lr\r
+ // Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
+ ldr r0, [r2, #0x8]\r
+ str r0, [r1, #PL350_SMC_SET_OPMODE_OFFSET]\r
\r
-// IN r1 SmcBase\r
-// IN r2 VideoSRamBase\r
-// NOTE: This code is been called before any stack has been setup. It means some registers\r
-// could be overwritten (case of 'r0')\r
-ASM_PFX(SMCInitializeVRAM):\r
-#\r
-# Setup VRAM (CS1-Interface0)\r
-#\r
- LoadConstantToReg (0x00049249,r0) @ldr r0, = 0x00049249\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- # 0x00000002 = MemoryWidth: 32bit\r
- # 0x00000004 = Memory reads are synchronous\r
- # 0x00000040 = Memory writes are synchronous\r
- LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- # 0x00800000 = ChipSelect1-Interface 0\r
- # 0x00400000 = CmdTypes: UpdateRegs\r
- LoadConstantToReg (0x00C00000,r0) @ldr r0, = 0x00C00000\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
- \r
-#\r
-# Page mode setup for VRAM\r
-#\r
- #read current state \r
- ldr r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
- str r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
+ // Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
+ ldr r0, =PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE\r
+ ldr r4, [r2, #0x0]\r
+ orr r0, r0, r4\r
+ str r0, [r1, #PL350_SMC_DIRECT_CMD_OFFSET]\r
\r
- #enable page mode \r
- ldr r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
- str r0, [r2, #0] \r
- LoadConstantToReg (0x00900090,r0) @ldr r0, = 0x00900090\r
- str r0, [r2, #0] \r
+ add r2, #0xC\r
+ b ASM_PFX(PL350SmcInitialize)\r
\r
- #confirm page mode enabled\r
- ldr r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
- str r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- \r
- bx lr\r
- \r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
\ No newline at end of file
\r
INCLUDE AsmMacroIoLib.inc\r
\r
- EXPORT SMCInitializeNOR\r
- EXPORT SMCInitializeSRAM\r
- EXPORT SMCInitializePeripherals\r
- EXPORT SMCInitializeVRAM\r
+ EXPORT PL35xSmcInitialize\r
\r
PRESERVE8\r
AREA ModuleInitializeSMC, CODE, READONLY\r
\r
-// CS0 CS0-Interf0 NOR1 flash on the motherboard\r
-// CS1 CS1-Interf0 Reserved for the motherboard\r
-// CS2 CS2-Interf0 SRAM on the motherboard\r
-// CS3 CS3-Interf0 memory-mapped Ethernet and USB controllers on the motherboard\r
-// CS4 CS0-Interf1 NOR2 flash on the motherboard\r
-// CS5 CS1-Interf1 memory-mapped peripherals\r
-// CS6 CS2-Interf1 memory-mapped peripherals\r
-// CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.\r
-\r
-// IN r1 SmcBase\r
-// IN r2 ChipSelect\r
+// IN r1 Smc Base Address\r
+// IN r2 Smc Configuration Start Address\r
+// IN r3 Smc Configuration End Address\r
// NOTE: This code is been called before any stack has been setup. It means some registers\r
// could be overwritten (case of 'r0')\r
-SMCInitializeNOR\r
+PL35xSmcInitialize\r
+ // While (SmcConfigurationStart < SmcConfigurationEnd)\r
+ cmp r2, r3\r
+ blxge lr\r
+\r
// Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
- // - Read cycle timeout = 0xA (0:3)\r
- // - Write cycle timeout = 0x3(7:4)\r
- // - OE Assertion Delay = 0x9(11:8)\r
- // - WE Assertion delay = 0x3(15:12)\r
- // - Page cycle timeout = 0x2(19:16)\r
- ldr r0, = 0x0002393A\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
+ ldr r0, [r2, #0x4]\r
+ str r0, [r1, #PL350_SMC_SET_CYCLES_OFFSET]\r
+\r
// Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
- ldr r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_ADV)\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
+ ldr r0, [r2, #0x8]\r
+ str r0, [r1, #PL350_SMC_SET_OPMODE_OFFSET]\r
\r
// Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
- ldr r0, =PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE\r
- orr r0, r0, r2\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
- \r
- bx lr\r
-\r
-\r
-//\r
-// Setup SRAM (CS2-Interface0)\r
-//\r
-SMCInitializeSRAM\r
- ldr r0, = 0x00027158\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
-\r
- ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_ADV)\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,2))\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
-\r
- bx lr\r
-\r
-SMCInitializePeripherals\r
-//\r
-// USB/Eth/VRAM (CS3-Interface0)\r
-//\r
- ldr r0, = 0x000CD2AA\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,3))\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
-\r
-\r
-//\r
-// Setup Peripherals (CS3-Interface1)\r
-//\r
- ldr r0, = 0x00025156\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(1,3))\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
-\r
- bx lr\r
-\r
+ ldr r0, =PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE\r
+ ldr r4, [r2, #0x0]\r
+ orr r0, r0, r4\r
+ str r0, [r1, #PL350_SMC_DIRECT_CMD_OFFSET]\r
\r
-// IN r1 SmcBase\r
-// IN r2 VideoSRamBase\r
-// NOTE: This code is been called before any stack has been setup. It means some registers\r
-// could be overwritten (case of 'r0')\r
-SMCInitializeVRAM\r
- //\r
- // Setup VRAM (CS1-Interface0)\r
- //\r
- ldr r0, = 0x00049249\r
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
- \r
- ldr r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
- \r
- ldr r0, = (PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,1))\r
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
- \r
- //\r
- // Page mode setup for VRAM\r
- //\r
-\r
- // Read current state\r
- ldr r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- ldr r0, = 0x00000000\r
- str r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
+ add r2, #0xC\r
+ b PL35xSmcInitialize\r
\r
- // Enable page mode\r
- ldr r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- ldr r0, = 0x00000000\r
- str r0, [r2, #0] \r
- ldr r0, = 0x00900090\r
- str r0, [r2, #0] \r
-\r
- // Confirm page mode enabled\r
- ldr r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- ldr r0, = 0x00000000\r
- str r0, [r2, #0] \r
- ldr r0, [r2, #0] \r
- \r
- bx lr\r
- \r
- END\r
*\r
**/\r
\r
-#ifndef PL354SMC_H_\r
-#define PL354SMC_H_\r
+#ifndef PL35xSMC_H_\r
+#define PL35xSMC_H_\r
\r
-#define PL354_SMC_DIRECT_CMD_OFFSET 0x10\r
-#define PL354_SMC_SET_CYCLES_OFFSET 0x14\r
-#define PL354_SMC_SET_OPMODE_OFFSET 0x18\r
+#define PL350_SMC_DIRECT_CMD_OFFSET 0x10\r
+#define PL350_SMC_SET_CYCLES_OFFSET 0x14\r
+#define PL350_SMC_SET_OPMODE_OFFSET 0x18\r
\r
-#define PL354_SMC_DIRECT_CMD_ADDR(addr) ((addr) & 0xFFFFF)\r
-#define PL354_SMC_DIRECT_CMD_ADDR_SET_CRE (1 << 20)\r
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE (3 << 21)\r
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE (2 << 21)\r
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE (1 << 21)\r
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI (0 << 21)\r
-#define PL354_SMC_DIRECT_CMD_ADDR_CS(interf,chip) (((interf) << 25) | ((chip) << 23))\r
+#define PL350_SMC_DIRECT_CMD_ADDR(addr) ((addr) & 0xFFFFF)\r
+#define PL350_SMC_DIRECT_CMD_ADDR_SET_CRE (1 << 20)\r
+#define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE (3 << 21)\r
+#define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE (2 << 21)\r
+#define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE (1 << 21)\r
+#define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI (0 << 21)\r
+#define PL350_SMC_DIRECT_CMD_ADDR_CS_INTERF(interf,chip) (((interf) << 25) | ((chip) << 23))\r
+#define PL350_SMC_DIRECT_CMD_ADDR_CS(ChipSelect) (((ChipSelect) & 0x7) << 23)\r
\r
-#define PL354_SMC_SET_OPMODE_MEM_WIDTH_8 (0 << 0)\r
-#define PL354_SMC_SET_OPMODE_MEM_WIDTH_16 (1 << 0)\r
-#define PL354_SMC_SET_OPMODE_MEM_WIDTH_32 (2 << 0)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_SYNC (1 << 2)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1 (0 << 3)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4 (1 << 3)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8 (2 << 3)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16 (3 << 3)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32 (4 << 3)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT (5 << 3)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_SYNC (1 << 6)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1 (0 << 7)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4 (1 << 7)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8 (2 << 7)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16 (3 << 7)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32 (4 << 7)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT (5 << 7)\r
-#define PL354_SMC_SET_OPMODE_SET_BAA (1 << 10)\r
-#define PL354_SMC_SET_OPMODE_SET_ADV (1 << 11)\r
-#define PL354_SMC_SET_OPMODE_SET_BLS (1 << 12)\r
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY (0 << 13)\r
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_32 (1 << 13)\r
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_64 (2 << 13)\r
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_128 (3 << 13)\r
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_256 (4 << 13)\r
+#define PL350_SMC_SET_OPMODE_MEM_WIDTH_8 (0 << 0)\r
+#define PL350_SMC_SET_OPMODE_MEM_WIDTH_16 (1 << 0)\r
+#define PL350_SMC_SET_OPMODE_MEM_WIDTH_32 (2 << 0)\r
+#define PL350_SMC_SET_OPMODE_SET_RD_SYNC (1 << 2)\r
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1 (0 << 3)\r
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4 (1 << 3)\r
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8 (2 << 3)\r
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16 (3 << 3)\r
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32 (4 << 3)\r
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT (5 << 3)\r
+#define PL350_SMC_SET_OPMODE_SET_WR_SYNC (1 << 6)\r
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1 (0 << 7)\r
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4 (1 << 7)\r
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8 (2 << 7)\r
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16 (3 << 7)\r
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32 (4 << 7)\r
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT (5 << 7)\r
+#define PL350_SMC_SET_OPMODE_SET_BAA (1 << 10)\r
+#define PL350_SMC_SET_OPMODE_SET_ADV (1 << 11)\r
+#define PL350_SMC_SET_OPMODE_SET_BLS (1 << 12)\r
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY (0 << 13)\r
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_32 (1 << 13)\r
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_64 (2 << 13)\r
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_128 (3 << 13)\r
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_256 (4 << 13)\r
\r
+#define PL350_SMC_SET_CYCLE_NAND_T_RC(t) (((t) & 0xF) << 0)\r
+#define PL350_SMC_SET_CYCLE_NAND_T_WC(t) (((t) & 0xF) << 4)\r
+#define PL350_SMC_SET_CYCLE_NAND_T_REA(t) (((t) & 0x7) << 8)\r
+#define PL350_SMC_SET_CYCLE_NAND_T_WP(t) (((t) & 0x7) << 11)\r
+#define PL350_SMC_SET_CYCLE_NAND_T_CLR(t) (((t) & 0x7) << 14)\r
+#define PL350_SMC_SET_CYCLE_NAND_T_AR(t) (((t) & 0x7) << 17)\r
+#define PL350_SMC_SET_CYCLE_NAND_T_RR(t) (((t) & 0x7) << 20)\r
+\r
+#define PL350_SMC_SET_CYCLE_SRAM_T_RC(t) (((t) & 0xF) << 0)\r
+#define PL350_SMC_SET_CYCLE_SRAM_T_WC(t) (((t) & 0xF) << 4)\r
+#define PL350_SMC_SET_CYCLE_SRAM_T_CEOE(t) (((t) & 0x7) << 8)\r
+#define PL350_SMC_SET_CYCLE_SRAM_T_WP(t) (((t) & 0x7) << 11)\r
+#define PL350_SMC_SET_CYCLE_SRAM_T_PC(t) (((t) & 0x7) << 14)\r
+#define PL350_SMC_SET_CYCLE_SRAM_T_TR(t) (((t) & 0x7) << 17)\r
+#define PL350_SMC_SET_CYCLE_SRAM_WE_TIME (1 << 20)\r
\r
#endif\r
projects / mirror_edk2.git / commitdiff