+/** @file\r
+ MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
+ December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-6.\r
+\r
+**/\r
+\r
+#ifndef __XEON_5600_MSR_H__\r
+#define __XEON_5600_MSR_H__\r
+\r
+#include <Register/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
+ handler to handle unsuccessful read of this MSR.\r
+\r
+ @param ECX MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_5600_FEATURE_CONFIG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);\r
+ AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
+ /// MSR, the configuration of AES instruction set availability is as\r
+ /// follows: 11b: AES instructions are not available until next RESET.\r
+ /// otherwise, AES instructions are available. Note, AES instruction set\r
+ /// is not available if read is unsuccessful. If the configuration is not\r
+ /// 01b, AES instruction can be mis-configured if a privileged agent\r
+ /// unintentionally writes 11b.\r
+ ///\r
+ UINT32 AESConfiguration:2;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_5600_FEATURE_CONFIG_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Offcore Response Event Select Register (R/W).\r
+\r
+ @param ECX MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);\r
+ AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
+ /// limit of 1 core active.\r
+ ///\r
+ UINT32 Maximum1C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
+ /// limit of 2 core active.\r
+ ///\r
+ UINT32 Maximum2C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
+ /// limit of 3 core active.\r
+ ///\r
+ UINT32 Maximum3C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
+ /// limit of 4 core active.\r
+ ///\r
+ UINT32 Maximum4C:8;\r
+ ///\r
+ /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
+ /// limit of 5 core active.\r
+ ///\r
+ UINT32 Maximum5C:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
+ /// limit of 6 core active.\r
+ ///\r
+ UINT32 Maximum6C:8;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. See Table 35-2.\r
+\r
+ @param ECX MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);\r
+ AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0\r
+\r
+#endif\r