ArmPkg/ArmLib: move cache maintenance sync barriers out of loop

There is no need to issue a full data synchronization barrier and an
instruction synchronization barrier after each and every set/way or
MVA cache maintenance operation. For the set/way case, we can simply
remove them, since the set/way outer loop already issues the required
barriers after completing its traversal over all the cache levels.

For the MVA case, move the data synchronization barrier out of the
loop, and add the instruction synchronization barrier to the I-cache
invalidation by MVA routine.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18755 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
index d8e53df6096ee93d37239e0ab0214fdd6a88a40f..d4c16a60746575398f7fbe1357b4ff85f62d4708 100644 (file)
--- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
+++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
@@ -35,6 +35,7 @@ CacheRangeOperation (
     LineOperation(AlignedAddress);\r
     AlignedAddress += ArmCacheLineLength;\r
   }\r
+  ArmDataSynchronizationBarrier ();\r
 }\r
 \r
 VOID\r

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
index f973a35c21d6a67a72fb0ce2451005c1a06b7a4a..df2dc935c122327e43d6399fca2348125dd9d6a2 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -65,43 +65,31 @@ GCC_ASM_EXPORT (ArmReadCurrentEL)
 \r
 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
   dc      ivac, x0    // Invalidate single data cache line\r
-  dsb     sy\r
-  isb\r
   ret\r
 \r
 \r
 ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
   dc      cvac, x0    // Clean single data cache line\r
-  dsb     sy\r
-  isb\r
   ret\r
 \r
 \r
 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r
   dc      civac, x0   // Clean and invalidate single data cache line\r
-  dsb     sy\r
-  isb\r
   ret\r
 \r
 \r
 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):\r
   dc      isw, x0     // Invalidate this line\r
-  dsb     sy\r
-  isb\r
   ret\r
 \r
 \r
 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):\r
   dc      cisw, x0    // Clean and Invalidate this line\r
-  dsb     sy\r
-  isb\r
   ret\r
 \r
 \r
 ASM_PFX(ArmCleanDataCacheEntryBySetWay):\r
   dc      csw, x0     // Clean this line\r
-  dsb     sy\r
-  isb\r
   ret\r
 \r
 \r

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
index fdc4d03776c8af17f74532b4e1331d5fd59588dc..93164b8f0ea4370dd8458f18f7b1343caa5766d7 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
@@ -62,42 +62,30 @@ GCC_ASM_EXPORT (ArmReadIdPfr1)
 \r
 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r
   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):\r
   mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):\r
   mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
 ASM_PFX(ArmCleanDataCacheEntryBySetWay):\r
   mcr     p15, 0, r0, c7, c10, 2       @ Clean this line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 ASM_PFX(ArmInvalidateInstructionCache):\r

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
index f16dd4a4ab01897e737747dafb4f0bffd222a163..d6f249038a053314079d1ab8f37b78f1a5a9cde3 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
@@ -62,42 +62,30 @@ CTRL_I_BIT      EQU     (1 << 12)
 \r
 ArmInvalidateDataCacheEntryByMVA\r
   mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 ArmCleanDataCacheEntryByMVA\r
   mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
 ArmCleanInvalidateDataCacheEntryByMVA\r
   mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
 ArmInvalidateDataCacheEntryBySetWay\r
   mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
 ArmCleanInvalidateDataCacheEntryBySetWay\r
   mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r
 ArmCleanDataCacheEntryBySetWay\r
   mcr     p15, 0, r0, c7, c10, 2       ; Clean this line\r
-  dsb\r
-  isb\r
   bx      lr\r
 \r
 \r