ArmPkg/ArmGicV3Dxe: configure all interrupts as non-secure Group-1

Reassign all interrupts to non-secure Group-1 if the GIC has its DS
(Disable Security) bit set. In this case, it is safe to assume that we
own the GIC, and that no other firmware has performed any configuration
yet, which means it is up to us to reconfigure the interrupts so they
can be taken by the non-secure firmware.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
index 50fa56262eaf3393884665554c7196635240f367..106c669fcb8777dfaad609c0ce9f5b572727a3ff 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
+++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
@@ -297,6 +297,22 @@ GicV3DxeInitialize (
     MpId = ArmReadMpidr ();\r
     CpuTarget = MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);\r
 \r
+    if ((MmioRead32 (mGicDistributorBase + ARM_GIC_ICDDCR) & ARM_GIC_ICDDCR_DS) != 0) {\r
+      //\r
+      // If the Disable Security (DS) control bit is set, we are dealing with a\r
+      // GIC that has only one security state. In this case, let's assume we are\r
+      // executing in non-secure state (which is appropriate for DXE modules)\r
+      // and that no other firmware has performed any configuration on the GIC.\r
+      // This means we need to reconfigure all interrupts to non-secure Group 1\r
+      // first.\r
+      //\r
+      MmioWrite32 (mGicRedistributorsBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDISR, 0xffffffff);\r
+\r
+      for (Index = 32; Index < mGicNumInterrupts; Index += 32) {\r
+        MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDISR + Index / 8, 0xffffffff);\r
+      }\r
+    }\r
+\r
     // Route the SPIs to the primary CPU. SPIs start at the INTID 32\r
     for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {\r
       MmioWrite32 (mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), CpuTarget | ARM_GICD_IROUTER_IRM);\r

diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h
index 10c4a9d72eb2f3d8612899851fbf34faf410d999..4364f3ffef464596f64cf59881d703cf54cf0ddd 100644 (file)
--- a/ArmPkg/Include/Library/ArmGicLib.h
+++ b/ArmPkg/Include/Library/ArmGicLib.h
@@ -47,8 +47,9 @@
 // GICv3 specific registers\r
 #define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers\r
 \r
-// the Affinity Routing Enable (ARE) bit in GICD_CTLR\r
-#define ARM_GIC_ICDDCR_ARE      (1 << 4)\r
+// GICD_CTLR bits\r
+#define ARM_GIC_ICDDCR_ARE      (1 << 4) // Affinity Routing Enable (ARE)\r
+#define ARM_GIC_ICDDCR_DS       (1 << 6) // Disable Security (DS)\r
 \r
 //\r
 // GIC Redistributor\r