--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006 - 2007, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+\r
+ DataHubGen.c\r
+\r
+Abstract:\r
+\r
+--*/\r
+\r
+#include "DataHubGen.h"\r
+\r
+EFI_HII_PROTOCOL *gHii;\r
+extern UINT8 DataHubGenDxeStrings[];\r
+\r
+EFI_DATA_HUB_PROTOCOL *gDataHub;\r
+EFI_HII_HANDLE gStringHandle;\r
+\r
+VOID *\r
+GetSmbiosTablesFromHob (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_HOB_HANDOFF_INFO_TABLE *HobList;\r
+ EFI_PHYSICAL_ADDRESS *Table;\r
+\r
+ //\r
+ // Get Hob List\r
+ //\r
+ \r
+ Status = EfiGetSystemConfigurationTable (&gEfiHobListGuid, (VOID *) &HobList);\r
+ if (EFI_ERROR (Status)) {\r
+ return NULL;\r
+ }\r
+\r
+ //\r
+ // If there is a SMBIOS table in the HOB add it to the EFI System table\r
+ //\r
+ Table = GetNextGuidHob (&gEfiSmbiosTableGuid, &HobList);\r
+\r
+ if (!EFI_ERROR (Status)) {\r
+ return (VOID *)(UINTN)*Table;\r
+ }\r
+\r
+ return NULL;\r
+}\r
+\r
+EFI_STATUS\r
+PrepareHiiPackage (\r
+ VOID\r
+ )\r
+{\r
+ EFI_HII_PACKAGES *PackageList;\r
+ EFI_STATUS Status;\r
+\r
+ PackageList = PreparePackages (1, &gEfiMiscProducerGuid, DataHubGenDxeStrings);\r
+ Status = gHii->NewPack (gHii, PackageList, &gStringHandle);\r
+\r
+ return Status;\r
+}\r
+\r
+EFI_SUBCLASS_TYPE1_HEADER mCpuDataRecordHeader = {\r
+ EFI_PROCESSOR_SUBCLASS_VERSION, // Version\r
+ sizeof (EFI_SUBCLASS_TYPE1_HEADER), // Header Size\r
+ 0, // Instance, Initialize later\r
+ EFI_SUBCLASS_INSTANCE_NON_APPLICABLE, // SubInstance\r
+ 0 // RecordType, Initialize later\r
+};\r
+\r
+VOID\r
+InstallProcessorDataHub (\r
+ IN VOID *Smbios\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ SMBIOS_STRUCTURE_POINTER SmbiosTable;\r
+ EFI_CPU_DATA_RECORD DataRecord;\r
+ CHAR8 *AString;\r
+ CHAR16 *UString;\r
+ STRING_REF Token;\r
+\r
+ //\r
+ // Processor info (TYPE 4)\r
+ // \r
+ SmbiosTable = GetSmbiosTableFromType ((SMBIOS_TABLE_ENTRY_POINT *)Smbios, 4, 0);\r
+ if (SmbiosTable.Raw == NULL) {\r
+ DEBUG ((EFI_D_ERROR, "SmbiosTable: Type 4 (Processor Info) not found!\n"));\r
+ return ;\r
+ }\r
+\r
+ //\r
+ // Record Header\r
+ //\r
+ CopyMem (&DataRecord, &mCpuDataRecordHeader, sizeof (DataRecord.DataRecordHeader));\r
+\r
+ //\r
+ // Record Type 1\r
+ //\r
+ DataRecord.DataRecordHeader.RecordType = ProcessorCoreFrequencyRecordType;\r
+ DataRecord.VariableRecord.ProcessorCoreFrequency.Value = SmbiosTable.Type4->CurrentSpeed;\r
+ DataRecord.VariableRecord.ProcessorCoreFrequency.Exponent = 6;\r
+\r
+ Status = gDataHub->LogData (\r
+ gDataHub,\r
+ &gEfiProcessorSubClassGuid,\r
+ &gEfiMiscProducerGuid,\r
+ EFI_DATA_RECORD_CLASS_DATA,\r
+ &DataRecord,\r
+ sizeof (DataRecord.DataRecordHeader) + sizeof (DataRecord.VariableRecord.ProcessorCoreFrequency)\r
+ );\r
+ //\r
+ // Record Type 3\r
+ //\r
+ AString = GetSmbiosString (SmbiosTable, SmbiosTable.Type4->ProcessorVersion);\r
+ UString = AllocateZeroPool ((AsciiStrLen(AString) + 1) * sizeof(CHAR16));\r
+ ASSERT (UString != NULL);\r
+ AsciiStrToUnicodeStr (AString, UString);\r
+\r
+ Token = 0;\r
+ Status = gHii->NewString (gHii, NULL, gStringHandle, &Token, UString);\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ gBS->FreePool (UString);\r
+ return ;\r
+ }\r
+ gBS->FreePool (UString);\r
+\r
+ DataRecord.DataRecordHeader.RecordType = ProcessorVersionRecordType;\r
+ DataRecord.VariableRecord.ProcessorVersion = Token;\r
+\r
+ Status = gDataHub->LogData (\r
+ gDataHub,\r
+ &gEfiProcessorSubClassGuid,\r
+ &gEfiMiscProducerGuid,\r
+ EFI_DATA_RECORD_CLASS_DATA,\r
+ &DataRecord,\r
+ sizeof (DataRecord.DataRecordHeader) + sizeof (DataRecord.VariableRecord.ProcessorVersion)\r
+ );\r
+\r
+ return ;\r
+}\r
+\r
+VOID\r
+InstallCacheDataHub (\r
+ IN VOID *Smbios\r
+ )\r
+{\r
+ return ;\r
+}\r
+\r
+EFI_SUBCLASS_TYPE1_HEADER mMemorySubclassDriverDataHeader = {\r
+ EFI_MEMORY_SUBCLASS_VERSION, // Version\r
+ sizeof (EFI_SUBCLASS_TYPE1_HEADER), // Header Size\r
+ 0, // Instance, Initialize later\r
+ EFI_SUBCLASS_INSTANCE_NON_APPLICABLE, // SubInstance\r
+ 0 // RecordType, Initialize later\r
+};\r
+\r
+VOID\r
+InstallMemoryDataHub (\r
+ IN VOID *Smbios\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ SMBIOS_STRUCTURE_POINTER SmbiosTable;\r
+ EFI_MEMORY_SUBCLASS_DRIVER_DATA DataRecord;\r
+\r
+ //\r
+ // Generate Memory Array Mapped Address info (TYPE 19)\r
+ //\r
+ SmbiosTable = GetSmbiosTableFromType ((SMBIOS_TABLE_ENTRY_POINT *)Smbios, 19, 0);\r
+ if (SmbiosTable.Raw == NULL) {\r
+ DEBUG ((EFI_D_ERROR, "SmbiosTable: Type 19 (Memory Array Mapped Address Info) not found!\n"));\r
+ return ;\r
+ }\r
+\r
+ //\r
+ // Record Header\r
+ //\r
+ CopyMem (&DataRecord, &mMemorySubclassDriverDataHeader, sizeof (DataRecord.Header));\r
+ \r
+ //\r
+ // Record Type 4\r
+ //\r
+ DataRecord.Header.RecordType = EFI_MEMORY_ARRAY_START_ADDRESS_RECORD_NUMBER;\r
+ DataRecord.Record.ArrayStartAddress.MemoryArrayStartAddress = LShiftU64(SmbiosTable.Type19->StartingAddress, 10);\r
+ DataRecord.Record.ArrayStartAddress.MemoryArrayEndAddress = LShiftU64((UINT64) SmbiosTable.Type19->EndingAddress + 1, 10) - 1;\r
+ \r
+ DataRecord.Record.ArrayStartAddress.PhysicalMemoryArrayLink.ProducerName = gEfiMemoryProducerGuid;\r
+ DataRecord.Record.ArrayStartAddress.PhysicalMemoryArrayLink.Instance = 0;\r
+ DataRecord.Record.ArrayStartAddress.PhysicalMemoryArrayLink.SubInstance = EFI_SUBCLASS_INSTANCE_NON_APPLICABLE;\r
+ DataRecord.Record.ArrayStartAddress.MemoryArrayPartitionWidth = (UINT16)(SmbiosTable.Type19->PartitionWidth); \r
+\r
+ Status = gDataHub->LogData (\r
+ gDataHub,\r
+ &gEfiMemorySubClassGuid,\r
+ &gEfiMiscProducerGuid,\r
+ EFI_DATA_RECORD_CLASS_DATA,\r
+ &DataRecord,\r
+ sizeof (DataRecord.Header) + sizeof (DataRecord.Record.ArrayStartAddress)\r
+ );\r
+\r
+ return ;\r
+}\r
+\r
+EFI_SUBCLASS_TYPE1_HEADER mMiscSubclassDriverDataHeader = {\r
+ EFI_MISC_SUBCLASS_VERSION, // Version\r
+ sizeof (EFI_SUBCLASS_TYPE1_HEADER), // Header Size\r
+ 0, // Instance, Initialize later\r
+ EFI_SUBCLASS_INSTANCE_NON_APPLICABLE, // SubInstance\r
+ 0 // RecordType, Initialize later\r
+};\r
+\r
+VOID\r
+InstallMiscDataHub (\r
+ IN VOID *Smbios\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ SMBIOS_STRUCTURE_POINTER SmbiosTable;\r
+ EFI_MISC_SUBCLASS_DRIVER_DATA DataRecord;\r
+ CHAR8 *AString;\r
+ CHAR16 *UString;\r
+ STRING_REF Token;\r
+\r
+ //\r
+ // BIOS information (TYPE 0)\r
+ // \r
+ SmbiosTable = GetSmbiosTableFromType ((SMBIOS_TABLE_ENTRY_POINT *)Smbios, 0, 0);\r
+ if (SmbiosTable.Raw == NULL) {\r
+ DEBUG ((EFI_D_ERROR, "SmbiosTable: Type 0 (BIOS Information) not found!\n"));\r
+ return ;\r
+ }\r
+\r
+ //\r
+ // Record Header\r
+ //\r
+ CopyMem (&DataRecord, &mMiscSubclassDriverDataHeader, sizeof (DataRecord.Header));\r
+\r
+ //\r
+ // Record Type 2\r
+ //\r
+ AString = GetSmbiosString (SmbiosTable, SmbiosTable.Type0->BiosVersion);\r
+ UString = AllocateZeroPool ((AsciiStrLen(AString) + 1) * sizeof(CHAR16) + sizeof(FIRMWARE_BIOS_VERSIONE));\r
+ ASSERT (UString != NULL);\r
+ CopyMem (UString, FIRMWARE_BIOS_VERSIONE, sizeof(FIRMWARE_BIOS_VERSIONE));\r
+ AsciiStrToUnicodeStr (AString, UString + sizeof(FIRMWARE_BIOS_VERSIONE) / sizeof(CHAR16) - 1);\r
+\r
+ Token = 0;\r
+ Status = gHii->NewString (gHii, NULL, gStringHandle, &Token, UString);\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ gBS->FreePool (UString);\r
+ return ;\r
+ }\r
+ gBS->FreePool (UString);\r
+\r
+ DataRecord.Header.RecordType = EFI_MISC_BIOS_VENDOR_RECORD_NUMBER;\r
+ DataRecord.Record.MiscBiosVendor.BiosVendor = 0;\r
+ DataRecord.Record.MiscBiosVendor.BiosVersion = Token;\r
+ DataRecord.Record.MiscBiosVendor.BiosReleaseDate = 0;\r
+ DataRecord.Record.MiscBiosVendor.BiosStartingAddress = 0;\r
+ DataRecord.Record.MiscBiosVendor.BiosPhysicalDeviceSize.Value = 0;\r
+ DataRecord.Record.MiscBiosVendor.BiosPhysicalDeviceSize.Exponent = 0;\r
+// DataRecord.Record.MiscBiosVendor.BiosCharacteristics1 = {0};\r
+// DataRecord.Record.MiscBiosVendor.BiosCharacteristics2 = {0};\r
+ DataRecord.Record.MiscBiosVendor.BiosMajorRelease = 0;\r
+ DataRecord.Record.MiscBiosVendor.BiosMinorRelease = 0;\r
+ DataRecord.Record.MiscBiosVendor.BiosEmbeddedFirmwareMajorRelease = 0;\r
+ DataRecord.Record.MiscBiosVendor.BiosEmbeddedFirmwareMinorRelease = 0;\r
+\r
+ Status = gDataHub->LogData (\r
+ gDataHub,\r
+ &gEfiMiscSubClassGuid,\r
+ &gEfiMiscProducerGuid,\r
+ EFI_DATA_RECORD_CLASS_DATA,\r
+ &DataRecord,\r
+ sizeof (DataRecord.Header) + sizeof (DataRecord.Record.MiscBiosVendor)\r
+ );\r
+\r
+ //\r
+ // System information (TYPE 1)\r
+ // \r
+ SmbiosTable = GetSmbiosTableFromType ((SMBIOS_TABLE_ENTRY_POINT *)Smbios, 1, 0);\r
+ if (SmbiosTable.Raw == NULL) {\r
+ DEBUG ((EFI_D_ERROR, "SmbiosTable: Type 1 (System Information) not found!\n"));\r
+ return ;\r
+ }\r
+\r
+ //\r
+ // Record Type 3\r
+ //\r
+ AString = GetSmbiosString (SmbiosTable, SmbiosTable.Type1->ProductName);\r
+ UString = AllocateZeroPool ((AsciiStrLen(AString) + 1) * sizeof(CHAR16) + sizeof(FIRMWARE_PRODUCT_NAME));\r
+ ASSERT (UString != NULL);\r
+ CopyMem (UString, FIRMWARE_PRODUCT_NAME, sizeof(FIRMWARE_PRODUCT_NAME));\r
+ AsciiStrToUnicodeStr (AString, UString + sizeof(FIRMWARE_PRODUCT_NAME) / sizeof(CHAR16) - 1);\r
+\r
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)\r
+ Status = IfrLibNewString (gStringHandle, &Token, UString);\r
+#else\r
+ Token = 0;\r
+ Status = gHii->NewString (gHii, NULL, gStringHandle, &Token, UString);\r
+#endif\r
+ if (EFI_ERROR (Status)) {\r
+ gBS->FreePool (UString);\r
+ return ;\r
+ }\r
+ gBS->FreePool (UString);\r
+\r
+ DataRecord.Header.RecordType = EFI_MISC_SYSTEM_MANUFACTURER_RECORD_NUMBER;\r
+ DataRecord.Record.MiscSystemManufacturer.SystemManufacturer = 0;\r
+ DataRecord.Record.MiscSystemManufacturer.SystemProductName = Token;\r
+ DataRecord.Record.MiscSystemManufacturer.SystemVersion = 0;\r
+ DataRecord.Record.MiscSystemManufacturer.SystemSerialNumber = 0;\r
+// DataRecord.Record.MiscSystemManufacturer.SystemUuid = {0};\r
+ DataRecord.Record.MiscSystemManufacturer.SystemWakeupType = 0;\r
+ DataRecord.Record.MiscSystemManufacturer.SystemSKUNumber = 0;\r
+ DataRecord.Record.MiscSystemManufacturer.SystemFamily = 0;\r
+\r
+ Status = gDataHub->LogData (\r
+ gDataHub,\r
+ &gEfiMiscSubClassGuid,\r
+ &gEfiMiscProducerGuid,\r
+ EFI_DATA_RECORD_CLASS_DATA,\r
+ &DataRecord,\r
+ sizeof (DataRecord.Header) + sizeof (DataRecord.Record.MiscSystemManufacturer)\r
+ );\r
+\r
+ return ;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+DataHubGenEntrypoint (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ VOID *Smbios;\r
+\r
+\r
+ Smbios = GetSmbiosTablesFromHob ();\r
+ if (Smbios == NULL) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ Status = gBS->LocateProtocol (\r
+ &gEfiDataHubProtocolGuid,\r
+ NULL,\r
+ &gDataHub\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)\r
+ Status = gBS->LocateProtocol (\r
+ &gEfiHiiDatabaseProtocolGuid,\r
+ NULL,\r
+ &gHiiDatabase\r
+ );\r
+#else\r
+ Status = gBS->LocateProtocol (\r
+ &gEfiHiiProtocolGuid,\r
+ NULL,\r
+ &gHii\r
+ );\r
+#endif\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ PrepareHiiPackage ();\r
+\r
+ InstallProcessorDataHub (Smbios);\r
+ InstallCacheDataHub (Smbios);\r
+ InstallMemoryDataHub (Smbios);\r
+ InstallMiscDataHub (Smbios);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+//\r
+// Internal function\r
+//\r
+\r
+UINTN\r
+SmbiosTableLength (\r
+ IN SMBIOS_STRUCTURE_POINTER SmbiosTable\r
+ )\r
+{\r
+ CHAR8 *AChar;\r
+ UINTN Length;\r
+\r
+ AChar = (CHAR8 *)(SmbiosTable.Raw + SmbiosTable.Hdr->Length);\r
+ while ((*AChar != 0) || (*(AChar + 1) != 0)) {\r
+ AChar ++;\r
+ }\r
+ Length = ((UINTN)AChar - (UINTN)SmbiosTable.Raw + 2);\r
+ \r
+ return Length;\r
+}\r
+\r
+SMBIOS_STRUCTURE_POINTER\r
+GetSmbiosTableFromType (\r
+ IN SMBIOS_TABLE_ENTRY_POINT *Smbios,\r
+ IN UINT8 Type,\r
+ IN UINTN Index\r
+ )\r
+{\r
+ SMBIOS_STRUCTURE_POINTER SmbiosTable;\r
+ UINTN SmbiosTypeIndex;\r
+ \r
+ SmbiosTypeIndex = 0;\r
+ SmbiosTable.Raw = (UINT8 *)(UINTN)Smbios->TableAddress;\r
+ if (SmbiosTable.Raw == NULL) {\r
+ return SmbiosTable;\r
+ }\r
+ while ((SmbiosTypeIndex != Index) || (SmbiosTable.Hdr->Type != Type)) {\r
+ if (SmbiosTable.Hdr->Type == 127) {\r
+ SmbiosTable.Raw = NULL;\r
+ return SmbiosTable;\r
+ }\r
+ if (SmbiosTable.Hdr->Type == Type) {\r
+ SmbiosTypeIndex ++;\r
+ }\r
+ SmbiosTable.Raw = (UINT8 *)(SmbiosTable.Raw + SmbiosTableLength (SmbiosTable));\r
+ }\r
+\r
+ return SmbiosTable;\r
+}\r
+\r
+CHAR8 *\r
+GetSmbiosString (\r
+ IN SMBIOS_STRUCTURE_POINTER SmbiosTable,\r
+ IN SMBIOS_TABLE_STRING String\r
+ )\r
+{\r
+ CHAR8 *AString;\r
+ UINT8 Index;\r
+\r
+ Index = 1;\r
+ AString = (CHAR8 *)(SmbiosTable.Raw + SmbiosTable.Hdr->Length);\r
+ while (Index != String) {\r
+ while (*AString != 0) {\r
+ AString ++;\r
+ }\r
+ AString ++;\r
+ if (*AString == 0) {\r
+ return AString;\r
+ }\r
+ Index ++;\r
+ }\r
+\r
+ return AString;\r
+}\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006 - 2007, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+\r
+ DataHub.dxs\r
+\r
+Abstract:\r
+\r
+ Dependency expression source file.\r
+ \r
+--*/ \r
+\r
+\r
+#include "EfiDepex.h"\r
+\r
+#include EFI_PROTOCOL_DEFINITION (DataHub)\r
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)\r
+#include EFI_PROTOCOL_DEFINITION (HiiDatabase)\r
+#else\r
+#include EFI_PROTOCOL_DEFINITION (Hii)\r
+#endif\r
+\r
+DEPENDENCY_START\r
+ EFI_DATA_HUB_PROTOCOL_GUID AND\r
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)\r
+ EFI_HII_DATABASE_PROTOCOL_GUID\r
+#else\r
+ EFI_HII_PROTOCOL_GUID\r
+#endif\r
+DEPENDENCY_END\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006 - 2007, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name: \r
+\r
+ DataHubGen.h\r
+\r
+Abstract:\r
+\r
+--*/\r
+\r
+#ifndef _DATA_HUB_GEN_H_\r
+#define _DATA_HUB_GEN_H_\r
+\r
+#include <FrameworkDxe.h>\r
+#include <IndustryStandard/Smbios.h>\r
+\r
+#include <Guid/HobList.h>\r
+#include <Guid/Smbios.h>\r
+#include <Guid/DataHubProducer.h>\r
+#include <Guid/DataHubRecords.h>\r
+\r
+#include <Protocol/Datahub.h>\r
+#include <Protocol/FrameworkHii.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/FrameworkHiiLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+\r
+#define PRODUCT_NAME L"DUET"\r
+#define PRODUCT_VERSION L"Beta"\r
+\r
+#define FIRMWARE_PRODUCT_NAME (PRODUCT_NAME L": ")\r
+#ifdef EFI32\r
+#if (EFI_SPECIFICATION_VERSION >= 0x00020000)\r
+#define FIRMWARE_BIOS_VERSIONE (PRODUCT_NAME L"(IA32.UEFI)" PRODUCT_VERSION L": ")\r
+#else\r
+#define FIRMWARE_BIOS_VERSIONE (PRODUCT_NAME L"(IA32.EFI)" PRODUCT_VERSION L": ")\r
+#endif\r
+#else // EFIX64\r
+#if (EFI_SPECIFICATION_VERSION >= 0x00020000)\r
+#define FIRMWARE_BIOS_VERSIONE (PRODUCT_NAME L"(X64.UEFI)" PRODUCT_VERSION L": ")\r
+#else\r
+#define FIRMWARE_BIOS_VERSIONE (PRODUCT_NAME L"(X64.EFI)" PRODUCT_VERSION L": ")\r
+#endif\r
+#endif\r
+\r
+SMBIOS_STRUCTURE_POINTER\r
+GetSmbiosTableFromType (\r
+ IN VOID *Smbios,\r
+ IN UINT8 Type,\r
+ IN UINTN Index\r
+ );\r
+\r
+CHAR8 *\r
+GetSmbiosString (\r
+ IN SMBIOS_STRUCTURE_POINTER SmbiosTable,\r
+ IN SMBIOS_TABLE_STRING String\r
+ );\r
+\r
+#endif\r
--- /dev/null
+#/*++\r
+#\r
+# Copyright (c) 2006 - 2007, Intel Corporation \r
+# All rights reserved. This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+# \r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+# \r
+# Module Name:\r
+#\r
+# DataHubGen.inf\r
+#\r
+# Abstract:\r
+#\r
+# Component description file for DataHubGen module.\r
+#\r
+--*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = DataHubGenDxe\r
+ FILE_GUID = 0021001C-3CE3-41f8-99C6-ECF5DA754731\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ EDK_RELEASE_VERSION = 0x00020000\r
+ EFI_SPECIFICATION_VERSION = 0x00020000\r
+ ENTRY_POINT = DataHubGenEntrypoint\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+\r
+[LibraryClasses]\r
+ UefiLib\r
+ HobLib\r
+ UefiBootServicesTableLib\r
+ BaseMemoryLib\r
+ MemoryAllocationLib\r
+ UefiDriverEntryPoint\r
+ BaseLib\r
+ FrameworkHiiLib\r
+ \r
+[Sources.common]\r
+ DataHubGen.c\r
+ DataHubGen.h\r
+ DataHubGenStrings.uni\r
+\r
+[Guids.common]\r
+ gEfiProcessorSubClassGuid\r
+ gEfiHiiProtocolGuid\r
+ gEfiMiscSubClassGuid\r
+ gEfiDataHubProtocolGuid\r
+ gEfiSmbiosTableGuid\r
+ gEfiMiscProducerGuid\r
+ gEfiMemorySubClassGuid\r
+ gEfiMemoryProducerGuid\r
+\r
+[Depex]\r
+ gEfiDataHubProtocolGuid AND gEfiHiiProtocolGuid
\ No newline at end of file
--- /dev/null
+[Defines]\r
+ DEC_SPECIFICATION = 0x00010005\r
+ PACKAGE_NAME = DuetPkg\r
+ PACKAGE_GUID = 151B568B-B390-4cf1-ABD6-228E0AB96F57\r
+ PACKAGE_VERSION = 0.1\r
+\r
+[Includes.common]\r
+ Include\r
+\r
+[Guids.common]\r
+ gEfiPciExpressBaseAddressGuid = {0x3677d529, 0x326f, 0x4603, {0xa9, 0x26, 0xea, 0xac, 0xe0, 0x1d, 0xcb, 0xb0 }}\r
+ gEfiAcpiDescriptionGuid = {0x3c699197, 0x093c, 0x4c69, {0xb0, 0x6b, 0x12, 0x8a, 0xe3, 0x48, 0x1d, 0xc9 }}
\ No newline at end of file
--- /dev/null
+\r
+\r
+[Defines]\r
+ PLATFORM_NAME = DuetPkg\r
+ PLATFORM_GUID = 199E24E0-0989-42aa-87F2-611A8C397E72\r
+ PLATFORM_VERSION = 0.3\r
+ DSC_SPECIFICATION = 0x00010005\r
+ OUTPUT_DIRECTORY = Build/DuetPkg\r
+ SUPPORTED_ARCHITECTURES = IA32|X64\r
+ BUILD_TARGETS = DEBUG\r
+ SKUID_IDENTIFIER = DEFAULT\r
+ #FLASH_DEFINITION = DuetPkg/DuetPkg.fdf\r
+\r
+[LibraryClasses.common]\r
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf\r
+ TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf\r
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf\r
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/BaseReportStatusCodeLib/BaseReportStatusCodeLib.inf\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
+ FrameworkHiiLib|IntelFrameworkPkg/Library/FrameworkHiiLib/HiiLib.inf\r
+\r
+[LibraryClasses.common.DXE_DRIVER]\r
+ MemoryAllocationLib|MdePkg/Library/DxeMemoryAllocationLib/DxeMemoryAllocationLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+\r
+[Components.IA32]\r
+ DuetPkg/DxeIpl/DxeIpl.inf\r
+ DuetPkg/DataHubGenDxe/DataHubGen.inf\r
+\r
+[Components.X64]\r
+ DuetPkg/DxeIpl/DxeIpl.inf\r
+ DuetPkg/DataHubGenDxe/DataHubGen.inf
\ No newline at end of file
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ Debug.c\r
+\r
+Abstract:\r
+\r
+Revision History:\r
+\r
+--*/\r
+\r
+#include "DxeIpl.h"\r
+\r
+UINT8 *mCursor;\r
+UINT8 mHeaderIndex = 10;\r
+\r
+\r
+VOID\r
+PrintHeader (\r
+ CHAR8 Char\r
+ )\r
+{\r
+ *(UINT8 *)(UINTN)(0x000b8000 + mHeaderIndex) = Char;\r
+ mHeaderIndex += 2;\r
+}\r
+\r
+VOID\r
+ClearScreen (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 Index;\r
+\r
+ mCursor = (UINT8 *)(UINTN)(0x000b8000 + 160);\r
+ for (Index = 0; Index < 80 * 49; Index++) {\r
+ *mCursor = ' ';\r
+ mCursor += 2;\r
+ }\r
+ mCursor = (UINT8 *)(UINTN)(0x000b8000 + 160);\r
+}\r
+\r
+VOID\r
+PrintValue (\r
+ UINT32 Value\r
+ )\r
+{\r
+ UINT32 Index;\r
+ UINT8 Char;\r
+\r
+ for (Index = 0; Index < 8; Index++) {\r
+ Char = (UINT8)((Value >> ((7 - Index) * 4)) & 0x0f) + '0';\r
+ if (Char > '9') {\r
+ Char = Char - '0' - 10 + 'A';\r
+ }\r
+ *mCursor = Char;\r
+ mCursor += 2;\r
+ }\r
+}\r
+\r
+VOID\r
+PrintValue64 (\r
+ UINT64 Value\r
+ )\r
+{\r
+ PrintValue ((UINT32) RShiftU64 (Value, 32));\r
+ PrintValue ((UINT32) Value);\r
+}\r
+\r
+\r
+\r
+VOID\r
+PrintString (\r
+ UINT8 *String\r
+ )\r
+{\r
+ UINT32 Index;\r
+\r
+ for (Index = 0; String[Index] != 0; Index++) {\r
+ if (String[Index] == '\n') {\r
+ mCursor = (UINT8 *)(UINTN)(0xb8000 + (((((UINTN)mCursor - 0xb8000) + 160) / 160) * 160));\r
+ } else {\r
+ *mCursor = String[Index];\r
+ mCursor += 2;\r
+ }\r
+ }\r
+}\r
+\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ Debug.h\r
+\r
+Abstract:\r
+\r
+Revision History:\r
+\r
+--*/\r
+\r
+#ifndef _EFILDR_DEBUG_H_\r
+#define _EFILDR_DEBUG_H_\r
+\r
+VOID\r
+PrintHeader (\r
+ CHAR8 Char\r
+ );\r
+\r
+VOID \r
+PrintValue (\r
+ UINT32 Value\r
+ );\r
+\r
+VOID\r
+PrintValue64 (\r
+ UINT64 Value\r
+ );\r
+\r
+VOID \r
+PrintString (\r
+ UINT8 *String\r
+ );\r
+\r
+VOID \r
+ClearScreen (\r
+ VOID\r
+ );\r
+\r
+#endif\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006 - 2007, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ DxeInit.c\r
+\r
+Abstract:\r
+\r
+Revision History:\r
+\r
+--*/\r
+\r
+#include "DxeIpl.h"\r
+\r
+#include "LegacyTable.h"\r
+#include "HobGeneration.h"\r
+#include "PpisNeededByDxeCore.h"\r
+#include "Debug.h"\r
+\r
+/*\r
+--------------------------------------------------------\r
+ Memory Map: (XX=32,64)\r
+--------------------------------------------------------\r
+0x0\r
+ IVT\r
+0x400\r
+ BDA\r
+0x500\r
+\r
+0x7C00\r
+ BootSector\r
+0x10000\r
+ EfiLdr (relocate by efiXX.COM)\r
+0x15000\r
+ Efivar.bin (Load by StartXX.COM)\r
+0x20000\r
+ StartXX.COM (E820 table, Temporary GDT, Temporary IDT)\r
+0x21000\r
+ EfiXX.COM (Temporary Interrupt Handler)\r
+0x22000\r
+ EfiLdr.efi + DxeIpl.Z + DxeMain.Z + BFV.Z\r
+0x86000\r
+ MemoryFreeUnder1M (For legacy driver DMA)\r
+0x90000\r
+ Temporary 4G PageTable for X64 (6 page)\r
+0x9F800\r
+ EBDA\r
+0xA0000\r
+ VGA\r
+0xC0000\r
+ OPROM\r
+0xE0000\r
+ FIRMEWARE\r
+0x100000 (1M)\r
+ Temporary Stack (1M)\r
+0x200000\r
+\r
+MemoryAbove1MB.PhysicalStart <-----------------------------------------------------+\r
+ ... |\r
+ ... |\r
+ <- Phit.EfiMemoryBottom -------------------+ |\r
+ HOB | |\r
+ <- Phit.EfiFreeMemoryBottom | |\r
+ | MemoryFreeAbove1MB.ResourceLength\r
+ <- Phit.EfiFreeMemoryTop ------+ | |\r
+ MemoryDescriptor (For ACPINVS, ACPIReclaim) | 4M = CONSUMED_MEMORY |\r
+ | | |\r
+ Permament 4G PageTable for IA32 or MemoryAllocation | |\r
+ Permament 64G PageTable for X64 | | |\r
+ <------------------------------+ | |\r
+ Permament Stack (0x20 Pages = 128K) | |\r
+ <- Phit.EfiMemoryTop ----------+-----------+---------------+\r
+ DxeCore |\r
+ DxeCore\r
+ DxeIpl |\r
+ <----------------------------------------------------------+\r
+ NvFV + FtwFV |\r
+ MMIO\r
+ BFV |\r
+ <- Top of Free Memory reported by E820 --------------------+\r
+ ACPINVS or\r
+ ACPIReclaim or\r
+ Reserved\r
+ <- Memory Top on RealMemory\r
+\r
+0x100000000 (4G)\r
+\r
+MemoryFreeAbove4G.Physicalstart <--------------------------------------------------+\r
+ |\r
+ |\r
+ MemoryFreeAbove4GB.ResourceLength\r
+ |\r
+ |\r
+ <--------------------------------------------------+\r
+*/\r
+\r
+VOID\r
+EnterDxeMain (\r
+ IN VOID *StackTop,\r
+ IN VOID *DxeCoreEntryPoint,\r
+ IN VOID *Hob,\r
+ IN VOID *PageTable\r
+ );\r
+\r
+VOID\r
+DxeInit (\r
+ IN EFILDRHANDOFF *Handoff\r
+ )\r
+/*++\r
+\r
+ Routine Description:\r
+\r
+ This is the entry point after this code has been loaded into memory. \r
+\r
+Arguments:\r
+\r
+\r
+Returns:\r
+\r
+ Calls into EFI Firmware\r
+\r
+--*/\r
+{\r
+ VOID *StackTop;\r
+ VOID *StackBottom;\r
+ VOID *PageTableBase;\r
+ VOID *MemoryTopOnDescriptor;\r
+ VOID *MemoryDescriptor;\r
+ VOID *NvStorageBase;\r
+\r
+/*\r
+ ClearScreen();\r
+ PrintString("handoff:\n");\r
+ PrintString("Handoff.BfvBase = "); \r
+ PrintValue64((UINT64)(UINTN)Handoff->BfvBase);\r
+ PrintString(", "); \r
+ PrintString("BfvLength = "); \r
+ PrintValue64(Handoff->BfvSize);\r
+ PrintString("\n"); \r
+ PrintString("Handoff.DxeIplImageBase = "); \r
+ PrintValue64((UINT64)(UINTN)Handoff->DxeIplImageBase);\r
+ PrintString(", "); \r
+ PrintString("DxeIplImageSize = "); \r
+ PrintValue64(Handoff->DxeIplImageSize);\r
+ PrintString("\n"); \r
+ PrintString("Handoff.DxeCoreImageBase = "); \r
+ PrintValue64((UINT64)(UINTN)Handoff->DxeCoreImageBase);\r
+ PrintString(", "); \r
+ PrintString("DxeCoreImageSize = "); \r
+ PrintValue64(Handoff->DxeCoreImageSize);\r
+ PrintString("\n"); \r
+*/\r
+ //\r
+ // Hob Generation Guild line:\r
+ // * Don't report FV as physical memory\r
+ // * MemoryAllocation Hob should only cover physical memory\r
+ // * Use ResourceDescriptor Hob to report physical memory or Firmware Device and they shouldn't be overlapped\r
+ \r
+ PrepareHobCpu ();\r
+ //\r
+ // 1. BFV\r
+ //\r
+ PrepareHobBfv (Handoff->BfvBase, Handoff->BfvSize);\r
+\r
+ //\r
+ // 2. Updates Memory information, and get the top free address under 4GB\r
+ //\r
+ MemoryTopOnDescriptor = PrepareHobMemory (Handoff->MemDescCount, Handoff->MemDesc);\r
+\r
+ //\r
+ // 3. Put [NV], [Stack], [PageTable], [MemDesc], [HOB] just below the [top free address under 4GB]\r
+ //\r
+ \r
+ // 3.1 NV data\r
+ NvStorageBase = PrepareHobNvStorage (MemoryTopOnDescriptor);\r
+ // 3.2 Stack\r
+ StackTop = NvStorageBase;\r
+ StackBottom = PrepareHobStack (StackTop);\r
+ // 3.3 Page Table\r
+ PageTableBase = PreparePageTable (StackBottom, gHob->Cpu.SizeOfMemorySpace);\r
+ // 3.4 MemDesc (will be used in PlatformBds)\r
+ MemoryDescriptor = PrepareHobMemoryDescriptor (PageTableBase, Handoff->MemDescCount, Handoff->MemDesc);\r
+ // 3.5 Copy the Hob itself to EfiMemoryBottom, and update the PHIT Hob\r
+ PrepareHobPhit (StackTop, MemoryDescriptor);\r
+\r
+ //\r
+ // 4. Register the memory occupied by DxeCore and DxeIpl together as DxeCore\r
+ //\r
+ PrepareHobDxeCore (\r
+ Handoff->DxeCoreEntryPoint,\r
+ (EFI_PHYSICAL_ADDRESS)(UINTN)Handoff->DxeCoreImageBase,\r
+ (UINTN)Handoff->DxeIplImageBase + (UINTN)Handoff->DxeIplImageSize - (UINTN)Handoff->DxeCoreImageBase\r
+ );\r
+\r
+ PrepareHobLegacyTable (gHob);\r
+ PreparePpisNeededByDxeCore (gHob);\r
+\r
+ CompleteHobGeneration ();\r
+\r
+/*\r
+ //\r
+ // Print Hob Info\r
+ //\r
+ ClearScreen();\r
+ PrintString("Hob Info\n");\r
+ PrintString("Phit.EfiMemoryTop = "); \r
+ PrintValue64(gHob->Phit.EfiMemoryTop);\r
+ PrintString(" Phit.EfiMemoryBottom = "); \r
+ PrintValue64(gHob->Phit.EfiMemoryBottom);\r
+ PrintString("\n"); \r
+ PrintString("Phit.EfiFreeMemoryTop = "); \r
+ PrintValue64(gHob->Phit.EfiFreeMemoryTop);\r
+ PrintString(" Phit.EfiFreeMemoryBottom = "); \r
+ PrintValue64(gHob->Phit.EfiFreeMemoryBottom);\r
+ PrintString("\n"); \r
+ PrintString("Bfv = "); \r
+ PrintValue64(gHob->Bfv.BaseAddress);\r
+ PrintString(" BfvLength = "); \r
+ PrintValue64(gHob->Bfv.Length);\r
+ PrintString("\n");\r
+ PrintString("NvStorageFvb = ");\r
+ PrintValue64(gHob->NvStorageFvb.FvbInfo.Entries[0].Base);\r
+ PrintString(" Length = ");\r
+ PrintValue64(gHob->NvStorageFvb.FvbInfo.Entries[0].Length);\r
+ PrintString("\n");\r
+ PrintString("NvFtwFvb = ");\r
+ PrintValue64(gHob->NvFtwFvb.FvbInfo.Entries[0].Base);\r
+ PrintString(" Length = ");\r
+ PrintValue64(gHob->NvFtwFvb.FvbInfo.Entries[0].Length);\r
+ PrintString("\n");\r
+ PrintString("Stack = "); \r
+ PrintValue64(gHob->Stack.AllocDescriptor.MemoryBaseAddress);\r
+ PrintString(" StackLength = "); \r
+ PrintValue64(gHob->Stack.AllocDescriptor.MemoryLength);\r
+ PrintString("\n"); \r
+ PrintString("MemoryFreeUnder1MB = "); \r
+ PrintValue64(gHob->MemoryFreeUnder1MB.PhysicalStart);\r
+ PrintString(" MemoryFreeUnder1MBLength = "); \r
+ PrintValue64(gHob->MemoryFreeUnder1MB.ResourceLength);\r
+ PrintString("\n"); \r
+ PrintString("MemoryAbove1MB = "); \r
+ PrintValue64(gHob->MemoryAbove1MB.PhysicalStart);\r
+ PrintString(" MemoryAbove1MBLength = "); \r
+ PrintValue64(gHob->MemoryAbove1MB.ResourceLength);\r
+ PrintString("\n"); \r
+ PrintString("MemoryAbove4GB = "); \r
+ PrintValue64(gHob->MemoryAbove4GB.PhysicalStart);\r
+ PrintString(" MemoryAbove4GBLength = "); \r
+ PrintValue64(gHob->MemoryAbove4GB.ResourceLength);\r
+ PrintString("\n"); \r
+ PrintString("DxeCore = "); \r
+ PrintValue64(gHob->DxeCore.MemoryAllocationHeader.MemoryBaseAddress);\r
+ PrintString(" DxeCoreLength = "); \r
+ PrintValue64(gHob->DxeCore.MemoryAllocationHeader.MemoryLength);\r
+ PrintString("\n"); \r
+ PrintString("MemoryAllocation = "); \r
+ PrintValue64(gHob->MemoryAllocation.AllocDescriptor.MemoryBaseAddress);\r
+ PrintString(" MemoryLength = "); \r
+ PrintValue64(gHob->MemoryAllocation.AllocDescriptor.MemoryLength);\r
+ PrintString("\n"); \r
+ EFI_DEADLOOP();\r
+*/\r
+\r
+ ClearScreen();\r
+ PrintString("\n\n\n\n\n\n\n\n\n\n");\r
+ PrintString(" WELCOME TO EFI WORLD!\n");\r
+\r
+ EnterDxeMain (StackTop, Handoff->DxeCoreEntryPoint, gHob, PageTableBase);\r
+\r
+ //\r
+ // Should never get here\r
+ //\r
+ CpuDeadLoop ();\r
+}\r
+\r
--- /dev/null
+\r
+#ifndef _DUET_DXEIPL_H_\r
+#define _DUET_DXEIPL_H_\r
+\r
+#include "FrameworkPei.h"\r
+#include "FrameworkModulePei.h"\r
+\r
+#include "EfiLdrHandoff.h"\r
+#include "EfiFlashMap.h"\r
+\r
+#include <Guid/MemoryTypeInformation.h>\r
+#include <Guid/PciExpressBaseAddress.h>\r
+#include <Guid/AcpiDescription.h>\r
+#include <Guid/PeiPeCoffLoader.h>\r
+#include <Guid/MemoryAllocationHob.h>\r
+#include <Guid/Acpi.h>\r
+#include <Guid/Smbios.h>\r
+#include <Guid/Mps.h>\r
+#include <Guid/FlashMapHob.h>\r
+#include <Guid/SystemNvDataGuid.h>\r
+\r
+#include <Protocol/Decompress.h>\r
+#include <Protocol/EdkDecompress.h>\r
+#include <Protocol/StatusCode.h>\r
+#include <Protocol/FirmwareVolumeBlock.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/ReportStatusCodeLib.h>\r
+#include <Library/PrintLib.h>\r
+\r
+#include <VariableFormat.h>\r
+#include <CpuIA32.h>\r
+\r
+#endif // _DUET_DXEIPL_H_
\ No newline at end of file
--- /dev/null
+#/*++\r
+# \r
+# Copyright (c) 2006 - 2007, Intel Corporation \r
+# All rights reserved. This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+# \r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+# Module Name:\r
+# DxeIpl.inf\r
+#\r
+# Abstract:\r
+#\r
+#--*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = DxeIpl\r
+ FILE_GUID = 2119BBD7-9432-4f47-B5E2-5C4EA31B6BDC\r
+ MODULE_TYPE = PEIM\r
+ VERSION_STRING = 1.0\r
+ EDK_RELEASE_VERSION = 0x00020000\r
+ EFI_SPECIFICATION_VERSION = 0x00020000\r
+ ENTRY_POINT = DxeInit\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ DuetPkg/DuetPkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+\r
+[LibraryClasses.common]\r
+ BaseLib\r
+ BaseMemoryLib\r
+ PrintLib\r
+ PeimEntryPoint\r
+ ReportStatusCodeLib\r
+\r
+[Sources.common]\r
+ DxeIpl.h\r
+ DxeInit.c\r
+ LegacyTable.c\r
+ LegacyTable.h\r
+ PpisNeededByDxeCore.c\r
+ PpisNeededByDxeCore.h\r
+ HobGeneration.c\r
+ HobGeneration.h\r
+ SerialStatusCode.c\r
+ SerialStatusCode.h\r
+ Debug.c\r
+ Debug.h\r
+ \r
+[Sources.x64]\r
+ X64\CpuIoAccess.asm\r
+ X64\EnterDxeCore.asm\r
+ X64\Paging.c\r
+ X64\VirtualMemory.h\r
+\r
+[Sources.Ia32]\r
+ Ia32\CpuIoAccess.asm\r
+ Ia32\EnterDxeCore.asm\r
+ Ia32\Paging.c\r
+ Ia32\VirtualMemory.h\r
+\r
+ \r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006 - 2007, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ HobGeneration.c\r
+\r
+Abstract:\r
+\r
+Revision History:\r
+\r
+--*/\r
+#include "DxeIpl.h"\r
+#include "HobGeneration.h"\r
+#include "PpisNeededByDxeCore.h"\r
+#include "FlashLayout.h"\r
+#include "Debug.h"\r
+\r
+#define EFI_DXE_FILE_GUID \\r
+ { 0xb1644c1a, 0xc16a, 0x4c5b, 0x88, 0xde, 0xea, 0xfb, 0xa9, 0x7e, 0x74, 0xd8 }\r
+\r
+#define CPUID_EXTENDED_ADD_SIZE 0x80000008\r
+\r
+HOB_TEMPLATE gHobTemplate = {\r
+ { // Phit\r
+ { // Header\r
+ EFI_HOB_TYPE_HANDOFF, // HobType\r
+ sizeof (EFI_HOB_HANDOFF_INFO_TABLE), // HobLength\r
+ 0 // Reserved\r
+ },\r
+ EFI_HOB_HANDOFF_TABLE_VERSION, // Version\r
+ BOOT_WITH_FULL_CONFIGURATION, // BootMode\r
+ 0, // EfiMemoryTop\r
+ 0, // EfiMemoryBottom\r
+ 0, // EfiFreeMemoryTop\r
+ 0, // EfiFreeMemoryBottom\r
+ 0 // EfiEndOfHobList\r
+ }, \r
+ { // Bfv\r
+ {\r
+ EFI_HOB_TYPE_FV, // HobType\r
+ sizeof (EFI_HOB_FIRMWARE_VOLUME), // HobLength\r
+ 0 // Reserved\r
+ },\r
+ 0, // BaseAddress\r
+ 0 // Length\r
+ },\r
+ { // BfvResource\r
+ {\r
+ EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, // HobType\r
+ sizeof (EFI_HOB_RESOURCE_DESCRIPTOR), // HobLength\r
+ 0 // Reserved\r
+ },\r
+ {\r
+ 0 // Owner Guid\r
+ },\r
+ EFI_RESOURCE_FIRMWARE_DEVICE, // ResourceType\r
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE), // ResourceAttribute\r
+ 0, // PhysicalStart\r
+ 0 // ResourceLength\r
+ },\r
+ { // Cpu\r
+ { // Header\r
+ EFI_HOB_TYPE_CPU, // HobType\r
+ sizeof (EFI_HOB_CPU), // HobLength\r
+ 0 // Reserved\r
+ },\r
+ 52, // SizeOfMemorySpace - Architecture Max\r
+ 16, // SizeOfIoSpace,\r
+ {\r
+ 0, 0, 0, 0, 0, 0 // Reserved[6]\r
+ }\r
+ },\r
+ { // Stack HOB\r
+ { // header\r
+ EFI_HOB_TYPE_MEMORY_ALLOCATION, // Hob type\r
+ sizeof (EFI_HOB_MEMORY_ALLOCATION_STACK), // Hob size\r
+ 0 // reserved\r
+ },\r
+ {\r
+ EFI_HOB_MEMORY_ALLOC_STACK_GUID,\r
+ 0x0, // EFI_PHYSICAL_ADDRESS MemoryBaseAddress;\r
+ 0x0, // UINT64 MemoryLength;\r
+ EfiBootServicesData, // EFI_MEMORY_TYPE MemoryType; \r
+ 0, 0, 0, 0 // Reserved Reserved[4]; \r
+ }\r
+ },\r
+ { // MemoryAllocation for HOB's & Images\r
+ {\r
+ EFI_HOB_TYPE_MEMORY_ALLOCATION, // HobType\r
+ sizeof (EFI_HOB_MEMORY_ALLOCATION), // HobLength\r
+ 0 // Reserved\r
+ },\r
+ {\r
+ {\r
+ 0, //EFI_HOB_MEMORY_ALLOC_MODULE_GUID // Name\r
+ },\r
+ 0x0, // EFI_PHYSICAL_ADDRESS MemoryBaseAddress;\r
+ 0x0, // UINT64 MemoryLength;\r
+ EfiBootServicesData, // EFI_MEMORY_TYPE MemoryType; \r
+ {\r
+ 0, 0, 0, 0 // Reserved Reserved[4]; \r
+ }\r
+ }\r
+ },\r
+ { // MemoryFreeUnder1MB for unused memory that DXE core will claim\r
+ {\r
+ EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, // HobType\r
+ sizeof (EFI_HOB_RESOURCE_DESCRIPTOR), // HobLength\r
+ 0 // Reserved\r
+ },\r
+ {\r
+ 0 // Owner Guid\r
+ },\r
+ EFI_RESOURCE_SYSTEM_MEMORY, // ResourceType\r
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | \r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | \r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | \r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE), \r
+ 0x0, // PhysicalStart\r
+ 0 // ResourceLength\r
+ },\r
+ { // MemoryFreeAbove1MB for unused memory that DXE core will claim\r
+ {\r
+ EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, // HobType\r
+ sizeof (EFI_HOB_RESOURCE_DESCRIPTOR), // HobLength\r
+ 0 // Reserved\r
+ },\r
+ {\r
+ 0 // Owner Guid\r
+ },\r
+ EFI_RESOURCE_SYSTEM_MEMORY, // ResourceType\r
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | \r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | \r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | \r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE), \r
+ 0x0, // PhysicalStart\r
+ 0 // ResourceLength\r
+ },\r
+ { // MemoryFreeAbove4GB for unused memory that DXE core will claim\r
+ {\r
+ EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, // HobType\r
+ sizeof (EFI_HOB_RESOURCE_DESCRIPTOR), // HobLength\r
+ 0 // Reserved\r
+ },\r
+ {\r
+ 0 // Owner Guid\r
+ },\r
+ EFI_RESOURCE_SYSTEM_MEMORY, // ResourceType\r
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | \r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | \r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | \r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE), \r
+ 0x0, // PhysicalStart\r
+ 0 // ResourceLength\r
+ },\r
+ { // Memory Allocation Module for DxeCore\r
+ { // header\r
+ EFI_HOB_TYPE_MEMORY_ALLOCATION, // Hob type\r
+ sizeof (EFI_HOB_MEMORY_ALLOCATION_MODULE), // Hob size\r
+ 0 // reserved\r
+ },\r
+ {\r
+ EFI_HOB_MEMORY_ALLOC_MODULE_GUID,\r
+ 0x0, // EFI_PHYSICAL_ADDRESS MemoryBaseAddress;\r
+ 0x0, // UINT64 MemoryLength;\r
+ EfiBootServicesCode, // EFI_MEMORY_TYPE MemoryType; \r
+ {\r
+ 0, 0, 0, 0 // UINT8 Reserved[4]; \r
+ },\r
+ },\r
+ EFI_DXE_FILE_GUID,\r
+ 0x0 // EFI_PHYSICAL_ADDRESS of EntryPoint;\r
+ },\r
+ { // Memory Map Hints to reduce fragmentation in the memory map\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (MEMORY_TYPE_INFORMATION_HOB), // Hob size\r
+ 0, // reserved\r
+ EFI_MEMORY_TYPE_INFORMATION_GUID,\r
+ {\r
+ {\r
+ EfiACPIReclaimMemory,\r
+ 0x80\r
+ }, // 0x80 pages = 512k for ASL\r
+ {\r
+ EfiACPIMemoryNVS,\r
+ 0x100\r
+ }, // 0x100 pages = 1024k for S3, SMM, etc\r
+ {\r
+ EfiReservedMemoryType,\r
+ 0x04\r
+ }, // 16k for BIOS Reserved\r
+ {\r
+ EfiRuntimeServicesData,\r
+ 0x100\r
+ },\r
+ {\r
+ EfiRuntimeServicesCode,\r
+ 0x100\r
+ },\r
+ {\r
+ EfiBootServicesCode,\r
+ 0x200\r
+ },\r
+ {\r
+ EfiBootServicesData,\r
+ 0x200\r
+ },\r
+ {\r
+ EfiLoaderCode,\r
+ 0x100\r
+ },\r
+ {\r
+ EfiLoaderData,\r
+ 0x100\r
+ },\r
+ {\r
+ EfiMaxMemoryType,\r
+ 0\r
+ }\r
+ }\r
+ },\r
+ { // Pointer to ACPI Table\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (TABLE_HOB), // Hob size\r
+ 0, // reserved\r
+ EFI_ACPI_TABLE_GUID,\r
+ 0\r
+ },\r
+ { // Pointer to ACPI20 Table\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (TABLE_HOB), // Hob size\r
+ 0, // reserved\r
+ EFI_ACPI_20_TABLE_GUID,\r
+ 0\r
+ },\r
+ { // Pointer to SMBIOS Table\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (TABLE_HOB), // Hob size\r
+ 0, // reserved\r
+ EFI_SMBIOS_TABLE_GUID,\r
+ 0\r
+ },\r
+ { // Pointer to MPS Table\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (TABLE_HOB), // Hob size\r
+ 0, // reserved\r
+ EFI_MPS_TABLE_GUID,\r
+ 0\r
+ },\r
+ /**\r
+ { // Pointer to FlushInstructionCache\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (PROTOCOL_HOB), // Hob size\r
+ 0, // reserved\r
+ EFI_PEI_FLUSH_INSTRUCTION_CACHE_GUID,\r
+ NULL\r
+ },\r
+ { // Pointer to TransferControl\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (PROTOCOL_HOB), // Hob size\r
+ 0, // reserved\r
+ EFI_PEI_TRANSFER_CONTROL_GUID,\r
+ NULL\r
+ },\r
+ { // Pointer to PeCoffLoader\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (PROTOCOL_HOB), // Hob size\r
+ 0, // reserved\r
+ EFI_PEI_PE_COFF_LOADER_GUID,\r
+ NULL\r
+ },\r
+ { // Pointer to EfiDecompress\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (PROTOCOL_HOB), // Hob size\r
+ 0, // reserved\r
+ EFI_DECOMPRESS_PROTOCOL_GUID,\r
+ NULL\r
+ },\r
+ { // Pointer to TianoDecompress\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (PROTOCOL_HOB), // Hob size\r
+ 0, // reserved\r
+ EFI_TIANO_DECOMPRESS_PROTOCOL_GUID,\r
+ NULL\r
+ },\r
+ **/\r
+ { // Pointer to ReportStatusCode\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (PROTOCOL_HOB), // Hob size\r
+ 0, // reserved\r
+ EFI_STATUS_CODE_RUNTIME_PROTOCOL_GUID,\r
+ NULL\r
+ },\r
+ { // EFILDR Memory Descriptor\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (MEMORY_DESC_HOB), // Hob size\r
+ 0, // reserved\r
+ EFI_LDR_MEMORY_DESCRIPTOR_GUID,\r
+ 0,\r
+ NULL\r
+ },\r
+ { // Pci Express Base Address Hob\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (PCI_EXPRESS_BASE_HOB), // Hob size\r
+ 0, // reserved\r
+ EFI_PCI_EXPRESS_BASE_ADDRESS_GUID,\r
+ {\r
+ 0,\r
+ 0,\r
+ 0,\r
+ }\r
+ },\r
+ { // Acpi Description Hob\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (ACPI_DESCRIPTION_HOB), // Hob size\r
+ 0, // reserved\r
+ EFI_ACPI_DESCRIPTION_GUID,\r
+ {\r
+ 0,\r
+ }\r
+ },\r
+ { // NV Storage FV Resource\r
+ {\r
+ EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, // HobType\r
+ sizeof (EFI_HOB_RESOURCE_DESCRIPTOR), // HobLength\r
+ 0 // Reserved\r
+ },\r
+ {\r
+ 0 // Owner Guid\r
+ },\r
+ EFI_RESOURCE_FIRMWARE_DEVICE, // ResourceType\r
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE), // ResourceAttribute\r
+ 0, // PhysicalStart (Fixed later)\r
+ NV_STORAGE_FVB_SIZE // ResourceLength\r
+ },\r
+ { // FVB holding NV Storage\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (FVB_HOB),\r
+ 0,\r
+ EFI_FLASH_MAP_HOB_GUID,\r
+ {\r
+ 0, 0, 0, // Reserved[3]\r
+ EFI_FLASH_AREA_GUID_DEFINED, // AreaType\r
+ EFI_SYSTEM_NV_DATA_HOB_GUID, // AreaTypeGuid\r
+ 1,\r
+ {\r
+ EFI_FLASH_AREA_FV | EFI_FLASH_AREA_MEMMAPPED_FV, // SubAreaData.Attributes\r
+ 0, // SubAreaData.Reserved\r
+ 0, // SubAreaData.Base (Fixed later)\r
+ NV_STORAGE_FVB_SIZE, // SubAreaData.Length\r
+ EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL_GUID // SubAreaData.FileSystem\r
+ }, \r
+ 0, // VolumeSignature (Fixed later)\r
+ NV_STORAGE_FILE_PATH, // Mapped file without padding\r
+ // TotalFVBSize = FileSize + PaddingSize = multiple of BLOCK_SIZE\r
+ NV_STORAGE_SIZE + EFI_RUNTIME_UPDATABLE_FV_HEADER_LENGTH,\r
+ // ActuralSize\r
+ EFI_RUNTIME_UPDATABLE_FV_HEADER_LENGTH\r
+ }\r
+ },\r
+ { // NV Storage Hob\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (FVB_HOB), // Hob size\r
+ 0, // reserved\r
+ EFI_FLASH_MAP_HOB_GUID,\r
+ {\r
+ 0, 0, 0, // Reserved[3]\r
+ EFI_FLASH_AREA_EFI_VARIABLES, // AreaType\r
+ { 0 }, // AreaTypeGuid\r
+ 1,\r
+ {\r
+ EFI_FLASH_AREA_SUBFV | EFI_FLASH_AREA_MEMMAPPED_FV, // SubAreaData.Attributes\r
+ 0, // SubAreaData.Reserved\r
+ 0, // SubAreaData.Base (Fixed later)\r
+ NV_STORAGE_SIZE, // SubAreaData.Length\r
+ EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL_GUID // SubAreaData.FileSystem\r
+ }, \r
+ 0,\r
+ NV_STORAGE_FILE_PATH,\r
+ NV_STORAGE_SIZE,\r
+ 0\r
+ }\r
+ },\r
+ { // FVB holding FTW spaces including Working & Spare space\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (FVB_HOB),\r
+ 0,\r
+ EFI_FLASH_MAP_HOB_GUID,\r
+ {\r
+ 0, 0, 0, // Reserved[3]\r
+ EFI_FLASH_AREA_GUID_DEFINED, // AreaType\r
+ EFI_SYSTEM_NV_DATA_HOB_GUID, // AreaTypeGuid\r
+ 1,\r
+ {\r
+ EFI_FLASH_AREA_FV | EFI_FLASH_AREA_MEMMAPPED_FV, // SubAreaData.Attributes\r
+ 0, // SubAreaData.Reserved\r
+ 0, // SubAreaData.Base (Fixed later)\r
+ NV_FTW_FVB_SIZE, // SubAreaData.Length\r
+ EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL_GUID // SubAreaData.FileSystem\r
+ }, \r
+ 0,\r
+ L"", // Empty String indicates using memory\r
+ 0,\r
+ 0\r
+ }\r
+ },\r
+ { // NV Ftw working Hob\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (FVB_HOB), // Hob size\r
+ 0, // reserved\r
+ EFI_FLASH_MAP_HOB_GUID,\r
+ {\r
+ 0, 0, 0, // Reserved[3]\r
+ EFI_FLASH_AREA_FTW_STATE, // AreaType\r
+ { 0 }, // AreaTypeGuid\r
+ 1,\r
+ {\r
+ EFI_FLASH_AREA_SUBFV | EFI_FLASH_AREA_MEMMAPPED_FV, // SubAreaData.Attributes\r
+ 0, // SubAreaData.Reserved\r
+ 0, // SubAreaData.Base (Fixed later)\r
+ NV_FTW_WORKING_SIZE, // SubAreaData.Length\r
+ EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL_GUID // SubAreaData.FileSystem\r
+ }, \r
+ 0, // VolumeSignature\r
+ L"",\r
+ 0,\r
+ 0\r
+ }\r
+ },\r
+ { // NV Ftw spare Hob\r
+ EFI_HOB_TYPE_GUID_EXTENSION, // Hob type\r
+ sizeof (FVB_HOB), // Hob size\r
+ 0, // reserved\r
+ EFI_FLASH_MAP_HOB_GUID,\r
+ {\r
+ 0, 0, 0, // Reserved[3]\r
+ EFI_FLASH_AREA_FTW_BACKUP, // AreaType\r
+ { 0 }, // AreaTypeGuid\r
+ 1,\r
+ {\r
+ EFI_FLASH_AREA_SUBFV | EFI_FLASH_AREA_MEMMAPPED_FV, // SubAreaData.Attributes\r
+ 0, // SubAreaData.Reserved\r
+ 0, // SubAreaData.Base (Fixed later)\r
+ NV_FTW_SPARE_SIZE, // SubAreaData.Length\r
+ EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL_GUID // SubAreaData.FileSystem\r
+ }, \r
+ 0,\r
+ L"",\r
+ 0,\r
+ 0\r
+ }\r
+ },\r
+ { // EndOfHobList\r
+ EFI_HOB_TYPE_END_OF_HOB_LIST, // HobType\r
+ sizeof (EFI_HOB_GENERIC_HEADER), // HobLength\r
+ 0 // Reserved\r
+ }\r
+};\r
+\r
+HOB_TEMPLATE *gHob = &gHobTemplate;\r
+\r
+VOID *\r
+PrepareHobMemory (\r
+ IN UINTN NumberOfMemoryMapEntries,\r
+ IN EFI_MEMORY_DESCRIPTOR *EfiMemoryDescriptor\r
+ )\r
+/*++\r
+Description:\r
+ Update the Hob filling MemoryFreeUnder1MB, MemoryAbove1MB, MemoryAbove4GB\r
+\r
+Arguments:\r
+ NumberOfMemoryMapEntries - Count of Memory Descriptors\r
+ EfiMemoryDescriptor - Point to the buffer containing NumberOfMemoryMapEntries Memory Descriptors\r
+\r
+Return:\r
+ VOID * : The end address of MemoryAbove1MB (or the top free memory under 4GB)\r
+--*/\r
+{\r
+ UINTN Index;\r
+\r
+ //\r
+ // Prepare Low Memory\r
+ // 0x18 pages is 72 KB.\r
+ //\r
+ gHob->MemoryFreeUnder1MB.ResourceLength = EFI_MEMORY_BELOW_1MB_END - EFI_MEMORY_BELOW_1MB_START;\r
+ gHob->MemoryFreeUnder1MB.PhysicalStart = EFI_MEMORY_BELOW_1MB_START;\r
+\r
+ //\r
+ // Prepare High Memory\r
+ // Assume Memory Map is ordered from low to high\r
+ //\r
+ gHob->MemoryAbove1MB.PhysicalStart = 0;\r
+ gHob->MemoryAbove1MB.ResourceLength = 0;\r
+ gHob->MemoryAbove4GB.PhysicalStart = 0;\r
+ gHob->MemoryAbove4GB.ResourceLength = 0;\r
+\r
+ for (Index = 0; Index < NumberOfMemoryMapEntries; Index++) {\r
+ //\r
+ // Skip regions below 1MB\r
+ //\r
+ if (EfiMemoryDescriptor[Index].PhysicalStart < 0x100000) {\r
+ continue;\r
+ }\r
+ //\r
+ // Process regions above 1MB\r
+ //\r
+ if (EfiMemoryDescriptor[Index].PhysicalStart >= 0x100000) {\r
+ if (EfiMemoryDescriptor[Index].Type == EfiConventionalMemory) {\r
+ if (gHob->MemoryAbove1MB.PhysicalStart == 0) {\r
+ gHob->MemoryAbove1MB.PhysicalStart = EfiMemoryDescriptor[Index].PhysicalStart;\r
+ gHob->MemoryAbove1MB.ResourceLength = LShiftU64 (EfiMemoryDescriptor[Index].NumberOfPages, EFI_PAGE_SHIFT);\r
+ } else if (gHob->MemoryAbove1MB.PhysicalStart + gHob->MemoryAbove1MB.ResourceLength == EfiMemoryDescriptor[Index].PhysicalStart) {\r
+ gHob->MemoryAbove1MB.ResourceLength += LShiftU64 (EfiMemoryDescriptor[Index].NumberOfPages, EFI_PAGE_SHIFT);\r
+ }\r
+ }\r
+ if ((EfiMemoryDescriptor[Index].Type == EfiReservedMemoryType) ||\r
+ (EfiMemoryDescriptor[Index].Type >= EfiACPIReclaimMemory) ) {\r
+ continue;\r
+ }\r
+ if ((EfiMemoryDescriptor[Index].Type == EfiRuntimeServicesCode) ||\r
+ (EfiMemoryDescriptor[Index].Type == EfiRuntimeServicesData)) {\r
+ break;\r
+ }\r
+ }\r
+ //\r
+ // Process region above 4GB\r
+ //\r
+ if (EfiMemoryDescriptor[Index].PhysicalStart >= 0x100000000) {\r
+ if (EfiMemoryDescriptor[Index].Type == EfiConventionalMemory) {\r
+ if (gHob->MemoryAbove4GB.PhysicalStart == 0) {\r
+ gHob->MemoryAbove4GB.PhysicalStart = EfiMemoryDescriptor[Index].PhysicalStart;\r
+ gHob->MemoryAbove4GB.ResourceLength = LShiftU64 (EfiMemoryDescriptor[Index].NumberOfPages, EFI_PAGE_SHIFT);\r
+ }\r
+ if (gHob->MemoryAbove4GB.PhysicalStart + gHob->MemoryAbove4GB.ResourceLength == \r
+ EfiMemoryDescriptor[Index].PhysicalStart) {\r
+ gHob->MemoryAbove4GB.ResourceLength += LShiftU64 (EfiMemoryDescriptor[Index].NumberOfPages, EFI_PAGE_SHIFT);\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ if (gHob->MemoryAbove4GB.ResourceLength == 0) {\r
+ //\r
+ // If there is no memory above 4GB then change the resource descriptor HOB\r
+ // into another type. I'm doing this as it's unclear if a resource\r
+ // descriptor HOB of length zero is valid. Spec does not say it's illegal,\r
+ // but code in EDK does not seem to handle this case.\r
+ //\r
+ gHob->MemoryAbove4GB.Header.HobType = EFI_HOB_TYPE_UNUSED;\r
+ }\r
+\r
+ return (VOID *)(UINTN)(gHob->MemoryAbove1MB.PhysicalStart + gHob->MemoryAbove1MB.ResourceLength);\r
+}\r
+\r
+VOID *\r
+PrepareHobStack (\r
+ IN VOID *StackTop\r
+ )\r
+{\r
+ gHob->Stack.AllocDescriptor.MemoryLength = EFI_MEMORY_STACK_PAGE_NUM * EFI_PAGE_SIZE;\r
+ gHob->Stack.AllocDescriptor.MemoryBaseAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)StackTop - gHob->Stack.AllocDescriptor.MemoryLength;\r
+\r
+ return (VOID *)(UINTN)gHob->Stack.AllocDescriptor.MemoryBaseAddress;\r
+}\r
+\r
+VOID *\r
+PrepareHobMemoryDescriptor (\r
+ VOID *MemoryDescriptorTop,\r
+ UINTN MemDescCount,\r
+ EFI_MEMORY_DESCRIPTOR *MemDesc\r
+ )\r
+{\r
+ gHob->MemoryDescriptor.MemDescCount = MemDescCount;\r
+ gHob->MemoryDescriptor.MemDesc = (EFI_MEMORY_DESCRIPTOR *)((UINTN)MemoryDescriptorTop - MemDescCount * sizeof(EFI_MEMORY_DESCRIPTOR));\r
+ //\r
+ // Make MemoryDescriptor.MemDesc page aligned\r
+ //\r
+ gHob->MemoryDescriptor.MemDesc = (EFI_MEMORY_DESCRIPTOR *)((UINTN) gHob->MemoryDescriptor.MemDesc & ~EFI_PAGE_MASK);\r
+\r
+ CopyMem (gHob->MemoryDescriptor.MemDesc, MemDesc, MemDescCount * sizeof(EFI_MEMORY_DESCRIPTOR));\r
+\r
+ return gHob->MemoryDescriptor.MemDesc;\r
+}\r
+\r
+VOID\r
+PrepareHobBfv (\r
+ VOID *Bfv,\r
+ UINTN BfvLength\r
+ )\r
+{\r
+ UINTN BfvLengthPageSize;\r
+\r
+ //\r
+ // Calculate BFV location at top of the memory region.\r
+ // This is like a RAM Disk. Align to page boundry.\r
+ //\r
+ BfvLengthPageSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (BfvLength));\r
+ \r
+ gHob->Bfv.BaseAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)Bfv;\r
+ gHob->Bfv.Length = BfvLength;\r
+\r
+ //\r
+ // Resource descriptor for the FV\r
+ //\r
+ gHob->BfvResource.PhysicalStart = gHob->Bfv.BaseAddress;\r
+ gHob->BfvResource.ResourceLength = gHob->Bfv.Length;\r
+}\r
+\r
+VOID\r
+PrepareHobDxeCore (\r
+ VOID *DxeCoreEntryPoint,\r
+ EFI_PHYSICAL_ADDRESS DxeCoreImageBase,\r
+ UINT64 DxeCoreLength\r
+ )\r
+{\r
+ gHob->DxeCore.MemoryAllocationHeader.MemoryBaseAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)DxeCoreImageBase;\r
+ gHob->DxeCore.MemoryAllocationHeader.MemoryLength = DxeCoreLength;\r
+ gHob->DxeCore.EntryPoint = (EFI_PHYSICAL_ADDRESS)(UINTN)DxeCoreEntryPoint;\r
+}\r
+\r
+VOID *\r
+PrepareHobNvStorage (\r
+ VOID *NvStorageTop\r
+ )\r
+/*\r
+ Initialize Block-Aligned Firmware Block.\r
+\r
+ Variable:\r
+ +-------------------+\r
+ | FV_Header |\r
+ +-------------------+\r
+ | |\r
+ |VAR_STORAGE(0x4000)|\r
+ | |\r
+ +-------------------+\r
+ FTW:\r
+ +-------------------+\r
+ | FV_Header |\r
+ +-------------------+\r
+ | |\r
+ | Working(0x2000) |\r
+ | |\r
+ +-------------------+\r
+ | |\r
+ | Spare(0x10000) |\r
+ | |\r
+ +-------------------+\r
+*/\r
+{\r
+ static VARIABLE_STORE_HEADER VarStoreHeader = {\r
+ VARIABLE_STORE_SIGNATURE,\r
+ 0xffffffff, // will be fixed in Variable driver\r
+ VARIABLE_STORE_FORMATTED,\r
+ VARIABLE_STORE_HEALTHY,\r
+ 0,\r
+ 0\r
+ };\r
+ \r
+ static EFI_FIRMWARE_VOLUME_HEADER NvStorageFvbHeader = {\r
+ {\r
+ 0,\r
+ }, // ZeroVector[16]\r
+ EFI_SYSTEM_NV_DATA_FV_GUID,\r
+ NV_STORAGE_FVB_SIZE,\r
+ EFI_FVH_SIGNATURE,\r
+ EFI_FVB_READ_ENABLED_CAP |\r
+ EFI_FVB_READ_STATUS |\r
+ EFI_FVB_WRITE_ENABLED_CAP |\r
+ EFI_FVB_WRITE_STATUS |\r
+ EFI_FVB_ERASE_POLARITY,\r
+ EFI_RUNTIME_UPDATABLE_FV_HEADER_LENGTH,\r
+ 0, // CheckSum\r
+ 0, // ExtHeaderOffset\r
+ {\r
+ 0,\r
+ }, // Reserved[1]\r
+ 1, // Revision\r
+ {\r
+ {\r
+ NV_STORAGE_FVB_BLOCK_NUM,\r
+ FV_BLOCK_SIZE,\r
+ }\r
+ }\r
+ };\r
+\r
+ static EFI_FV_BLOCK_MAP_ENTRY BlockMapEntryEnd = {0, 0};\r
+\r
+ EFI_PHYSICAL_ADDRESS StorageFvbBase;\r
+ EFI_PHYSICAL_ADDRESS FtwFvbBase;\r
+\r
+ UINT16 *Ptr;\r
+ UINT16 Checksum;\r
+\r
+\r
+ //\r
+ // Use first 16-byte Reset Vector of FVB to store extra information\r
+ // UINT32 Offset 0 stores the volume signature\r
+ // UINT8 Offset 4 : should init the Variable Store Header if non-zero\r
+ //\r
+ gHob->NvStorageFvb.FvbInfo.VolumeId = *(UINT32 *) (UINTN) (NV_STORAGE_STATE);\r
+ gHob->NvStorage. FvbInfo.VolumeId = *(UINT32 *) (UINTN) (NV_STORAGE_STATE);\r
+\r
+ //\r
+ // *(NV_STORAGE_STATE + 4):\r
+ // 2 - Size error\r
+ // 1 - File not exist\r
+ // 0 - File exist with correct size\r
+ //\r
+ if (*(UINT8 *) (UINTN) (NV_STORAGE_STATE + 4) == 2) {\r
+ ClearScreen ();\r
+ PrintString ("Error: Size of Efivar.bin should be 16k!\n");\r
+ CpuDeadLoop();\r
+ }\r
+ \r
+ if (*(UINT8 *) (UINTN) (NV_STORAGE_STATE + 4) != 0) {\r
+ //\r
+ // Efivar.bin doesn't exist\r
+ // 1. Init variable storage header to valid header\r
+ //\r
+ CopyMem (\r
+ (VOID *) (UINTN) NV_STORAGE_START,\r
+ &VarStoreHeader,\r
+ sizeof (VARIABLE_STORE_HEADER)\r
+ );\r
+ //\r
+ // 2. set all bits in variable storage body to 1\r
+ //\r
+ SetMem (\r
+ (VOID *) (UINTN) (NV_STORAGE_START + sizeof (VARIABLE_STORE_HEADER)),\r
+ NV_STORAGE_SIZE - sizeof (VARIABLE_STORE_HEADER),\r
+ 0xff\r
+ );\r
+ }\r
+\r
+ //\r
+ // Relocate variable storage\r
+ // \r
+ // 1. Init FVB Header to valid header: First 0x48 bytes\r
+ // In real platform, these fields are fixed by tools\r
+ //\r
+ //\r
+ Checksum = 0;\r
+ for (\r
+ Ptr = (UINT16 *) &NvStorageFvbHeader; \r
+ Ptr < (UINT16 *) ((UINTN) (UINT8 *) &NvStorageFvbHeader + sizeof (EFI_FIRMWARE_VOLUME_HEADER));\r
+ ++Ptr\r
+ ) {\r
+ Checksum = (UINT16) (Checksum + (*Ptr));\r
+ }\r
+ NvStorageFvbHeader.Checksum = (UINT16) (0x10000 - Checksum);\r
+ StorageFvbBase = (EFI_PHYSICAL_ADDRESS)(((UINTN)NvStorageTop - NV_STORAGE_FVB_SIZE - NV_FTW_FVB_SIZE) & ~EFI_PAGE_MASK);\r
+ CopyMem ((VOID *) (UINTN) StorageFvbBase, &NvStorageFvbHeader, sizeof (EFI_FIRMWARE_VOLUME_HEADER));\r
+ CopyMem (\r
+ (VOID *) (UINTN) (StorageFvbBase + sizeof (EFI_FIRMWARE_VOLUME_HEADER)),\r
+ &BlockMapEntryEnd,\r
+ sizeof (EFI_FV_BLOCK_MAP_ENTRY)\r
+ );\r
+ \r
+ //\r
+ // 2. Relocate variable data\r
+ //\r
+ CopyMem (\r
+ (VOID *) (UINTN) (StorageFvbBase + EFI_RUNTIME_UPDATABLE_FV_HEADER_LENGTH),\r
+ (VOID *) (UINTN) NV_STORAGE_START,\r
+ NV_STORAGE_SIZE\r
+ );\r
+\r
+ //\r
+ // 3. Set the remaining memory to 0xff\r
+ //\r
+ SetMem (\r
+ (VOID *) (UINTN) (StorageFvbBase + EFI_RUNTIME_UPDATABLE_FV_HEADER_LENGTH + NV_STORAGE_SIZE),\r
+ NV_STORAGE_FVB_SIZE - NV_STORAGE_SIZE - EFI_RUNTIME_UPDATABLE_FV_HEADER_LENGTH,\r
+ 0xff\r
+ );\r
+\r
+ //\r
+ // Create the FVB holding NV Storage in memory\r
+ //\r
+ gHob->NvStorageFvResource.PhysicalStart =\r
+ gHob->NvStorageFvb.FvbInfo.Entries[0].Base = StorageFvbBase;\r
+ //\r
+ // Create the NV Storage Hob\r
+ //\r
+ gHob->NvStorage.FvbInfo.Entries[0].Base = StorageFvbBase + EFI_RUNTIME_UPDATABLE_FV_HEADER_LENGTH;\r
+\r
+ //\r
+ // Create the FVB holding FTW spaces\r
+ //\r
+ FtwFvbBase = (EFI_PHYSICAL_ADDRESS)((UINTN) StorageFvbBase + NV_STORAGE_FVB_SIZE);\r
+ gHob->NvFtwFvb.FvbInfo.Entries[0].Base = FtwFvbBase;\r
+ //\r
+ // Put FTW Working in front\r
+ //\r
+ gHob->NvFtwWorking.FvbInfo.Entries[0].Base = FtwFvbBase + EFI_RUNTIME_UPDATABLE_FV_HEADER_LENGTH;\r
+\r
+ //\r
+ // Put FTW Spare area after FTW Working area\r
+ //\r
+ gHob->NvFtwSpare.FvbInfo.Entries[0].Base = \r
+ (EFI_PHYSICAL_ADDRESS)((UINTN) FtwFvbBase + EFI_RUNTIME_UPDATABLE_FV_HEADER_LENGTH + NV_FTW_WORKING_SIZE);\r
+ \r
+ return (VOID *)(UINTN)StorageFvbBase;\r
+}\r
+\r
+VOID\r
+PrepareHobPhit (\r
+ VOID *MemoryTop,\r
+ VOID *FreeMemoryTop\r
+ )\r
+{\r
+ gHob->Phit.EfiMemoryTop = (EFI_PHYSICAL_ADDRESS)(UINTN)MemoryTop;\r
+ gHob->Phit.EfiMemoryBottom = gHob->Phit.EfiMemoryTop - CONSUMED_MEMORY;\r
+ gHob->Phit.EfiFreeMemoryTop = (EFI_PHYSICAL_ADDRESS)(UINTN)FreeMemoryTop;\r
+ gHob->Phit.EfiFreeMemoryBottom = gHob->Phit.EfiMemoryBottom + sizeof(HOB_TEMPLATE);\r
+\r
+ CopyMem ((VOID *)(UINTN)gHob->Phit.EfiMemoryBottom, gHob, sizeof(HOB_TEMPLATE));\r
+ gHob = (HOB_TEMPLATE *)(UINTN)gHob->Phit.EfiMemoryBottom;\r
+\r
+ gHob->Phit.EfiEndOfHobList = (EFI_PHYSICAL_ADDRESS)(UINTN)&gHob->EndOfHobList;\r
+}\r
+\r
+VOID\r
+PrepareHobCpu (\r
+ VOID\r
+ )\r
+{\r
+ EFI_CPUID_REGISTER Reg;\r
+ UINT8 CpuMemoryAddrBitNumber;\r
+\r
+ //\r
+ // Create a CPU hand-off information\r
+ //\r
+ CpuMemoryAddrBitNumber = 36;\r
+ AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION, &Reg.RegEax, &Reg.RegEbx, &Reg.RegEcx, &Reg.RegEdx);\r
+\r
+ if (Reg.RegEax >= CPUID_EXTENDED_ADD_SIZE) {\r
+ AsmCpuid (CPUID_EXTENDED_ADD_SIZE, &Reg.RegEax, &Reg.RegEbx, &Reg.RegEcx, &Reg.RegEdx);\r
+ CpuMemoryAddrBitNumber = (UINT8)(UINTN)(Reg.RegEax & 0xFF);\r
+ }\r
+ \r
+ gHob->Cpu.SizeOfMemorySpace = CpuMemoryAddrBitNumber;\r
+}\r
+\r
+VOID\r
+CompleteHobGeneration (\r
+ VOID\r
+ )\r
+{\r
+ gHob->MemoryAllocation.AllocDescriptor.MemoryBaseAddress = gHob->Phit.EfiFreeMemoryTop;\r
+ //\r
+ // Reserve all the memory under Stack above FreeMemoryTop as allocated\r
+ //\r
+ gHob->MemoryAllocation.AllocDescriptor.MemoryLength = gHob->Stack.AllocDescriptor.MemoryBaseAddress - gHob->Phit.EfiFreeMemoryTop;\r
+\r
+ //\r
+ // adjust Above1MB ResourceLength\r
+ //\r
+ if (gHob->MemoryAbove1MB.PhysicalStart + gHob->MemoryAbove1MB.ResourceLength > gHob->Phit.EfiMemoryTop) {\r
+ gHob->MemoryAbove1MB.ResourceLength = gHob->Phit.EfiMemoryTop - gHob->MemoryAbove1MB.PhysicalStart;\r
+ }\r
+}\r
+\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006 - 2007, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ HobGeneration.h\r
+\r
+Abstract:\r
+\r
+Revision History:\r
+\r
+--*/\r
+\r
+#ifndef _DXELDR_HOB_GENERATION_H_\r
+#define _DXELDR_HOB_GENERATION_H_\r
+\r
+#include "DxeIpl.h"\r
+\r
+#define EFI_MEMORY_BELOW_1MB_START 0x86000\r
+#define EFI_MEMORY_BELOW_1MB_END 0x9F800\r
+#define EFI_MEMORY_STACK_PAGE_NUM 0x20\r
+#define CONSUMED_MEMORY 0x2000000\r
+\r
+#define NV_STORAGE_START 0x15000\r
+#define NV_STORAGE_STATE 0x19000\r
+\r
+#define EFI_LDR_MEMORY_DESCRIPTOR_GUID \\r
+ { 0x7701d7e5, 0x7d1d, 0x4432, 0xa4, 0x68, 0x67, 0x3d, 0xab, 0x8a, 0xde, 0x60 }\r
+\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+ EFI_HOB_GUID_TYPE Hob;\r
+ EFI_MEMORY_TYPE_INFORMATION Info[10];\r
+} MEMORY_TYPE_INFORMATION_HOB;\r
+\r
+typedef struct {\r
+ EFI_HOB_GUID_TYPE Hob;\r
+ EFI_PHYSICAL_ADDRESS Table;\r
+} TABLE_HOB;\r
+\r
+typedef struct {\r
+ EFI_HOB_GUID_TYPE Hob;\r
+ VOID *Interface;\r
+} PROTOCOL_HOB;\r
+\r
+typedef struct {\r
+ EFI_HOB_GUID_TYPE Hob;\r
+ UINTN MemDescCount;\r
+ EFI_MEMORY_DESCRIPTOR *MemDesc;\r
+} MEMORY_DESC_HOB;\r
+\r
+typedef struct {\r
+ EFI_HOB_GUID_TYPE Hob;\r
+ // Note: we get only one PCI Segment now.\r
+ EFI_PCI_EXPRESS_BASE_ADDRESS_INFORMATION PciExpressBaseAddressInfo;\r
+} PCI_EXPRESS_BASE_HOB;\r
+\r
+typedef struct {\r
+ EFI_HOB_GUID_TYPE Hob;\r
+ EFI_ACPI_DESCRIPTION AcpiDescription;\r
+} ACPI_DESCRIPTION_HOB;\r
+\r
+typedef struct {\r
+ EFI_HOB_GUID_TYPE Hob;\r
+ EFI_FLASH_MAP_FS_ENTRY_DATA FvbInfo;\r
+} FVB_HOB;\r
+\r
+typedef struct {\r
+ EFI_HOB_HANDOFF_INFO_TABLE Phit;\r
+ EFI_HOB_FIRMWARE_VOLUME Bfv;\r
+ EFI_HOB_RESOURCE_DESCRIPTOR BfvResource;\r
+ EFI_HOB_CPU Cpu;\r
+ EFI_HOB_MEMORY_ALLOCATION_STACK Stack;\r
+ EFI_HOB_MEMORY_ALLOCATION MemoryAllocation;\r
+ EFI_HOB_RESOURCE_DESCRIPTOR MemoryFreeUnder1MB;\r
+ EFI_HOB_RESOURCE_DESCRIPTOR MemoryAbove1MB;\r
+ EFI_HOB_RESOURCE_DESCRIPTOR MemoryAbove4GB;\r
+ EFI_HOB_MEMORY_ALLOCATION_MODULE DxeCore;\r
+ MEMORY_TYPE_INFORMATION_HOB MemoryTypeInfo;\r
+ TABLE_HOB Acpi;\r
+ TABLE_HOB Acpi20;\r
+ TABLE_HOB Smbios;\r
+ TABLE_HOB Mps;\r
+ /**\r
+ PROTOCOL_HOB FlushInstructionCache;\r
+ PROTOCOL_HOB TransferControl;\r
+ PROTOCOL_HOB PeCoffLoader;\r
+ PROTOCOL_HOB EfiDecompress;\r
+ PROTOCOL_HOB TianoDecompress;\r
+ **/\r
+ PROTOCOL_HOB SerialStatusCode;\r
+ MEMORY_DESC_HOB MemoryDescriptor;\r
+ PCI_EXPRESS_BASE_HOB PciExpress;\r
+ ACPI_DESCRIPTION_HOB AcpiInfo;\r
+ \r
+ EFI_HOB_RESOURCE_DESCRIPTOR NvStorageFvResource;\r
+\r
+ FVB_HOB NvStorageFvb;\r
+ FVB_HOB NvStorage;\r
+\r
+ FVB_HOB NvFtwFvb;\r
+ FVB_HOB NvFtwWorking;\r
+ FVB_HOB NvFtwSpare;\r
+ \r
+ EFI_HOB_GENERIC_HEADER EndOfHobList;\r
+} HOB_TEMPLATE;\r
+\r
+#pragma pack()\r
+\r
+extern HOB_TEMPLATE *gHob;\r
+\r
+VOID *\r
+PrepareHobStack (\r
+ IN VOID *StackTop\r
+ );\r
+\r
+VOID\r
+PrepareHobBfv (\r
+ VOID *Bfv,\r
+ UINTN BfvLength\r
+ );\r
+\r
+VOID *\r
+PrepareHobMemory (\r
+ IN UINTN NumberOfMemoryMapEntries,\r
+ IN EFI_MEMORY_DESCRIPTOR *EfiMemoryDescriptor\r
+ );\r
+\r
+VOID\r
+PrepareHobDxeCore (\r
+ VOID *DxeCoreEntryPoint,\r
+ EFI_PHYSICAL_ADDRESS DxeCoreImageBase,\r
+ UINT64 DxeCoreLength\r
+ );\r
+\r
+VOID *\r
+PreparePageTable (\r
+ VOID *PageNumberTop,\r
+ UINT8 SizeOfMemorySpace\r
+ );\r
+\r
+VOID *\r
+PrepareHobMemoryDescriptor (\r
+ VOID *MemoryDescriptorTop,\r
+ UINTN MemDescCount,\r
+ EFI_MEMORY_DESCRIPTOR *MemDesc\r
+ );\r
+\r
+VOID\r
+PrepareHobPhit (\r
+ VOID *MemoryTop,\r
+ VOID *FreeMemoryTop\r
+ );\r
+\r
+VOID *\r
+PrepareHobNvStorage (\r
+ VOID *NvStorageTop\r
+ );\r
+\r
+VOID\r
+PrepareHobCpu (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+CompleteHobGeneration (\r
+ VOID\r
+ );\r
+\r
+#endif\r
--- /dev/null
+ title CpuIoAccess.asm\r
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation \r
+; All rights reserved. This program and the accompanying materials \r
+; are licensed and made available under the terms and conditions of the BSD License \r
+; which accompanies this distribution. The full text of the license may be found at \r
+; http://opensource.org/licenses/bsd-license.php \r
+; \r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+; \r
+; Module Name:\r
+; CpuIoAccess.asm\r
+; \r
+; Abstract:\r
+; CPU IO Abstraction\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .686\r
+ .MODEL FLAT,C\r
+ .CODE\r
+\r
+\r
+UINT8 TYPEDEF BYTE\r
+UINT16 TYPEDEF WORD\r
+UINT32 TYPEDEF DWORD\r
+UINT64 TYPEDEF QWORD\r
+UINTN TYPEDEF UINT32\r
+\r
+\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT8\r
+; CpuIoRead8 (\r
+; IN UINT16 Port\r
+; )\r
+;------------------------------------------------------------------------------\r
+CpuIoRead8 PROC PUBLIC Port:UINT16\r
+ mov dx, Port\r
+ in al, dx\r
+ ret\r
+CpuIoRead8 ENDP\r
+\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; CpuIoWrite8 (\r
+; IN UINT16 Port,\r
+; IN UINT32 Data\r
+; )\r
+;------------------------------------------------------------------------------\r
+CpuIoWrite8 PROC PUBLIC Port:UINT16, Data:UINT32\r
+ mov eax, Data\r
+ mov dx, Port\r
+ out dx, al\r
+ ret\r
+CpuIoWrite8 ENDP\r
+\r
+\r
+END
\ No newline at end of file
--- /dev/null
+ TITLE EnterDxeCore.asm: Assembly code for the entering DxeCore\r
+;------------------------------------------------------------------------------\r
+;*\r
+;* Copyright 2006, Intel Corporation \r
+;* All rights reserved. This program and the accompanying materials \r
+;* are licensed and made available under the terms and conditions of the BSD License \r
+;* which accompanies this distribution. The full text of the license may be found at \r
+;* http://opensource.org/licenses/bsd-license.php \r
+;* \r
+;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+;* \r
+;* EnterDxeCore.asm\r
+;* \r
+;* Abstract:\r
+;*\r
+;------------------------------------------------------------------------------\r
+\r
+.686p\r
+.model flat \r
+\r
+.code\r
+.stack\r
+.MMX\r
+.XMM\r
+\r
+;\r
+; VOID\r
+; EnterDxeMain (\r
+; IN VOID *StackTop,\r
+; IN VOID *DxeCoreEntryPoint,\r
+; IN VOID *Hob,\r
+; IN VOID *PageTable\r
+; )\r
+;\r
+EnterDxeMain PROC C \\r
+ StackTop:DWORD, \\r
+ DxeCoreEntryPoint:DWORD, \\r
+ Hob:DWORD, \\r
+ PageTable:DWORD\r
+ \r
+ mov eax, PageTable\r
+; mov cr3, eax ; load page table\r
+; mov eax, cr4\r
+; bts eax, 4 ; enable CR4.PSE\r
+; mov cr4, eax\r
+; mov eax, cr0\r
+; bts eax, 31 ; enable CR0.PG\r
+; mov cr0, eax\r
+ mov ecx, DxeCoreEntryPoint\r
+ mov eax, StackTop\r
+ mov esp, eax\r
+ mov edx, Hob\r
+ push edx\r
+ push 0\r
+ jmp ecx\r
+\r
+; should never get here\r
+ jmp $\r
+ ret\r
+\r
+EnterDxeMain ENDP\r
+\r
+END\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006 - 2007, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ Paging.c\r
+\r
+Abstract:\r
+\r
+Revision History:\r
+\r
+--*/\r
+\r
+#include "DxeIpl.h"\r
+#include "HobGeneration.h"\r
+#include "VirtualMemory.h"\r
+#include "Debug.h"\r
+\r
+#define EFI_PAGE_SIZE_4K 0x1000\r
+#define EFI_PAGE_SIZE_4M 0x400000\r
+\r
+//\r
+// Create 4G 4M-page table\r
+// PDE (31:22) : 1024 entries\r
+//\r
+#define EFI_MAX_ENTRY_NUM 1024\r
+\r
+#define EFI_PDE_ENTRY_NUM EFI_MAX_ENTRY_NUM\r
+\r
+#define EFI_PDE_PAGE_NUM 1\r
+\r
+#define EFI_PAGE_NUMBER_4M (EFI_PDE_PAGE_NUM)\r
+\r
+//\r
+// Create 4M 4K-page table\r
+// PTE (21:12) : 1024 entries\r
+//\r
+#define EFI_PTE_ENTRY_NUM EFI_MAX_ENTRY_NUM\r
+#define EFI_PTE_PAGE_NUM 1\r
+\r
+#define EFI_PAGE_NUMBER_4K (EFI_PTE_PAGE_NUM)\r
+\r
+#define EFI_PAGE_NUMBER (EFI_PAGE_NUMBER_4M + EFI_PAGE_NUMBER_4K)\r
+\r
+VOID\r
+EnableNullPointerProtection (\r
+ UINT8 *PageTable\r
+ )\r
+{\r
+ IA32_PAGE_TABLE_ENTRY_4K *PageTableEntry4KB;\r
+\r
+ PageTableEntry4KB = (IA32_PAGE_TABLE_ENTRY_4K *)((UINTN)PageTable + EFI_PAGE_NUMBER_4M * EFI_PAGE_SIZE_4K);\r
+\r
+ //\r
+ // Fill in the Page Table entries\r
+ // Mark 0~4K as not present\r
+ //\r
+ PageTableEntry4KB->Bits.Present = 0;\r
+\r
+ return ;\r
+}\r
+\r
+VOID\r
+Ia32Create4KPageTables (\r
+ UINT8 *PageTable\r
+ )\r
+{\r
+ UINT64 PageAddress;\r
+ UINTN PTEIndex;\r
+ IA32_PAGE_DIRECTORY_ENTRY_4K *PageDirectoryEntry4KB;\r
+ IA32_PAGE_TABLE_ENTRY_4K *PageTableEntry4KB;\r
+\r
+ PageAddress = 0;\r
+\r
+ //\r
+ // Page Table structure 2 level 4K.\r
+ //\r
+ // Page Table 4K : PageDirectoryEntry4K : bits 31-22\r
+ // PageTableEntry : bits 21-12\r
+ //\r
+\r
+ PageTableEntry4KB = (IA32_PAGE_TABLE_ENTRY_4K *)((UINTN)PageTable + EFI_PAGE_NUMBER_4M * EFI_PAGE_SIZE_4K);\r
+ PageDirectoryEntry4KB = (IA32_PAGE_DIRECTORY_ENTRY_4K *)((UINTN)PageTable);\r
+\r
+ PageDirectoryEntry4KB->Uint32 = (UINT32)(UINTN)PageTableEntry4KB;\r
+ PageDirectoryEntry4KB->Bits.ReadWrite = 0;\r
+ PageDirectoryEntry4KB->Bits.Present = 1;\r
+ PageDirectoryEntry4KB->Bits.MustBeZero = 1;\r
+\r
+ for (PTEIndex = 0; PTEIndex < EFI_PTE_ENTRY_NUM; PTEIndex++, PageTableEntry4KB++) {\r
+ //\r
+ // Fill in the Page Table entries\r
+ //\r
+ PageTableEntry4KB->Uint32 = (UINT32)PageAddress;\r
+ PageTableEntry4KB->Bits.ReadWrite = 1;\r
+ PageTableEntry4KB->Bits.Present = 1;\r
+\r
+ PageAddress += EFI_PAGE_SIZE_4K;\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+VOID\r
+Ia32Create4MPageTables (\r
+ UINT8 *PageTable\r
+ )\r
+{\r
+ UINT32 PageAddress;\r
+ UINT8 *TempPageTable;\r
+ UINTN PDEIndex;\r
+ IA32_PAGE_TABLE_ENTRY_4M *PageDirectoryEntry4MB;\r
+\r
+ TempPageTable = PageTable;\r
+\r
+ PageAddress = 0;\r
+\r
+ //\r
+ // Page Table structure 1 level 4MB.\r
+ //\r
+ // Page Table 4MB : PageDirectoryEntry4M : bits 31-22\r
+ //\r
+\r
+ PageDirectoryEntry4MB = (IA32_PAGE_TABLE_ENTRY_4M *)TempPageTable;\r
+\r
+ for (PDEIndex = 0; PDEIndex < EFI_PDE_ENTRY_NUM; PDEIndex++, PageDirectoryEntry4MB++) {\r
+ //\r
+ // Fill in the Page Directory entries\r
+ //\r
+ PageDirectoryEntry4MB->Uint32 = (UINT32)PageAddress;\r
+ PageDirectoryEntry4MB->Bits.ReadWrite = 1;\r
+ PageDirectoryEntry4MB->Bits.Present = 1;\r
+ PageDirectoryEntry4MB->Bits.MustBe1 = 1;\r
+\r
+ PageAddress += EFI_PAGE_SIZE_4M;\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+VOID *\r
+PreparePageTable (\r
+ VOID *PageNumberTop,\r
+ UINT8 SizeOfMemorySpace \r
+ )\r
+/*++\r
+Description:\r
+ Generate pagetable below PageNumberTop, \r
+ and return the bottom address of pagetable for putting other things later.\r
+--*/\r
+{\r
+ VOID *PageNumberBase;\r
+\r
+ PageNumberBase = (VOID *)((UINTN)PageNumberTop - EFI_PAGE_NUMBER * EFI_PAGE_SIZE_4K);\r
+ ZeroMem (PageNumberBase, EFI_PAGE_NUMBER * EFI_PAGE_SIZE_4K);\r
+\r
+ Ia32Create4MPageTables (PageNumberBase);\r
+ Ia32Create4KPageTables (PageNumberBase);\r
+ //\r
+ // Not enable NULL Pointer Protection if using INTX call\r
+ //\r
+// EnableNullPointerProtection (PageNumberBase);\r
+\r
+ return PageNumberBase;\r
+}\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ VirtualMemory.h\r
+\r
+Abstract:\r
+\r
+Revision History:\r
+\r
+--*/\r
+ \r
+#ifndef _VIRTUAL_MEMORY_H_\r
+#define _VIRTUAL_MEMORY_H_\r
+\r
+#pragma pack(1)\r
+\r
+//\r
+// Page Directory Entry 4K\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT32 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
+ UINT32 UserSupervisor:1; // 0 = Supervisor, 1=User\r
+ UINT32 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT32 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
+ UINT32 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+ UINT32 MustBeZero:3; // Must Be Zero\r
+ UINT32 Available:3; // Available for use by system software\r
+ UINT32 PageTableBaseAddress:20; // Page Table Base Address\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} IA32_PAGE_DIRECTORY_ENTRY_4K;\r
+\r
+//\r
+// Page Table Entry 4K\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 Present:1; // 0 = Not present in memory, 1 = Present in memory \r
+ UINT32 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
+ UINT32 UserSupervisor:1; // 0 = Supervisor, 1=User\r
+ UINT32 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT32 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
+ UINT32 Accessed:1; // 0 = Not accessed (cleared by software), 1 = Accessed (set by CPU)\r
+ UINT32 Dirty:1; // 0 = Not written to (cleared by software), 1 = Written to (set by CPU)\r
+ UINT32 PAT:1; // 0 = Disable PAT, 1 = Enable PAT\r
+ UINT32 Global:1; // Ignored\r
+ UINT32 Available:3; // Available for use by system software\r
+ UINT32 PageTableBaseAddress:20; // Page Table Base Address\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} IA32_PAGE_TABLE_ENTRY_4K;\r
+\r
+//\r
+// Page Table Entry 4M\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT32 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
+ UINT32 UserSupervisor:1; // 0 = Supervisor, 1=User\r
+ UINT32 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT32 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
+ UINT32 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+ UINT32 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
+ UINT32 MustBe1:1; // Must be 1 \r
+ UINT32 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
+ UINT32 Available:3; // Available for use by system software\r
+ UINT32 PAT:1; //\r
+ UINT32 MustBeZero:9; // Must be zero;\r
+ UINT32 PageTableBaseAddress:10; // Page Table Base Address\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} IA32_PAGE_TABLE_ENTRY_4M;\r
+\r
+#pragma pack()\r
+\r
+#endif \r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ LegacyTable.c\r
+\r
+Abstract:\r
+\r
+Revision History:\r
+\r
+--*/\r
+\r
+#include "DxeIpl.h"\r
+#include "HobGeneration.h"\r
+\r
+#define ACPI_RSD_PTR 0x2052545020445352\r
+#define MPS_PTR EFI_SIGNATURE_32('_','M','P','_')\r
+#define SMBIOS_PTR EFI_SIGNATURE_32('_','S','M','_')\r
+\r
+#define EBDA_BASE_ADDRESS 0x40E\r
+\r
+VOID *\r
+FindAcpiRsdPtr (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Address;\r
+ UINTN Index;\r
+\r
+ //\r
+ // First Seach 0x0e0000 - 0x0fffff for RSD Ptr\r
+ //\r
+ for (Address = 0xe0000; Address < 0xfffff; Address += 0x10) {\r
+ if (*(UINT64 *)(Address) == ACPI_RSD_PTR) {\r
+ return (VOID *)Address;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Search EBDA\r
+ //\r
+\r
+ Address = (*(UINT16 *)(UINTN)(EBDA_BASE_ADDRESS)) << 4;\r
+ for (Index = 0; Index < 0x400 ; Index += 16) {\r
+ if (*(UINT64 *)(Address + Index) == ACPI_RSD_PTR) {\r
+ return (VOID *)Address;\r
+ }\r
+ }\r
+ return NULL;\r
+}\r
+\r
+VOID *\r
+FindSMBIOSPtr (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Address;\r
+\r
+ //\r
+ // First Seach 0x0f0000 - 0x0fffff for SMBIOS Ptr\r
+ //\r
+ for (Address = 0xf0000; Address < 0xfffff; Address += 0x10) {\r
+ if (*(UINT32 *)(Address) == SMBIOS_PTR) {\r
+ return (VOID *)Address;\r
+ }\r
+ }\r
+ return NULL;\r
+}\r
+\r
+VOID *\r
+FindMPSPtr (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Address;\r
+ UINTN Index;\r
+\r
+ //\r
+ // First Seach 0x0e0000 - 0x0fffff for MPS Ptr\r
+ //\r
+ for (Address = 0xe0000; Address < 0xfffff; Address += 0x10) {\r
+ if (*(UINT32 *)(Address) == MPS_PTR) {\r
+ return (VOID *)Address;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Search EBDA\r
+ //\r
+\r
+ Address = (*(UINT16 *)(UINTN)(EBDA_BASE_ADDRESS)) << 4;\r
+ for (Index = 0; Index < 0x400 ; Index += 16) {\r
+ if (*(UINT32 *)(Address + Index) == MPS_PTR) {\r
+ return (VOID *)Address;\r
+ }\r
+ }\r
+ return NULL;\r
+}\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+ UINT8 Signature[8];\r
+ UINT8 Checksum;\r
+ UINT8 OemId[6];\r
+ UINT8 Revision;\r
+ UINT32 RsdtAddress;\r
+ UINT32 Length;\r
+ UINT64 XsdtAddress;\r
+ UINT8 ExtendedChecksum;\r
+ UINT8 Reserved[3];\r
+} RSDP_TABLE;\r
+\r
+typedef struct {\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
+ UINT8 Revision;\r
+ UINT8 Checksum;\r
+ UINT8 OemId[6];\r
+ UINT8 OemTableId[8];\r
+ UINT32 OemRevision;\r
+ UINT8 CreatorId[4];\r
+ UINT32 CreatorRevision;\r
+} DESCRIPTION_HEADER;\r
+\r
+typedef struct {\r
+ DESCRIPTION_HEADER Header;\r
+ UINT32 Entry;\r
+} RSDT_TABLE;\r
+\r
+typedef struct {\r
+ DESCRIPTION_HEADER Header;\r
+ UINT64 Entry;\r
+} XSDT_TABLE;\r
+\r
+typedef struct {\r
+ UINT8 Address_Space_ID;\r
+ UINT8 Register_Bit_Width;\r
+ UINT8 Register_Bit_Offset;\r
+ UINT8 Access_Size;\r
+ UINT64 Address;\r
+} GADDRESS_STRUCTURE;\r
+\r
+#pragma pack()\r
+\r
+VOID\r
+ScanTableInRSDT (\r
+ RSDT_TABLE *Rsdt,\r
+ UINT32 Signature,\r
+ DESCRIPTION_HEADER **FoundTable\r
+ )\r
+{\r
+ UINTN Index;\r
+ UINT32 EntryCount;\r
+ UINT32 *EntryPtr;\r
+ DESCRIPTION_HEADER *Table;\r
+ \r
+ *FoundTable = NULL;\r
+ \r
+ EntryCount = (Rsdt->Header.Length - sizeof (DESCRIPTION_HEADER)) / sizeof(UINT32);\r
+ \r
+ EntryPtr = &Rsdt->Entry;\r
+ for (Index = 0; Index < EntryCount; Index ++, EntryPtr ++) {\r
+ Table = (DESCRIPTION_HEADER*)((UINTN)(*EntryPtr));\r
+ if (Table->Signature == Signature) {\r
+ *FoundTable = Table;\r
+ break;\r
+ }\r
+ }\r
+ \r
+ return;\r
+}\r
+\r
+VOID\r
+ScanTableInXSDT (\r
+ XSDT_TABLE *Xsdt,\r
+ UINT32 Signature,\r
+ DESCRIPTION_HEADER **FoundTable\r
+ )\r
+{\r
+ UINTN Index;\r
+ UINT32 EntryCount;\r
+ UINT64 EntryPtr;\r
+ UINTN BasePtr;\r
+ \r
+ DESCRIPTION_HEADER *Table;\r
+ \r
+ *FoundTable = NULL;\r
+ \r
+ EntryCount = (Xsdt->Header.Length - sizeof (DESCRIPTION_HEADER)) / sizeof(UINT64);\r
+ \r
+ BasePtr = (UINTN)(&(Xsdt->Entry));\r
+ for (Index = 0; Index < EntryCount; Index ++) {\r
+ CopyMem (&EntryPtr, (VOID *)(BasePtr + Index * sizeof(UINT64)), sizeof(UINT64));\r
+ Table = (DESCRIPTION_HEADER*)((UINTN)(EntryPtr));\r
+ if (Table->Signature == Signature) {\r
+ *FoundTable = Table;\r
+ break;\r
+ }\r
+ }\r
+ \r
+ return;\r
+}\r
+\r
+VOID *\r
+FindAcpiPtr (\r
+ IN HOB_TEMPLATE *Hob,\r
+ UINT32 Signature\r
+ )\r
+{\r
+ DESCRIPTION_HEADER *AcpiTable;\r
+ RSDP_TABLE *Rsdp;\r
+ RSDT_TABLE *Rsdt;\r
+ XSDT_TABLE *Xsdt;\r
+ \r
+ AcpiTable = NULL;\r
+\r
+ //\r
+ // Check ACPI2.0 table\r
+ //\r
+ if (Hob->Acpi20.Table > 0) {\r
+ Rsdp = (RSDP_TABLE *)(UINTN)Hob->Acpi20.Table;\r
+ Rsdt = (RSDT_TABLE *)(UINTN)Rsdp->RsdtAddress;\r
+ Xsdt = NULL;\r
+ if ((Rsdp->Revision >= 2) && (Rsdp->XsdtAddress < (UINT64)(UINTN)-1)) {\r
+ Xsdt = (XSDT_TABLE *)(UINTN)Rsdp->XsdtAddress;\r
+ }\r
+ //\r
+ // Check Xsdt\r
+ //\r
+ if (Xsdt != NULL) {\r
+ ScanTableInXSDT (Xsdt, Signature, &AcpiTable);\r
+ }\r
+ //\r
+ // Check Rsdt\r
+ //\r
+ if ((AcpiTable == NULL) && (Rsdt != NULL)) {\r
+ ScanTableInRSDT (Rsdt, Signature, &AcpiTable);\r
+ }\r
+ }\r
+ \r
+ //\r
+ // Check ACPI1.0 table\r
+ //\r
+ if ((AcpiTable == NULL) && (Hob->Acpi.Table > 0)) {\r
+ Rsdp = (RSDP_TABLE *)(UINTN)Hob->Acpi.Table;\r
+ Rsdt = (RSDT_TABLE *)(UINTN)Rsdp->RsdtAddress;\r
+ //\r
+ // Check Rsdt\r
+ //\r
+ if (Rsdt != NULL) {\r
+ ScanTableInRSDT (Rsdt, Signature, &AcpiTable);\r
+ }\r
+ }\r
+\r
+ return AcpiTable;\r
+}\r
+\r
+#pragma pack(1)\r
+//#define MCFG_SIGNATURE 0x4746434D\r
+#define MCFG_SIGNATURE EFI_SIGNATURE_32 ('M', 'C', 'F', 'G')\r
+typedef struct {\r
+ UINT64 BaseAddress;\r
+ UINT16 PciSegmentGroupNumber;\r
+ UINT8 StartBusNumber;\r
+ UINT8 EndBusNumber;\r
+ UINT32 Reserved;\r
+} MCFG_STRUCTURE;\r
+\r
+#define FADT_SIGNATURE EFI_SIGNATURE_32 ('F', 'A', 'C', 'P')\r
+typedef struct {\r
+ DESCRIPTION_HEADER Header;\r
+ UINT32 FIRMWARE_CTRL;\r
+ UINT32 DSDT;\r
+ UINT8 INT_MODEL;\r
+ UINT8 Preferred_PM_Profile;\r
+ UINT16 SCI_INIT;\r
+ UINT32 SMI_CMD;\r
+ UINT8 ACPI_ENABLE;\r
+ UINT8 ACPI_DISABLE;\r
+ UINT8 S4BIOS_REQ;\r
+ UINT8 PSTATE_CNT;\r
+ UINT32 PM1a_EVT_BLK;\r
+ UINT32 PM1b_EVT_BLK;\r
+ UINT32 PM1a_CNT_BLK;\r
+ UINT32 PM1b_CNT_BLK;\r
+ UINT32 PM2_CNT_BLK;\r
+ UINT32 PM_TMR_BLK;\r
+ UINT32 GPE0_BLK;\r
+ UINT32 GPE1_BLK;\r
+ UINT8 PM1_EVT_LEN;\r
+ UINT8 PM1_CNT_LEN;\r
+ UINT8 PM2_CNT_LEN;\r
+ UINT8 PM_TMR_LEN;\r
+ UINT8 GPE0_BLK_LEN;\r
+ UINT8 GPE1_BLK_LEN;\r
+ UINT8 GPE1_BASE;\r
+ UINT8 CST_CNT;\r
+ UINT16 P_LVL2_LAT;\r
+ UINT16 P_LVL3_LAT;\r
+ UINT16 FLUSH_SIZE;\r
+ UINT16 FLUSH_STRIDE;\r
+ UINT8 DUTY_OFFSET;\r
+ UINT8 DUTY_WIDTH;\r
+ UINT8 DAY_ALARM;\r
+ UINT8 MON_ALARM;\r
+ UINT8 CENTRY;\r
+ UINT16 IAPC_BOOT_ARCH;\r
+ UINT8 Reserved_111;\r
+ UINT32 Flags;\r
+ GADDRESS_STRUCTURE RESET_REG;\r
+ UINT8 RESET_VALUE;\r
+ UINT8 Reserved_129[3];\r
+ UINT64 X_FIRMWARE_CTRL;\r
+ UINT64 X_DSDT;\r
+ GADDRESS_STRUCTURE X_PM1a_EVT_BLK;\r
+ GADDRESS_STRUCTURE X_PM1b_EVT_BLK;\r
+ GADDRESS_STRUCTURE X_PM1a_CNT_BLK;\r
+ GADDRESS_STRUCTURE X_PM1b_CNT_BLK;\r
+ GADDRESS_STRUCTURE X_PM2_CNT_BLK;\r
+ GADDRESS_STRUCTURE X_PM_TMR_BLK;\r
+ GADDRESS_STRUCTURE X_GPE0_BLK;\r
+ GADDRESS_STRUCTURE X_GPE1_BLK;\r
+} FADT_TABLE;\r
+\r
+#pragma pack()\r
+\r
+VOID\r
+PrepareMcfgTable (\r
+ IN HOB_TEMPLATE *Hob\r
+ )\r
+{\r
+ DESCRIPTION_HEADER *McfgTable;\r
+ MCFG_STRUCTURE *Mcfg;\r
+ UINTN McfgCount;\r
+ UINTN Index;\r
+\r
+ McfgTable = FindAcpiPtr (Hob, MCFG_SIGNATURE);\r
+ if (McfgTable == NULL) {\r
+ return ;\r
+ }\r
+\r
+ Mcfg = (MCFG_STRUCTURE *)((UINTN)McfgTable + sizeof(DESCRIPTION_HEADER) + sizeof(UINT64));\r
+ McfgCount = (McfgTable->Length - sizeof(DESCRIPTION_HEADER) - sizeof(UINT64)) / sizeof(MCFG_STRUCTURE);\r
+\r
+ //\r
+ // Fill PciExpress info on Hob\r
+ // Note: Only for 1st segment\r
+ //\r
+ for (Index = 0; Index < McfgCount; Index++) {\r
+ if (Mcfg[Index].PciSegmentGroupNumber == 0) {\r
+ Hob->PciExpress.PciExpressBaseAddressInfo.PciExpressBaseAddress = Mcfg[Index].BaseAddress;\r
+ break;\r
+ }\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+VOID\r
+PrepareFadtTable (\r
+ IN HOB_TEMPLATE *Hob\r
+ )\r
+{\r
+ FADT_TABLE *Fadt;\r
+ EFI_ACPI_DESCRIPTION *AcpiDescription;\r
+\r
+ Fadt = FindAcpiPtr (Hob, FADT_SIGNATURE);\r
+ if (Fadt == NULL) {\r
+ return ;\r
+ }\r
+\r
+ AcpiDescription = &Hob->AcpiInfo.AcpiDescription;\r
+ //\r
+ // Fill AcpiDescription according to FADT\r
+ // Currently, only for PM_TMR\r
+ //\r
+ AcpiDescription->PM_TMR_LEN = Fadt->PM_TMR_LEN;\r
+ AcpiDescription->TMR_VAL_EXT = (UINT8)((Fadt->Flags & 0x100) != 0);\r
+ if ((Fadt->Header.Revision >= 3) && (Fadt->Header.Length >= sizeof(FADT_TABLE))) {\r
+ CopyMem (\r
+ &AcpiDescription->PM_TMR_BLK,\r
+ &Fadt->X_PM_TMR_BLK,\r
+ sizeof(GADDRESS_STRUCTURE)\r
+ );\r
+ CopyMem (\r
+ &AcpiDescription->RESET_REG,\r
+ &Fadt->RESET_REG,\r
+ sizeof(GADDRESS_STRUCTURE)\r
+ );\r
+ AcpiDescription->RESET_VALUE = Fadt->RESET_VALUE;\r
+ }\r
+ if (AcpiDescription->PM_TMR_BLK.Address == 0) {\r
+ AcpiDescription->PM_TMR_BLK.Address = Fadt->PM_TMR_BLK;\r
+ AcpiDescription->PM_TMR_BLK.AddressSpaceId = ACPI_ADDRESS_ID_IO;\r
+ AcpiDescription->PM_TMR_BLK.RegisterBitWidth = (AcpiDescription->TMR_VAL_EXT == 0) ? 24 : 32;\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+VOID\r
+PrepareHobLegacyTable (\r
+ IN HOB_TEMPLATE *Hob\r
+ )\r
+{\r
+ Hob->Acpi.Table = (EFI_PHYSICAL_ADDRESS)(UINTN)FindAcpiRsdPtr ();\r
+ Hob->Acpi20.Table = (EFI_PHYSICAL_ADDRESS)(UINTN)FindAcpiRsdPtr ();\r
+ Hob->Smbios.Table = (EFI_PHYSICAL_ADDRESS)(UINTN)FindSMBIOSPtr ();\r
+ Hob->Mps.Table = (EFI_PHYSICAL_ADDRESS)(UINTN)FindMPSPtr ();\r
+\r
+ PrepareMcfgTable (Hob);\r
+\r
+ PrepareFadtTable (Hob);\r
+\r
+ return ;\r
+}\r
+\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ LegacyTable.h\r
+\r
+Abstract:\r
+\r
+Revision History:\r
+\r
+--*/\r
+\r
+#ifndef _DXELDR_LEGACY_TABLE_H_\r
+#define _DXELDR_LEGACY_TABLE_H_\r
+\r
+#include "HobGeneration.h"\r
+\r
+VOID\r
+PrepareHobLegacyTable (\r
+ IN HOB_TEMPLATE *Hob\r
+ );\r
+\r
+#endif\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ PpisNeededByDxeCore.c\r
+\r
+Abstract:\r
+ \r
+Revision History:\r
+\r
+--*/\r
+\r
+#include "PpisNeededByDxeCore.h"\r
+#include "HobGeneration.h"\r
+#include "SerialStatusCode.h"\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PreparePpisNeededByDxeCore (\r
+ IN HOB_TEMPLATE *Hob\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ This routine adds the PPI/Protocol Hobs that are consumed by the DXE Core.\r
+ Normally these come from PEI, but since our PEI was 32-bit we need an\r
+ alternate source. That is this driver.\r
+\r
+ This driver does not consume PEI or DXE services and thus updates the \r
+ Phit (HOB list) directly\r
+\r
+Arguments:\r
+\r
+ HobStart - Pointer to the beginning of the HOB List from PEI\r
+\r
+Returns:\r
+\r
+ This function should after it has add it's HOBs\r
+\r
+--*/\r
+{\r
+ //EFI_PEI_PE_COFF_LOADER_PROTOCOL *PeCoffLoader;\r
+ //EFI_DECOMPRESS_PROTOCOL *EfiDecompress;\r
+ //EFI_TIANO_DECOMPRESS_PROTOCOL *TianoDecompress;\r
+ EFI_REPORT_STATUS_CODE ReportStatusCode;\r
+\r
+ //InstallEfiPeiFlushInstructionCache (&FlushInstructionCache);\r
+ //Hob->FlushInstructionCache.Interface = FlushInstructionCache;\r
+\r
+ // R9 do not need this protocol.\r
+ // InstallEfiPeiTransferControl (&TransferControl);\r
+ // Hob->TransferControl.Interface = TransferControl;\r
+\r
+ //InstallEfiPeiPeCoffLoader (NULL, &PeCoffLoader, NULL);\r
+ //Hob->PeCoffLoader.Interface = PeCoffLoader;\r
+\r
+ //InstallEfiDecompress (&EfiDecompress);\r
+ //Hob->EfiDecompress.Interface = EfiDecompress;\r
+\r
+ //InstallTianoDecompress (&TianoDecompress);\r
+ //Hob->TianoDecompress.Interface = TianoDecompress;\r
+\r
+ InstallSerialStatusCode (&ReportStatusCode);\r
+ Hob->SerialStatusCode.Interface = (VOID *)(UINTN)ReportStatusCode;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ PpisNeededByDxeCore.h\r
+\r
+Abstract:\r
+ \r
+Revision History:\r
+\r
+--*/\r
+\r
+#ifndef _DXELDR_PPIS_NEEDED_BY_DXE_CORE_H_\r
+#define _DXELDR_PPIS_NEEDED_BY_DXE_CORE_H_\r
+\r
+#include "DxeIpl.h"\r
+#include "HobGeneration.h"\r
+\r
+//EFI_STATUS\r
+//InstallEfiPeiTransferControl (\r
+// IN OUT EFI_PEI_TRANSFER_CONTROL_PROTOCOL **This\r
+// );\r
+\r
+//EFI_STATUS\r
+//InstallEfiPeiFlushInstructionCache (\r
+// IN OUT EFI_PEI_FLUSH_INSTRUCTION_CACHE_PROTOCOL **This\r
+// );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PreparePpisNeededByDxeCore (\r
+ IN HOB_TEMPLATE *HobStart\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ This routine adds the PPI/Protocol Hobs that are consumed by the DXE Core.\r
+ Normally these come from PEI, but since our PEI was 32-bit we need an\r
+ alternate source. That is this driver.\r
+\r
+ This driver does not consume PEI or DXE services and thus updates the \r
+ Phit (HOB list) directly\r
+\r
+Arguments:\r
+\r
+ HobStart - Pointer to the beginning of the HOB List from PEI\r
+\r
+Returns:\r
+\r
+ This function should after it has add it's HOBs\r
+\r
+--*/\r
+;\r
+\r
+#endif\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ SerialStatusCode.c\r
+\r
+Abstract:\r
+\r
+Revision History:\r
+\r
+--*/\r
+\r
+#include "SerialStatusCode.h"\r
+\r
+\r
+UINT16 gComBase = 0x3f8;\r
+UINTN gBps = 115200;\r
+UINT8 gData = 8;\r
+UINT8 gStop = 1;\r
+UINT8 gParity = 0;\r
+UINT8 gBreakSet = 0;\r
+\r
+//\r
+// All of the lookup tables are only needed in debug.\r
+//\r
+\r
+typedef struct {\r
+ UINT32 Value;\r
+ CHAR8 *Token;\r
+} STATUS_CODE_LOOKUP_TABLE;\r
+\r
+STATUS_CODE_LOOKUP_TABLE mSeverityToken[] = {\r
+ { EFI_ERROR_MINOR, "ERROR_MINOR" },\r
+ { EFI_ERROR_MAJOR, "ERROR_MAJOR" },\r
+ { EFI_ERROR_UNRECOVERED, "ERROR_UNRECOVERED" },\r
+ { EFI_ERROR_UNCONTAINED, "ERROR_UNCONTAINED" },\r
+ { 0xFFFFFFFF, "ERROR_UNRECOGNIZED" }\r
+ };\r
+\r
+STATUS_CODE_LOOKUP_TABLE mClassSubClassToken[] = {\r
+ { EFI_COMPUTING_UNIT_UNSPECIFIED, "COMPUTING_UNIT_UNSPECIFIED" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR, "COMPUTING_UNIT_HOST_PROCESSOR" },\r
+ { EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR, "COMPUTING_UNIT_FIRMWARE_PROCESSOR" },\r
+ { EFI_COMPUTING_UNIT_IO_PROCESSOR, "COMPUTING_UNIT_IO_PROCESSOR" },\r
+ { EFI_COMPUTING_UNIT_CACHE, "COMPUTING_UNIT_CACHE" },\r
+ { EFI_COMPUTING_UNIT_MEMORY, "COMPUTING_UNIT_MEMORY" },\r
+ { EFI_COMPUTING_UNIT_CHIPSET, "COMPUTING_UNIT_CHIPSET" },\r
+ { EFI_PERIPHERAL_UNSPECIFIED, "PERIPHERAL_UNSPECIFIED" },\r
+ { EFI_PERIPHERAL_KEYBOARD, "PERIPHERAL_KEYBOARD" },\r
+ { EFI_PERIPHERAL_MOUSE, "PERIPHERAL_MOUSE" },\r
+ { EFI_PERIPHERAL_LOCAL_CONSOLE, "PERIPHERAL_LOCAL_CONSOLE" },\r
+ { EFI_PERIPHERAL_REMOTE_CONSOLE, "PERIPHERAL_REMOTE_CONSOLE" },\r
+ { EFI_PERIPHERAL_SERIAL_PORT, "PERIPHERAL_SERIAL_PORT" },\r
+ { EFI_PERIPHERAL_PARALLEL_PORT, "PERIPHERAL_PARALLEL_PORT" },\r
+ { EFI_PERIPHERAL_FIXED_MEDIA, "PERIPHERAL_FIXED_MEDIA" },\r
+ { EFI_PERIPHERAL_REMOVABLE_MEDIA, "PERIPHERAL_REMOVABLE_MEDIA" },\r
+ { EFI_PERIPHERAL_AUDIO_INPUT, "PERIPHERAL_AUDIO_INPUT" },\r
+ { EFI_PERIPHERAL_AUDIO_OUTPUT, "PERIPHERAL_AUDIO_OUTPUT" },\r
+ { EFI_PERIPHERAL_LCD_DEVICE, "PERIPHERAL_LCD_DEVICE" },\r
+ { EFI_IO_BUS_UNSPECIFIED, "IO_BUS_UNSPECIFIED" },\r
+ { EFI_IO_BUS_PCI, "IO_BUS_PCI" },\r
+ { EFI_IO_BUS_USB, "IO_BUS_USB" },\r
+ { EFI_IO_BUS_IBA, "IO_BUS_IBA" },\r
+ { EFI_IO_BUS_AGP, "IO_BUS_AGP" },\r
+ { EFI_IO_BUS_PC_CARD, "IO_BUS_PC_CARD" },\r
+ { EFI_IO_BUS_LPC, "IO_BUS_LPC" },\r
+ { EFI_IO_BUS_SCSI, "IO_BUS_SCSI" },\r
+ { EFI_IO_BUS_ATA_ATAPI, "IO_BUS_ATA_ATAPI" },\r
+ { EFI_IO_BUS_FC, "IO_BUS_FC" },\r
+ { EFI_IO_BUS_IP_NETWORK, "IO_BUS_IP_NETWORK" },\r
+ { EFI_IO_BUS_SMBUS, "IO_BUS_SMBUS" },\r
+ { EFI_IO_BUS_I2C, "IO_BUS_I2C" },\r
+ { EFI_SOFTWARE_UNSPECIFIED, "SOFTWARE_UNSPECIFIED" },\r
+ { EFI_SOFTWARE_SEC, "SOFTWARE_SEC" },\r
+ { EFI_SOFTWARE_PEI_CORE, "SOFTWARE_PEI_CORE" },\r
+ { EFI_SOFTWARE_PEI_MODULE, "SOFTWARE_PEI_MODULE" },\r
+ { EFI_SOFTWARE_DXE_CORE, "SOFTWARE_DXE_CORE" },\r
+ { EFI_SOFTWARE_EFI_BOOT_SERVICE, "SOFTWARE_EFI_BOOT_SERVICE" },\r
+ { EFI_SOFTWARE_EFI_RUNTIME_SERVICE, "SOFTWARE_EFI_RUNTIME_SERVICE" },\r
+ { EFI_SOFTWARE_DXE_BS_DRIVER, "SOFTWARE_DXE_BS_DRIVER" },\r
+ { EFI_SOFTWARE_DXE_RT_DRIVER, "SOFTWARE_DXE_RT_DRIVER" },\r
+ { EFI_SOFTWARE_SMM_DRIVER, "SOFTWARE_SMM_DRIVER" },\r
+ { EFI_SOFTWARE_RT, "SOFTWARE_EFI_RT" },\r
+ { EFI_SOFTWARE_AL, "SOFTWARE_EFI_AL" },\r
+ { EFI_SOFTWARE_EFI_APPLICATION, "SOFTWARE_EFI_APPLICATION" },\r
+ { EFI_SOFTWARE_EFI_OS_LOADER, "SOFTWARE_EFI_OS_LOADER" },\r
+ { 0xFFFFFFFF, "ERROR_UNRECOGNIZED" }\r
+ };\r
+\r
+STATUS_CODE_LOOKUP_TABLE mOperationToken[] = {\r
+ { EFI_COMPUTING_UNIT_UNSPECIFIED | EFI_CU_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_COMPUTING_UNIT_UNSPECIFIED | EFI_CU_EC_DISABLED, "DISABLED" },\r
+ { EFI_COMPUTING_UNIT_UNSPECIFIED | EFI_CU_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_COMPUTING_UNIT_UNSPECIFIED | EFI_CU_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_COMPUTING_UNIT_UNSPECIFIED | EFI_CU_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_EC_DISABLED, "DISABLED" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_INVALID_TYPE, "INVALID_TYPE" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_INVALID_SPEED, "INVALID_SPEED" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_MISMATCH, "MISMATCH" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_TIMER_EXPIRED, "TIMER_EXPIRED" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_SELF_TEST, "SELF_TEST" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_INTERNAL, "INTERNAL" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_THERMAL, "THERMAL" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_LOW_VOLTAGE, "LOW_VOLTAGE" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_HIGH_VOLTAGE, "HIGH_VOLTAGE" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_CACHE, "CACHE" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_MICROCODE_UPDATE, "MICROCODE_UPDATE" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_NO_MICROCODE_UPDATE, "NO_MICROCODE_UPDATE" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_CORRECTABLE, "1XECC" },\r
+ { EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_UNCORRECTABLE, "2XECC" },\r
+ { EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR | EFI_CU_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR | EFI_CU_EC_DISABLED, "DISABLED" },\r
+ { EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR | EFI_CU_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR | EFI_CU_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR | EFI_CU_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_COMPUTING_UNIT_IO_PROCESSOR | EFI_CU_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_COMPUTING_UNIT_IO_PROCESSOR | EFI_CU_EC_DISABLED, "DISABLED" },\r
+ { EFI_COMPUTING_UNIT_IO_PROCESSOR | EFI_CU_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_COMPUTING_UNIT_IO_PROCESSOR | EFI_CU_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_COMPUTING_UNIT_IO_PROCESSOR | EFI_CU_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_COMPUTING_UNIT_CACHE | EFI_CU_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_COMPUTING_UNIT_CACHE | EFI_CU_EC_DISABLED, "DISABLED" },\r
+ { EFI_COMPUTING_UNIT_CACHE | EFI_CU_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_COMPUTING_UNIT_CACHE | EFI_CU_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_COMPUTING_UNIT_CACHE | EFI_CU_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_COMPUTING_UNIT_CACHE | EFI_CU_CACHE_EC_INVALID_TYPE, "INVALID_TYPE" },\r
+ { EFI_COMPUTING_UNIT_CACHE | EFI_CU_CACHE_EC_INVALID_SPEED, "INVALID_SPEED" },\r
+ { EFI_COMPUTING_UNIT_CACHE | EFI_CU_CACHE_EC_INVALID_SIZE, "INVALID_SIZE" },\r
+ { EFI_COMPUTING_UNIT_MEMORY | EFI_CU_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_COMPUTING_UNIT_MEMORY | EFI_CU_EC_DISABLED, "DISABLED" },\r
+ { EFI_COMPUTING_UNIT_MEMORY | EFI_CU_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_COMPUTING_UNIT_MEMORY | EFI_CU_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_COMPUTING_UNIT_MEMORY | EFI_CU_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_EC_INVALID_TYPE, "INVALID_TYPE" },\r
+ { EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_EC_INVALID_SPEED, "INVALID_SPEED" },\r
+ { EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_EC_CORRECTABLE, "1XECC" },\r
+ { EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_EC_UNCORRECTABLE, "2XECC" },\r
+ { EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_EC_SPD_FAIL, "SPD_FAIL" },\r
+ { EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_EC_INVALID_SIZE, "INVALID_SIZE" },\r
+ { EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_EC_MISMATCH, "MISMATCH" },\r
+ { EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_EC_S3_RESUME_FAIL, "S3_RESUME_FAIL" },\r
+ { EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_EC_UPDATE_FAIL, "UPDATE_FAIL" },\r
+ { EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_EC_DISABLED, "DISABLED" },\r
+ { EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_PERIPHERAL_UNSPECIFIED | EFI_P_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_PERIPHERAL_UNSPECIFIED | EFI_P_EC_DISABLED, "DISABLED" },\r
+ { EFI_PERIPHERAL_UNSPECIFIED | EFI_P_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_PERIPHERAL_UNSPECIFIED | EFI_P_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_PERIPHERAL_UNSPECIFIED | EFI_P_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_PERIPHERAL_UNSPECIFIED | EFI_P_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_PERIPHERAL_UNSPECIFIED | EFI_P_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_PERIPHERAL_UNSPECIFIED | EFI_P_EC_INPUT_ERROR, "INPUT_ERROR" },\r
+ { EFI_PERIPHERAL_UNSPECIFIED | EFI_P_EC_OUTPUT_ERROR, "OUTPUT_ERROR" },\r
+ { EFI_PERIPHERAL_UNSPECIFIED | EFI_P_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_PERIPHERAL_KEYBOARD | EFI_P_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_PERIPHERAL_KEYBOARD | EFI_P_EC_DISABLED, "DISABLED" },\r
+ { EFI_PERIPHERAL_KEYBOARD | EFI_P_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_PERIPHERAL_KEYBOARD | EFI_P_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_PERIPHERAL_KEYBOARD | EFI_P_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_PERIPHERAL_KEYBOARD | EFI_P_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_PERIPHERAL_KEYBOARD | EFI_P_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_PERIPHERAL_KEYBOARD | EFI_P_EC_INPUT_ERROR, "INPUT_ERROR" },\r
+ { EFI_PERIPHERAL_KEYBOARD | EFI_P_EC_OUTPUT_ERROR, "OUTPUT_ERROR" },\r
+ { EFI_PERIPHERAL_KEYBOARD | EFI_P_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_PERIPHERAL_KEYBOARD | EFI_P_KEYBOARD_EC_LOCKED, "LOCKED" },\r
+ { EFI_PERIPHERAL_KEYBOARD | EFI_P_KEYBOARD_EC_STUCK_KEY, "STUCK_KEY" },\r
+ { EFI_PERIPHERAL_MOUSE | EFI_P_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_PERIPHERAL_MOUSE | EFI_P_EC_DISABLED, "DISABLED" },\r
+ { EFI_PERIPHERAL_MOUSE | EFI_P_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_PERIPHERAL_MOUSE | EFI_P_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_PERIPHERAL_MOUSE | EFI_P_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_PERIPHERAL_MOUSE | EFI_P_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_PERIPHERAL_MOUSE | EFI_P_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_PERIPHERAL_MOUSE | EFI_P_EC_INPUT_ERROR, "INPUT_ERROR" },\r
+ { EFI_PERIPHERAL_MOUSE | EFI_P_EC_OUTPUT_ERROR, "OUTPUT_ERROR" },\r
+ { EFI_PERIPHERAL_MOUSE | EFI_P_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_PERIPHERAL_MOUSE | EFI_P_MOUSE_EC_LOCKED, "LOCKED" },\r
+ { EFI_PERIPHERAL_LOCAL_CONSOLE | EFI_P_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_PERIPHERAL_LOCAL_CONSOLE | EFI_P_EC_DISABLED, "DISABLED" },\r
+ { EFI_PERIPHERAL_LOCAL_CONSOLE | EFI_P_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_PERIPHERAL_LOCAL_CONSOLE | EFI_P_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_PERIPHERAL_LOCAL_CONSOLE | EFI_P_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_PERIPHERAL_LOCAL_CONSOLE | EFI_P_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_PERIPHERAL_LOCAL_CONSOLE | EFI_P_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_PERIPHERAL_LOCAL_CONSOLE | EFI_P_EC_INPUT_ERROR, "INPUT_ERROR" },\r
+ { EFI_PERIPHERAL_LOCAL_CONSOLE | EFI_P_EC_OUTPUT_ERROR, "OUTPUT_ERROR" },\r
+ { EFI_PERIPHERAL_LOCAL_CONSOLE | EFI_P_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_PERIPHERAL_REMOTE_CONSOLE | EFI_P_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_PERIPHERAL_REMOTE_CONSOLE | EFI_P_EC_DISABLED, "DISABLED" },\r
+ { EFI_PERIPHERAL_REMOTE_CONSOLE | EFI_P_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_PERIPHERAL_REMOTE_CONSOLE | EFI_P_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_PERIPHERAL_REMOTE_CONSOLE | EFI_P_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_PERIPHERAL_REMOTE_CONSOLE | EFI_P_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_PERIPHERAL_REMOTE_CONSOLE | EFI_P_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_PERIPHERAL_REMOTE_CONSOLE | EFI_P_EC_INPUT_ERROR, "INPUT_ERROR" },\r
+ { EFI_PERIPHERAL_REMOTE_CONSOLE | EFI_P_EC_OUTPUT_ERROR, "OUTPUT_ERROR" },\r
+ { EFI_PERIPHERAL_REMOTE_CONSOLE | EFI_P_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_PERIPHERAL_SERIAL_PORT | EFI_P_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_PERIPHERAL_SERIAL_PORT | EFI_P_EC_DISABLED, "DISABLED" },\r
+ { EFI_PERIPHERAL_SERIAL_PORT | EFI_P_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_PERIPHERAL_SERIAL_PORT | EFI_P_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_PERIPHERAL_SERIAL_PORT | EFI_P_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_PERIPHERAL_SERIAL_PORT | EFI_P_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_PERIPHERAL_SERIAL_PORT | EFI_P_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_PERIPHERAL_SERIAL_PORT | EFI_P_EC_INPUT_ERROR, "INPUT_ERROR" },\r
+ { EFI_PERIPHERAL_SERIAL_PORT | EFI_P_EC_OUTPUT_ERROR, "OUTPUT_ERROR" },\r
+ { EFI_PERIPHERAL_SERIAL_PORT | EFI_P_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_PERIPHERAL_PARALLEL_PORT | EFI_P_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_PERIPHERAL_PARALLEL_PORT | EFI_P_EC_DISABLED, "DISABLED" },\r
+ { EFI_PERIPHERAL_PARALLEL_PORT | EFI_P_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_PERIPHERAL_PARALLEL_PORT | EFI_P_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_PERIPHERAL_PARALLEL_PORT | EFI_P_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_PERIPHERAL_PARALLEL_PORT | EFI_P_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_PERIPHERAL_PARALLEL_PORT | EFI_P_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_PERIPHERAL_PARALLEL_PORT | EFI_P_EC_INPUT_ERROR, "INPUT_ERROR" },\r
+ { EFI_PERIPHERAL_PARALLEL_PORT | EFI_P_EC_OUTPUT_ERROR, "OUTPUT_ERROR" },\r
+ { EFI_PERIPHERAL_PARALLEL_PORT | EFI_P_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_DISABLED, "DISABLED" },\r
+ { EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_INPUT_ERROR, "INPUT_ERROR" },\r
+ { EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_OUTPUT_ERROR, "OUTPUT_ERROR" },\r
+ { EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_PERIPHERAL_REMOVABLE_MEDIA | EFI_P_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_PERIPHERAL_REMOVABLE_MEDIA | EFI_P_EC_DISABLED, "DISABLED" },\r
+ { EFI_PERIPHERAL_REMOVABLE_MEDIA | EFI_P_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_PERIPHERAL_REMOVABLE_MEDIA | EFI_P_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_PERIPHERAL_REMOVABLE_MEDIA | EFI_P_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_PERIPHERAL_REMOVABLE_MEDIA | EFI_P_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_PERIPHERAL_REMOVABLE_MEDIA | EFI_P_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_PERIPHERAL_REMOVABLE_MEDIA | EFI_P_EC_INPUT_ERROR, "INPUT_ERROR" },\r
+ { EFI_PERIPHERAL_REMOVABLE_MEDIA | EFI_P_EC_OUTPUT_ERROR, "OUTPUT_ERROR" },\r
+ { EFI_PERIPHERAL_REMOVABLE_MEDIA | EFI_P_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_PERIPHERAL_AUDIO_INPUT | EFI_P_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_PERIPHERAL_AUDIO_INPUT | EFI_P_EC_DISABLED, "DISABLED" },\r
+ { EFI_PERIPHERAL_AUDIO_INPUT | EFI_P_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_PERIPHERAL_AUDIO_INPUT | EFI_P_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_PERIPHERAL_AUDIO_INPUT | EFI_P_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_PERIPHERAL_AUDIO_INPUT | EFI_P_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_PERIPHERAL_AUDIO_INPUT | EFI_P_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_PERIPHERAL_AUDIO_INPUT | EFI_P_EC_INPUT_ERROR, "INPUT_ERROR" },\r
+ { EFI_PERIPHERAL_AUDIO_INPUT | EFI_P_EC_OUTPUT_ERROR, "OUTPUT_ERROR" },\r
+ { EFI_PERIPHERAL_AUDIO_INPUT | EFI_P_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_PERIPHERAL_AUDIO_OUTPUT | EFI_P_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_PERIPHERAL_AUDIO_OUTPUT | EFI_P_EC_DISABLED, "DISABLED" },\r
+ { EFI_PERIPHERAL_AUDIO_OUTPUT | EFI_P_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_PERIPHERAL_AUDIO_OUTPUT | EFI_P_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_PERIPHERAL_AUDIO_OUTPUT | EFI_P_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_PERIPHERAL_AUDIO_OUTPUT | EFI_P_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_PERIPHERAL_AUDIO_OUTPUT | EFI_P_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_PERIPHERAL_AUDIO_OUTPUT | EFI_P_EC_INPUT_ERROR, "INPUT_ERROR" },\r
+ { EFI_PERIPHERAL_AUDIO_OUTPUT | EFI_P_EC_OUTPUT_ERROR, "OUTPUT_ERROR" },\r
+ { EFI_PERIPHERAL_AUDIO_OUTPUT | EFI_P_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_PERIPHERAL_LCD_DEVICE | EFI_P_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_PERIPHERAL_LCD_DEVICE | EFI_P_EC_DISABLED, "DISABLED" },\r
+ { EFI_PERIPHERAL_LCD_DEVICE | EFI_P_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_PERIPHERAL_LCD_DEVICE | EFI_P_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_PERIPHERAL_LCD_DEVICE | EFI_P_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_PERIPHERAL_LCD_DEVICE | EFI_P_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_PERIPHERAL_LCD_DEVICE | EFI_P_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_PERIPHERAL_LCD_DEVICE | EFI_P_EC_INPUT_ERROR, "INPUT_ERROR" },\r
+ { EFI_PERIPHERAL_LCD_DEVICE | EFI_P_EC_OUTPUT_ERROR, "OUTPUT_ERROR" },\r
+ { EFI_PERIPHERAL_LCD_DEVICE | EFI_P_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_IO_BUS_UNSPECIFIED | EFI_IOB_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_IO_BUS_UNSPECIFIED | EFI_IOB_EC_DISABLED, "DISABLED" },\r
+ { EFI_IO_BUS_UNSPECIFIED | EFI_IOB_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_IO_BUS_UNSPECIFIED | EFI_IOB_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_IO_BUS_UNSPECIFIED | EFI_IOB_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_IO_BUS_UNSPECIFIED | EFI_IOB_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_IO_BUS_UNSPECIFIED | EFI_IOB_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_IO_BUS_UNSPECIFIED | EFI_IOB_EC_READ_ERROR, "READ_ERROR" },\r
+ { EFI_IO_BUS_UNSPECIFIED | EFI_IOB_EC_WRITE_ERROR, "WRITE_ERROR" },\r
+ { EFI_IO_BUS_UNSPECIFIED | EFI_IOB_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_IO_BUS_PCI | EFI_IOB_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_IO_BUS_PCI | EFI_IOB_EC_DISABLED, "DISABLED" },\r
+ { EFI_IO_BUS_PCI | EFI_IOB_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_IO_BUS_PCI | EFI_IOB_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_IO_BUS_PCI | EFI_IOB_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_IO_BUS_PCI | EFI_IOB_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR, "READ_ERROR" },\r
+ { EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR, "WRITE_ERROR" },\r
+ { EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_IO_BUS_PCI | EFI_IOB_PCI_EC_PERR, "PERR" },\r
+ { EFI_IO_BUS_PCI | EFI_IOB_PCI_EC_SERR, "SERR" },\r
+ { EFI_IO_BUS_USB | EFI_IOB_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_IO_BUS_USB | EFI_IOB_EC_DISABLED, "DISABLED" },\r
+ { EFI_IO_BUS_USB | EFI_IOB_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_IO_BUS_USB | EFI_IOB_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_IO_BUS_USB | EFI_IOB_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_IO_BUS_USB | EFI_IOB_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_IO_BUS_USB | EFI_IOB_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_IO_BUS_USB | EFI_IOB_EC_READ_ERROR, "READ_ERROR" },\r
+ { EFI_IO_BUS_USB | EFI_IOB_EC_WRITE_ERROR, "WRITE_ERROR" },\r
+ { EFI_IO_BUS_USB | EFI_IOB_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_IO_BUS_IBA | EFI_IOB_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_IO_BUS_IBA | EFI_IOB_EC_DISABLED, "DISABLED" },\r
+ { EFI_IO_BUS_IBA | EFI_IOB_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_IO_BUS_IBA | EFI_IOB_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_IO_BUS_IBA | EFI_IOB_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_IO_BUS_IBA | EFI_IOB_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_IO_BUS_IBA | EFI_IOB_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_IO_BUS_IBA | EFI_IOB_EC_READ_ERROR, "READ_ERROR" },\r
+ { EFI_IO_BUS_IBA | EFI_IOB_EC_WRITE_ERROR, "WRITE_ERROR" },\r
+ { EFI_IO_BUS_IBA | EFI_IOB_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_IO_BUS_AGP | EFI_IOB_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_IO_BUS_AGP | EFI_IOB_EC_DISABLED, "DISABLED" },\r
+ { EFI_IO_BUS_AGP | EFI_IOB_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_IO_BUS_AGP | EFI_IOB_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_IO_BUS_AGP | EFI_IOB_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_IO_BUS_AGP | EFI_IOB_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_IO_BUS_AGP | EFI_IOB_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_IO_BUS_AGP | EFI_IOB_EC_READ_ERROR, "READ_ERROR" },\r
+ { EFI_IO_BUS_AGP | EFI_IOB_EC_WRITE_ERROR, "WRITE_ERROR" },\r
+ { EFI_IO_BUS_AGP | EFI_IOB_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_IO_BUS_PC_CARD | EFI_IOB_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_IO_BUS_PC_CARD | EFI_IOB_EC_DISABLED, "DISABLED" },\r
+ { EFI_IO_BUS_PC_CARD | EFI_IOB_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_IO_BUS_PC_CARD | EFI_IOB_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_IO_BUS_PC_CARD | EFI_IOB_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_IO_BUS_PC_CARD | EFI_IOB_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_IO_BUS_PC_CARD | EFI_IOB_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_IO_BUS_PC_CARD | EFI_IOB_EC_READ_ERROR, "READ_ERROR" },\r
+ { EFI_IO_BUS_PC_CARD | EFI_IOB_EC_WRITE_ERROR, "WRITE_ERROR" },\r
+ { EFI_IO_BUS_PC_CARD | EFI_IOB_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_IO_BUS_LPC | EFI_IOB_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_IO_BUS_LPC | EFI_IOB_EC_DISABLED, "DISABLED" },\r
+ { EFI_IO_BUS_LPC | EFI_IOB_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_IO_BUS_LPC | EFI_IOB_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_IO_BUS_LPC | EFI_IOB_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_IO_BUS_LPC | EFI_IOB_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_IO_BUS_LPC | EFI_IOB_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_IO_BUS_LPC | EFI_IOB_EC_READ_ERROR, "READ_ERROR" },\r
+ { EFI_IO_BUS_LPC | EFI_IOB_EC_WRITE_ERROR, "WRITE_ERROR" },\r
+ { EFI_IO_BUS_LPC | EFI_IOB_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_IO_BUS_SCSI | EFI_IOB_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_IO_BUS_SCSI | EFI_IOB_EC_DISABLED, "DISABLED" },\r
+ { EFI_IO_BUS_SCSI | EFI_IOB_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_IO_BUS_SCSI | EFI_IOB_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_IO_BUS_SCSI | EFI_IOB_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_IO_BUS_SCSI | EFI_IOB_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_IO_BUS_SCSI | EFI_IOB_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_IO_BUS_SCSI | EFI_IOB_EC_READ_ERROR, "READ_ERROR" },\r
+ { EFI_IO_BUS_SCSI | EFI_IOB_EC_WRITE_ERROR, "WRITE_ERROR" },\r
+ { EFI_IO_BUS_SCSI | EFI_IOB_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_IO_BUS_ATA_ATAPI | EFI_IOB_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_IO_BUS_ATA_ATAPI | EFI_IOB_EC_DISABLED, "DISABLED" },\r
+ { EFI_IO_BUS_ATA_ATAPI | EFI_IOB_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_IO_BUS_ATA_ATAPI | EFI_IOB_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_IO_BUS_ATA_ATAPI | EFI_IOB_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_IO_BUS_ATA_ATAPI | EFI_IOB_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_IO_BUS_ATA_ATAPI | EFI_IOB_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_IO_BUS_ATA_ATAPI | EFI_IOB_EC_READ_ERROR, "READ_ERROR" },\r
+ { EFI_IO_BUS_ATA_ATAPI | EFI_IOB_EC_WRITE_ERROR, "WRITE_ERROR" },\r
+ { EFI_IO_BUS_ATA_ATAPI | EFI_IOB_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_IO_BUS_FC | EFI_IOB_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_IO_BUS_FC | EFI_IOB_EC_DISABLED, "DISABLED" },\r
+ { EFI_IO_BUS_FC | EFI_IOB_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_IO_BUS_FC | EFI_IOB_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_IO_BUS_FC | EFI_IOB_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_IO_BUS_FC | EFI_IOB_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_IO_BUS_FC | EFI_IOB_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_IO_BUS_FC | EFI_IOB_EC_READ_ERROR, "READ_ERROR" },\r
+ { EFI_IO_BUS_FC | EFI_IOB_EC_WRITE_ERROR, "WRITE_ERROR" },\r
+ { EFI_IO_BUS_FC | EFI_IOB_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_IO_BUS_IP_NETWORK | EFI_IOB_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_IO_BUS_IP_NETWORK | EFI_IOB_EC_DISABLED, "DISABLED" },\r
+ { EFI_IO_BUS_IP_NETWORK | EFI_IOB_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_IO_BUS_IP_NETWORK | EFI_IOB_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_IO_BUS_IP_NETWORK | EFI_IOB_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_IO_BUS_IP_NETWORK | EFI_IOB_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_IO_BUS_IP_NETWORK | EFI_IOB_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_IO_BUS_IP_NETWORK | EFI_IOB_EC_READ_ERROR, "READ_ERROR" },\r
+ { EFI_IO_BUS_IP_NETWORK | EFI_IOB_EC_WRITE_ERROR, "WRITE_ERROR" },\r
+ { EFI_IO_BUS_IP_NETWORK | EFI_IOB_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_IO_BUS_SMBUS | EFI_IOB_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_IO_BUS_SMBUS | EFI_IOB_EC_DISABLED, "DISABLED" },\r
+ { EFI_IO_BUS_SMBUS | EFI_IOB_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_IO_BUS_SMBUS | EFI_IOB_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_IO_BUS_SMBUS | EFI_IOB_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_IO_BUS_SMBUS | EFI_IOB_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_IO_BUS_SMBUS | EFI_IOB_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_IO_BUS_SMBUS | EFI_IOB_EC_READ_ERROR, "READ_ERROR" },\r
+ { EFI_IO_BUS_SMBUS | EFI_IOB_EC_WRITE_ERROR, "WRITE_ERROR" },\r
+ { EFI_IO_BUS_SMBUS | EFI_IOB_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_IO_BUS_I2C | EFI_IOB_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_IO_BUS_I2C | EFI_IOB_EC_DISABLED, "DISABLED" },\r
+ { EFI_IO_BUS_I2C | EFI_IOB_EC_NOT_SUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_IO_BUS_I2C | EFI_IOB_EC_NOT_DETECTED, "NOT_DETECTED" },\r
+ { EFI_IO_BUS_I2C | EFI_IOB_EC_NOT_CONFIGURED, "NOT_CONFIGURED" },\r
+ { EFI_IO_BUS_I2C | EFI_IOB_EC_INTERFACE_ERROR, "INTERFACE_ERROR" },\r
+ { EFI_IO_BUS_I2C | EFI_IOB_EC_CONTROLLER_ERROR, "CONTROLLER_ERROR" },\r
+ { EFI_IO_BUS_I2C | EFI_IOB_EC_READ_ERROR, "READ_ERROR" },\r
+ { EFI_IO_BUS_I2C | EFI_IOB_EC_WRITE_ERROR, "WRITE_ERROR" },\r
+ { EFI_IO_BUS_I2C | EFI_IOB_EC_RESOURCE_CONFLICT, "RESOURCE_CONFLICT" },\r
+ { EFI_SOFTWARE_UNSPECIFIED | EFI_SW_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_SOFTWARE_UNSPECIFIED | EFI_SW_EC_LOAD_ERROR, "LOAD_ERROR" },\r
+ { EFI_SOFTWARE_UNSPECIFIED | EFI_SW_EC_INVALID_PARAMETER, "INVALID_PARAMETER" },\r
+ { EFI_SOFTWARE_UNSPECIFIED | EFI_SW_EC_UNSUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_SOFTWARE_UNSPECIFIED | EFI_SW_EC_INVALID_BUFFER, "INVALID_BUFFER" },\r
+ { EFI_SOFTWARE_UNSPECIFIED | EFI_SW_EC_OUT_OF_RESOURCES, "OUT_OF_RESOURCES" },\r
+ { EFI_SOFTWARE_UNSPECIFIED | EFI_SW_EC_ABORTED, "ABORTED" },\r
+ { EFI_SOFTWARE_UNSPECIFIED | EFI_SW_EC_ILLEGAL_SOFTWARE_STATE, "ILLEGAL_SOFTWARE_STATE" },\r
+ { EFI_SOFTWARE_UNSPECIFIED | EFI_SW_EC_ILLEGAL_HARDWARE_STATE, "ILLEGAL_HARDWARE_STATE" },\r
+ { EFI_SOFTWARE_SEC | EFI_SW_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_SOFTWARE_SEC | EFI_SW_EC_LOAD_ERROR, "LOAD_ERROR" },\r
+ { EFI_SOFTWARE_SEC | EFI_SW_EC_INVALID_PARAMETER, "INVALID_PARAMETER" },\r
+ { EFI_SOFTWARE_SEC | EFI_SW_EC_UNSUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_SOFTWARE_SEC | EFI_SW_EC_INVALID_BUFFER, "INVALID_BUFFER" },\r
+ { EFI_SOFTWARE_SEC | EFI_SW_EC_OUT_OF_RESOURCES, "OUT_OF_RESOURCES" },\r
+ { EFI_SOFTWARE_SEC | EFI_SW_EC_ABORTED, "ABORTED" },\r
+ { EFI_SOFTWARE_SEC | EFI_SW_EC_ILLEGAL_SOFTWARE_STATE, "ILLEGAL_SOFTWARE_STATE" },\r
+ { EFI_SOFTWARE_SEC | EFI_SW_EC_ILLEGAL_HARDWARE_STATE, "ILLEGAL_HARDWARE_STATE" },\r
+ { EFI_SOFTWARE_PEI_CORE | EFI_SW_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_SOFTWARE_PEI_CORE | EFI_SW_EC_LOAD_ERROR, "LOAD_ERROR" },\r
+ { EFI_SOFTWARE_PEI_CORE | EFI_SW_EC_INVALID_PARAMETER, "INVALID_PARAMETER" },\r
+ { EFI_SOFTWARE_PEI_CORE | EFI_SW_EC_UNSUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_SOFTWARE_PEI_CORE | EFI_SW_EC_INVALID_BUFFER, "INVALID_BUFFER" },\r
+ { EFI_SOFTWARE_PEI_CORE | EFI_SW_EC_OUT_OF_RESOURCES, "OUT_OF_RESOURCES" },\r
+ { EFI_SOFTWARE_PEI_CORE | EFI_SW_EC_ABORTED, "ABORTED" },\r
+ { EFI_SOFTWARE_PEI_CORE | EFI_SW_EC_ILLEGAL_SOFTWARE_STATE, "ILLEGAL_SOFTWARE_STATE" },\r
+ { EFI_SOFTWARE_PEI_CORE | EFI_SW_EC_ILLEGAL_HARDWARE_STATE, "ILLEGAL_HARDWARE_STATE" },\r
+ { EFI_SOFTWARE_PEI_MODULE | EFI_SW_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_SOFTWARE_PEI_MODULE | EFI_SW_EC_LOAD_ERROR, "LOAD_ERROR" },\r
+ { EFI_SOFTWARE_PEI_MODULE | EFI_SW_EC_INVALID_PARAMETER, "INVALID_PARAMETER" },\r
+ { EFI_SOFTWARE_PEI_MODULE | EFI_SW_EC_UNSUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_SOFTWARE_PEI_MODULE | EFI_SW_EC_INVALID_BUFFER, "INVALID_BUFFER" },\r
+ { EFI_SOFTWARE_PEI_MODULE | EFI_SW_EC_OUT_OF_RESOURCES, "OUT_OF_RESOURCES" },\r
+ { EFI_SOFTWARE_PEI_MODULE | EFI_SW_EC_ABORTED, "ABORTED" },\r
+ { EFI_SOFTWARE_PEI_MODULE | EFI_SW_EC_ILLEGAL_SOFTWARE_STATE, "ILLEGAL_SOFTWARE_STATE" },\r
+ { EFI_SOFTWARE_PEI_MODULE | EFI_SW_EC_ILLEGAL_HARDWARE_STATE, "ILLEGAL_HARDWARE_STATE" },\r
+ { EFI_SOFTWARE_DXE_CORE | EFI_SW_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_SOFTWARE_DXE_CORE | EFI_SW_EC_LOAD_ERROR, "LOAD_ERROR" },\r
+ { EFI_SOFTWARE_DXE_CORE | EFI_SW_EC_INVALID_PARAMETER, "INVALID_PARAMETER" },\r
+ { EFI_SOFTWARE_DXE_CORE | EFI_SW_EC_UNSUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_SOFTWARE_DXE_CORE | EFI_SW_EC_INVALID_BUFFER, "INVALID_BUFFER" },\r
+ { EFI_SOFTWARE_DXE_CORE | EFI_SW_EC_OUT_OF_RESOURCES, "OUT_OF_RESOURCES" },\r
+ { EFI_SOFTWARE_DXE_CORE | EFI_SW_EC_ABORTED, "ABORTED" },\r
+ { EFI_SOFTWARE_DXE_CORE | EFI_SW_EC_ILLEGAL_SOFTWARE_STATE, "ILLEGAL_SOFTWARE_STATE" },\r
+ { EFI_SOFTWARE_DXE_CORE | EFI_SW_EC_ILLEGAL_HARDWARE_STATE, "ILLEGAL_HARDWARE_STATE" },\r
+ { EFI_SOFTWARE_EFI_BOOT_SERVICE | EFI_SW_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_SOFTWARE_EFI_BOOT_SERVICE | EFI_SW_EC_LOAD_ERROR, "LOAD_ERROR" },\r
+ { EFI_SOFTWARE_EFI_BOOT_SERVICE | EFI_SW_EC_INVALID_PARAMETER, "INVALID_PARAMETER" },\r
+ { EFI_SOFTWARE_EFI_BOOT_SERVICE | EFI_SW_EC_UNSUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_SOFTWARE_EFI_BOOT_SERVICE | EFI_SW_EC_INVALID_BUFFER, "INVALID_BUFFER" },\r
+ { EFI_SOFTWARE_EFI_BOOT_SERVICE | EFI_SW_EC_OUT_OF_RESOURCES, "OUT_OF_RESOURCES" },\r
+ { EFI_SOFTWARE_EFI_BOOT_SERVICE | EFI_SW_EC_ABORTED, "ABORTED" },\r
+ { EFI_SOFTWARE_EFI_BOOT_SERVICE | EFI_SW_EC_ILLEGAL_SOFTWARE_STATE, "ILLEGAL_SOFTWARE_STATE" },\r
+ { EFI_SOFTWARE_EFI_BOOT_SERVICE | EFI_SW_EC_ILLEGAL_HARDWARE_STATE, "ILLEGAL_HARDWARE_STATE" },\r
+ { EFI_SOFTWARE_EFI_RUNTIME_SERVICE | EFI_SW_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_SOFTWARE_EFI_RUNTIME_SERVICE | EFI_SW_EC_LOAD_ERROR, "LOAD_ERROR" },\r
+ { EFI_SOFTWARE_EFI_RUNTIME_SERVICE | EFI_SW_EC_INVALID_PARAMETER, "INVALID_PARAMETER" },\r
+ { EFI_SOFTWARE_EFI_RUNTIME_SERVICE | EFI_SW_EC_UNSUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_SOFTWARE_EFI_RUNTIME_SERVICE | EFI_SW_EC_INVALID_BUFFER, "INVALID_BUFFER" },\r
+ { EFI_SOFTWARE_EFI_RUNTIME_SERVICE | EFI_SW_EC_OUT_OF_RESOURCES, "OUT_OF_RESOURCES" },\r
+ { EFI_SOFTWARE_EFI_RUNTIME_SERVICE | EFI_SW_EC_ABORTED, "ABORTED" },\r
+ { EFI_SOFTWARE_EFI_RUNTIME_SERVICE | EFI_SW_EC_ILLEGAL_SOFTWARE_STATE, "ILLEGAL_SOFTWARE_STATE" },\r
+ { EFI_SOFTWARE_EFI_RUNTIME_SERVICE | EFI_SW_EC_ILLEGAL_HARDWARE_STATE, "ILLEGAL_HARDWARE_STATE" },\r
+ { EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_EC_LOAD_ERROR, "LOAD_ERROR" },\r
+ { EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_EC_INVALID_PARAMETER, "INVALID_PARAMETER" },\r
+ { EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_EC_UNSUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_EC_INVALID_BUFFER, "INVALID_BUFFER" },\r
+ { EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_EC_OUT_OF_RESOURCES, "OUT_OF_RESOURCES" },\r
+ { EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_EC_ABORTED, "ABORTED" },\r
+ { EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_EC_ILLEGAL_SOFTWARE_STATE, "ILLEGAL_SOFTWARE_STATE" },\r
+ { EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_EC_ILLEGAL_HARDWARE_STATE, "ILLEGAL_HARDWARE_STATE" },\r
+ { EFI_SOFTWARE_DXE_RT_DRIVER | EFI_SW_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_SOFTWARE_DXE_RT_DRIVER | EFI_SW_EC_LOAD_ERROR, "LOAD_ERROR" },\r
+ { EFI_SOFTWARE_DXE_RT_DRIVER | EFI_SW_EC_INVALID_PARAMETER, "INVALID_PARAMETER" },\r
+ { EFI_SOFTWARE_DXE_RT_DRIVER | EFI_SW_EC_UNSUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_SOFTWARE_DXE_RT_DRIVER | EFI_SW_EC_INVALID_BUFFER, "INVALID_BUFFER" },\r
+ { EFI_SOFTWARE_DXE_RT_DRIVER | EFI_SW_EC_OUT_OF_RESOURCES, "OUT_OF_RESOURCES" },\r
+ { EFI_SOFTWARE_DXE_RT_DRIVER | EFI_SW_EC_ABORTED, "ABORTED" },\r
+ { EFI_SOFTWARE_DXE_RT_DRIVER | EFI_SW_EC_ILLEGAL_SOFTWARE_STATE, "ILLEGAL_SOFTWARE_STATE" },\r
+ { EFI_SOFTWARE_DXE_RT_DRIVER | EFI_SW_EC_ILLEGAL_HARDWARE_STATE, "ILLEGAL_HARDWARE_STATE" },\r
+ { EFI_SOFTWARE_SMM_DRIVER | EFI_SW_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_SOFTWARE_SMM_DRIVER | EFI_SW_EC_LOAD_ERROR, "LOAD_ERROR" },\r
+ { EFI_SOFTWARE_SMM_DRIVER | EFI_SW_EC_INVALID_PARAMETER, "INVALID_PARAMETER" },\r
+ { EFI_SOFTWARE_SMM_DRIVER | EFI_SW_EC_UNSUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_SOFTWARE_SMM_DRIVER | EFI_SW_EC_INVALID_BUFFER, "INVALID_BUFFER" },\r
+ { EFI_SOFTWARE_SMM_DRIVER | EFI_SW_EC_OUT_OF_RESOURCES, "OUT_OF_RESOURCES" },\r
+ { EFI_SOFTWARE_SMM_DRIVER | EFI_SW_EC_ABORTED, "ABORTED" },\r
+ { EFI_SOFTWARE_SMM_DRIVER | EFI_SW_EC_ILLEGAL_SOFTWARE_STATE, "ILLEGAL_SOFTWARE_STATE" },\r
+ { EFI_SOFTWARE_SMM_DRIVER | EFI_SW_EC_ILLEGAL_HARDWARE_STATE, "ILLEGAL_HARDWARE_STATE" },\r
+ { EFI_SOFTWARE_RT | EFI_SW_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_SOFTWARE_RT | EFI_SW_EC_LOAD_ERROR, "LOAD_ERROR" },\r
+ { EFI_SOFTWARE_RT | EFI_SW_EC_INVALID_PARAMETER, "INVALID_PARAMETER" },\r
+ { EFI_SOFTWARE_RT | EFI_SW_EC_UNSUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_SOFTWARE_RT | EFI_SW_EC_INVALID_BUFFER, "INVALID_BUFFER" },\r
+ { EFI_SOFTWARE_RT | EFI_SW_EC_OUT_OF_RESOURCES, "OUT_OF_RESOURCES" },\r
+ { EFI_SOFTWARE_RT | EFI_SW_EC_ABORTED, "ABORTED" },\r
+ { EFI_SOFTWARE_RT | EFI_SW_EC_ILLEGAL_SOFTWARE_STATE, "ILLEGAL_SOFTWARE_STATE" },\r
+ { EFI_SOFTWARE_RT | EFI_SW_EC_ILLEGAL_HARDWARE_STATE, "ILLEGAL_HARDWARE_STATE" },\r
+ { EFI_SOFTWARE_AL | EFI_SW_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_SOFTWARE_AL | EFI_SW_EC_LOAD_ERROR, "LOAD_ERROR" },\r
+ { EFI_SOFTWARE_AL | EFI_SW_EC_INVALID_PARAMETER, "INVALID_PARAMETER" },\r
+ { EFI_SOFTWARE_AL | EFI_SW_EC_UNSUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_SOFTWARE_AL | EFI_SW_EC_INVALID_BUFFER, "INVALID_BUFFER" },\r
+ { EFI_SOFTWARE_AL | EFI_SW_EC_OUT_OF_RESOURCES, "OUT_OF_RESOURCES" },\r
+ { EFI_SOFTWARE_AL | EFI_SW_EC_ABORTED, "ABORTED" },\r
+ { EFI_SOFTWARE_AL | EFI_SW_EC_ILLEGAL_SOFTWARE_STATE, "ILLEGAL_SOFTWARE_STATE" },\r
+ { EFI_SOFTWARE_AL | EFI_SW_EC_ILLEGAL_HARDWARE_STATE, "ILLEGAL_HARDWARE_STATE" },\r
+ { EFI_SOFTWARE_EFI_APPLICATION | EFI_SW_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_SOFTWARE_EFI_APPLICATION | EFI_SW_EC_LOAD_ERROR, "LOAD_ERROR" },\r
+ { EFI_SOFTWARE_EFI_APPLICATION | EFI_SW_EC_INVALID_PARAMETER, "INVALID_PARAMETER" },\r
+ { EFI_SOFTWARE_EFI_APPLICATION | EFI_SW_EC_UNSUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_SOFTWARE_EFI_APPLICATION | EFI_SW_EC_INVALID_BUFFER, "INVALID_BUFFER" },\r
+ { EFI_SOFTWARE_EFI_APPLICATION | EFI_SW_EC_OUT_OF_RESOURCES, "OUT_OF_RESOURCES" },\r
+ { EFI_SOFTWARE_EFI_APPLICATION | EFI_SW_EC_ABORTED, "ABORTED" },\r
+ { EFI_SOFTWARE_EFI_APPLICATION | EFI_SW_EC_ILLEGAL_SOFTWARE_STATE, "ILLEGAL_SOFTWARE_STATE" },\r
+ { EFI_SOFTWARE_EFI_APPLICATION | EFI_SW_EC_ILLEGAL_HARDWARE_STATE, "ILLEGAL_HARDWARE_STATE" },\r
+ { EFI_SOFTWARE_EFI_OS_LOADER | EFI_SW_EC_NON_SPECIFIC, "NON_SPECIFIC" },\r
+ { EFI_SOFTWARE_EFI_OS_LOADER | EFI_SW_EC_LOAD_ERROR, "LOAD_ERROR" },\r
+ { EFI_SOFTWARE_EFI_OS_LOADER | EFI_SW_EC_INVALID_PARAMETER, "INVALID_PARAMETER" },\r
+ { EFI_SOFTWARE_EFI_OS_LOADER | EFI_SW_EC_UNSUPPORTED, "NOT_SUPPORTED" },\r
+ { EFI_SOFTWARE_EFI_OS_LOADER | EFI_SW_EC_INVALID_BUFFER, "INVALID_BUFFER" },\r
+ { EFI_SOFTWARE_EFI_OS_LOADER | EFI_SW_EC_OUT_OF_RESOURCES, "OUT_OF_RESOURCES" },\r
+ { EFI_SOFTWARE_EFI_OS_LOADER | EFI_SW_EC_ABORTED, "ABORTED" },\r
+ { EFI_SOFTWARE_EFI_OS_LOADER | EFI_SW_EC_ILLEGAL_SOFTWARE_STATE, "ILLEGAL_SOFTWARE_STATE" },\r
+ { EFI_SOFTWARE_EFI_OS_LOADER | EFI_SW_EC_ILLEGAL_HARDWARE_STATE, "ILLEGAL_HARDWARE_STATE" },\r
+ { 0xFFFFFFFF, "ERROR_UNRECOGNIZED" }\r
+ };\r
+\r
+\r
+//\r
+// Private function declarations\r
+//\r
+UINT8\r
+CpuIoRead8 (\r
+ UINT16 Port \r
+ );\r
+\r
+VOID\r
+CpuIoWrite8 (\r
+ UINT16 Port, \r
+ UINT32 Data \r
+ );\r
+\r
+\r
+EFI_STATUS\r
+MatchString (\r
+ IN STATUS_CODE_LOOKUP_TABLE *Table,\r
+ IN UINT32 Value,\r
+ OUT CHAR8 **Token\r
+ );\r
+\r
+//\r
+// Function implemenations\r
+//\r
+\r
+//\r
+// Match is only needed for debug.\r
+//\r
+\r
+EFI_STATUS\r
+MatchString (\r
+ IN STATUS_CODE_LOOKUP_TABLE *Table,\r
+ IN UINT32 Value,\r
+ OUT CHAR8 **Token\r
+ )\r
+/*++\r
+\r
+Routine Description: \r
+\r
+ Search the input table for a matching value and return the token associated\r
+ with that value. Well formed tables will have the last value == 0 and will \r
+ return a default token.\r
+\r
+Arguments: \r
+\r
+ Table Pointer to first entry in an array of table entries.\r
+ Value Value to look up.\r
+ Token String to return.\r
+\r
+Returns: \r
+\r
+ EFI_SUCCESS The function always returns success.\r
+\r
+--*/\r
+{\r
+ UINTN Current;\r
+ \r
+ Current = 0;\r
+ *Token = 0;\r
+\r
+ while (!*Token) {\r
+ //\r
+ // Found token if values match or current entry is the last entry.\r
+ //\r
+ if ((Table[Current].Value == (-1)) ||\r
+ (Table[Current].Value == Value)) {\r
+ *Token = Table[Current].Token;\r
+ }\r
+ Current++;\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+\r
+VOID\r
+DebugSerialWrite (\r
+ IN UINT8 Character\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ DebugSerialWrite - Outputs a character to the Serial port\r
+\r
+ Repeatedly polls the TXRDY bit of the Line Status Register\r
+ until the Transmitter Holding Register is empty. The character\r
+ is then written to the Serial port.\r
+\r
+Arguments:\r
+\r
+ Character - Character to write\r
+\r
+Returns:\r
+\r
+ None\r
+\r
+--*/\r
+{\r
+ UINT8 Data;\r
+\r
+ //\r
+ // Wait for the serail port to be ready.\r
+ //\r
+ do {\r
+ Data = CpuIoRead8 (gComBase + LSR_OFFSET);\r
+ } while ((Data & LSR_TXRDY) == 0);\r
+ \r
+ CpuIoWrite8 (gComBase, Character);\r
+}\r
+\r
+VOID\r
+DebugSerialPrint (\r
+ IN UINT8 *OutputString\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Prints a string to the Serial port\r
+\r
+Arguments:\r
+\r
+ OutputString - Ascii string to print to serial port.\r
+\r
+Returns:\r
+\r
+ None\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ Status = EFI_SUCCESS;\r
+\r
+ for ( ; *OutputString != 0; OutputString++) {\r
+ DebugSerialWrite (*OutputString);\r
+ }\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI \r
+SerialReportStatusCode (\r
+ IN EFI_STATUS_CODE_TYPE CodeType,\r
+ IN EFI_STATUS_CODE_VALUE Value,\r
+ IN UINT32 Instance,\r
+ IN EFI_GUID *CallerId,\r
+ IN EFI_STATUS_CODE_DATA *Data OPTIONAL\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Provide a serial port print\r
+\r
+Arguments:\r
+\r
+ PeiServices - General purpose services available to every PEIM.\r
+ \r
+Returns:\r
+\r
+ Status - EFI_SUCCESS if the interface could be successfully\r
+ installed\r
+\r
+--*/\r
+{\r
+ CHAR8 Buffer[EFI_STATUS_CODE_DATA_MAX_SIZE];\r
+ UINT32 LineNumber;\r
+ CHAR8 *Filename;\r
+ CHAR8 *Description;\r
+ CHAR8 *Format;\r
+ VA_LIST Marker;\r
+ UINT32 ErrorLevel;\r
+ UINTN CharCount;\r
+\r
+ Buffer[0] = '\0';\r
+\r
+ if (ReportStatusCodeExtractAssertInfo (CodeType, Value, Data, &Filename, &Description, &LineNumber)) {\r
+ //\r
+ // Processes PEI_ASSERT ()\r
+ //\r
+ AsciiSPrint (\r
+ Buffer,\r
+ EFI_STATUS_CODE_DATA_MAX_SIZE,\r
+ "\nPEI_ASSERT!: %a (%d): %a\n",\r
+ Filename,\r
+ LineNumber,\r
+ Description\r
+ );\r
+\r
+ } else if (ReportStatusCodeExtractDebugInfo (Data, &ErrorLevel, &Marker, &Format)) {\r
+ //\r
+ // Process PEI_DEBUG () macro to Serial\r
+ //\r
+ AsciiVSPrint (Buffer, EFI_STATUS_CODE_DATA_MAX_SIZE, Format, Marker);\r
+\r
+ } else if ((CodeType & EFI_STATUS_CODE_TYPE_MASK) == EFI_ERROR_CODE) { \r
+ //\r
+ // Process Errors\r
+ //\r
+ CharCount = AsciiSPrint (Buffer, EFI_STATUS_CODE_DATA_MAX_SIZE, "ERROR: C%x:V%x I%x", CodeType, Value, Instance);\r
+ //\r
+ // Make sure we don't try to print values that weren't intended to be printed, especially NULL GUID pointers.\r
+ //\r
+ if (CallerId) {\r
+ CharCount += AsciiSPrint (&Buffer[CharCount - 1], (EFI_STATUS_CODE_DATA_MAX_SIZE - (sizeof(Buffer[0]) * CharCount)), " %g", CallerId);\r
+ }\r
+ if (Data) {\r
+ CharCount += AsciiSPrint (&Buffer[CharCount - 1], (EFI_STATUS_CODE_DATA_MAX_SIZE - (sizeof(Buffer[0]) * CharCount)), " %x", Data);\r
+ }\r
+ CharCount += AsciiSPrint (&Buffer[CharCount - 1], (EFI_STATUS_CODE_DATA_MAX_SIZE - (sizeof(Buffer[0]) * CharCount)), "\n");\r
+\r
+ }\r
+\r
+ if (Buffer[0] != '\0') {\r
+ //\r
+ // Callout to platform Lib function to do print.\r
+ //\r
+ DebugSerialPrint (Buffer);\r
+ }\r
+\r
+ //\r
+ // Debug code to display human readable code information.\r
+ //\r
+ {\r
+ CHAR8 *SeverityToken;\r
+ CHAR8 *SubClassToken;\r
+ CHAR8 *OperationToken;\r
+\r
+ if ((CodeType & EFI_STATUS_CODE_TYPE_MASK) == EFI_ERROR_CODE) { \r
+ //\r
+ // Get the severity token\r
+ //\r
+ MatchString (\r
+ mSeverityToken,\r
+ (CodeType & EFI_STATUS_CODE_SEVERITY_MASK),\r
+ &SeverityToken\r
+ );\r
+ \r
+ //\r
+ // Get the Class/SubClass token\r
+ //\r
+ MatchString (\r
+ mClassSubClassToken,\r
+ (Value & (EFI_STATUS_CODE_CLASS_MASK | EFI_STATUS_CODE_SUBCLASS_MASK)),\r
+ &SubClassToken\r
+ );\r
+ \r
+ //\r
+ // Get the operation token\r
+ //\r
+ MatchString (\r
+ mOperationToken,\r
+ (Value & (EFI_STATUS_CODE_CLASS_MASK | EFI_STATUS_CODE_SUBCLASS_MASK | EFI_STATUS_CODE_OPERATION_MASK)),\r
+ &OperationToken\r
+ );\r
+ \r
+ //\r
+ // Concatenate the instance\r
+ //\r
+ AsciiSPrint (\r
+ Buffer,\r
+ EFI_STATUS_CODE_DATA_MAX_SIZE,\r
+ "%a:%a:%a:%d\n",\r
+ SeverityToken,\r
+ SubClassToken,\r
+ OperationToken,\r
+ Instance\r
+ );\r
+\r
+ DebugSerialPrint (Buffer);\r
+ }\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+VOID\r
+InstallSerialStatusCode (\r
+ IN EFI_REPORT_STATUS_CODE *ReportStatusCode\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Initialize Serial Port\r
+\r
+ The Baud Rate Divisor registers are programmed and the LCR \r
+ is used to configure the communications format. Hard coded\r
+ UART config comes from globals in DebugSerialPlatform lib.\r
+\r
+Arguments: \r
+\r
+ None\r
+\r
+Returns: \r
+\r
+ None\r
+\r
+--*/\r
+{\r
+ UINTN Divisor;\r
+ UINT8 OutputData;\r
+ UINT8 Data;\r
+\r
+ //\r
+ // Some init is done by the platform status code initialization.\r
+ //\r
+ \r
+ //\r
+ // Map 5..8 to 0..3\r
+ //\r
+ Data = (UINT8) (gData - (UINT8)5);\r
+\r
+ //\r
+ // Calculate divisor for baud generator\r
+ //\r
+ Divisor = 115200 / gBps; \r
+ \r
+ //\r
+ // Set communications format\r
+ //\r
+ OutputData = (UINT8)((DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data))));\r
+ CpuIoWrite8 (gComBase + LCR_OFFSET, OutputData);\r
+\r
+ //\r
+ // Configure baud rate\r
+ //\r
+ CpuIoWrite8 (gComBase + BAUD_HIGH_OFFSET, (UINT8)(Divisor >> 8));\r
+ CpuIoWrite8 (gComBase + BAUD_LOW_OFFSET, (UINT8)(Divisor & 0xff));\r
+\r
+ //\r
+ // Switch back to bank 0\r
+ //\r
+ OutputData = (UINT8)((~DLAB<<7)|((gBreakSet<<6)|((gParity<<3)|((gStop<<2)| Data))));\r
+ CpuIoWrite8 (gComBase + LCR_OFFSET, OutputData);\r
+\r
+ *ReportStatusCode = SerialReportStatusCode;\r
+}\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ SerialStatusCode.h\r
+\r
+Abstract:\r
+\r
+Revision History:\r
+\r
+--*/\r
+\r
+#ifndef _DXELDR_SERIAL_STATUS_CODE_H_\r
+#define _DXELDR_SERIAL_STATUS_CODE_H_\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#include "DxeIpl.h"\r
+\r
+//\r
+// GUID consumed\r
+//\r
+\r
+\r
+//---------------------------------------------\r
+// UART Register Offsets\r
+//---------------------------------------------\r
+#define BAUD_LOW_OFFSET 0x00\r
+#define BAUD_HIGH_OFFSET 0x01\r
+#define IER_OFFSET 0x01\r
+#define LCR_SHADOW_OFFSET 0x01\r
+#define FCR_SHADOW_OFFSET 0x02\r
+#define IR_CONTROL_OFFSET 0x02\r
+#define FCR_OFFSET 0x02\r
+#define EIR_OFFSET 0x02\r
+#define BSR_OFFSET 0x03\r
+#define LCR_OFFSET 0x03\r
+#define MCR_OFFSET 0x04\r
+#define LSR_OFFSET 0x05\r
+#define MSR_OFFSET 0x06\r
+\r
+//---------------------------------------------\r
+// UART Register Bit Defines\r
+//---------------------------------------------\r
+#define LSR_TXRDY 0x20\r
+#define LSR_RXDA 0x01\r
+#define DLAB 0x01\r
+\r
+//\r
+// Globals for Serial Port settings\r
+//\r
+extern UINT16 gComBase;\r
+extern UINTN gBps;\r
+extern UINT8 gData;\r
+extern UINT8 gStop;\r
+extern UINT8 gParity;\r
+extern UINT8 gBreakSet;\r
+\r
+VOID\r
+DebugSerialPrint (\r
+ IN UINT8 *OutputString\r
+ );\r
+\r
+VOID\r
+DebugSerialWrite (\r
+ IN UINT8 Character\r
+ );\r
+\r
+VOID\r
+InstallSerialStatusCode (\r
+ IN EFI_REPORT_STATUS_CODE *ReportStatusCode\r
+ );\r
+\r
+#endif \r
--- /dev/null
+ title CpuIoAccess.asm\r
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006 - 2007, Intel Corporation \r
+; All rights reserved. This program and the accompanying materials \r
+; are licensed and made available under the terms and conditions of the BSD License \r
+; which accompanies this distribution. The full text of the license may be found at \r
+; http://opensource.org/licenses/bsd-license.php \r
+; \r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+; \r
+; Module Name:\r
+; CpuIoAccess.asm\r
+; \r
+; Abstract:\r
+; CPU IO Abstraction\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+\r
+.code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT8\r
+; CpuIoRead8 (\r
+; UINT16 Port // rcx\r
+; )\r
+;------------------------------------------------------------------------------\r
+CpuIoRead8 PROC PUBLIC\r
+ xor eax, eax\r
+ mov dx, cx\r
+ in al, dx\r
+ ret\r
+CpuIoRead8 ENDP\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; CpuIoWrite8 (\r
+; UINT16 Port, // rcx\r
+; UINT32 Data // rdx\r
+; )\r
+;------------------------------------------------------------------------------\r
+CpuIoWrite8 PROC PUBLIC\r
+ mov eax, edx\r
+ mov dx, cx\r
+ out dx, al\r
+ ret\r
+CpuIoWrite8 ENDP\r
+\r
+\r
+END\r
--- /dev/null
+ TITLE EnterDxeCore.asm: Assembly code for the entering DxeCore\r
+;------------------------------------------------------------------------------\r
+;*\r
+;* Copyright 2006, Intel Corporation \r
+;* All rights reserved. This program and the accompanying materials \r
+;* are licensed and made available under the terms and conditions of the BSD License \r
+;* which accompanies this distribution. The full text of the license may be found at \r
+;* http://opensource.org/licenses/bsd-license.php \r
+;* \r
+;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+;* \r
+;* EnterDxeCore.asm\r
+;* \r
+;* Abstract:\r
+;*\r
+;------------------------------------------------------------------------------\r
+\r
+.code\r
+\r
+;\r
+; VOID\r
+; EnterDxeMain (\r
+; IN VOID *StackTop, // rcx\r
+; IN VOID *DxeCoreEntryPoint, // rdx\r
+; IN VOID *Hob, // r8\r
+; IN VOID *PageTable // r9\r
+; )\r
+;\r
+EnterDxeMain PROC\r
+ \r
+ mov cr3, r9\r
+ sub rcx, 32\r
+ mov rsp, rcx\r
+ mov rcx, r8\r
+ push 0\r
+ jmp rdx\r
+\r
+; should never get here\r
+ jmp $\r
+ ret\r
+\r
+EnterDxeMain ENDP\r
+\r
+END\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006 - 2007, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ Paging.c\r
+\r
+Abstract:\r
+\r
+Revision History:\r
+\r
+--*/\r
+\r
+#include "HobGeneration.h"\r
+#include "VirtualMemory.h"\r
+\r
+//\r
+// Create 2M-page table\r
+// PML4 (47:39)\r
+// PDPTE (38:30)\r
+// PDE (29:21)\r
+//\r
+\r
+#define EFI_2M_PAGE_BITS_NUM 21\r
+#define EFI_MAX_ENTRY_BITS_NUM 9\r
+\r
+#define EFI_PAGE_SIZE_4K 0x1000\r
+#define EFI_PAGE_SIZE_2M (1 << EFI_2M_PAGE_BITS_NUM)\r
+\r
+#ifndef MIN\r
+ #define MIN(a, b) ((a) < (b) ? (a) : (b))\r
+#endif\r
+#define ENTRY_NUM(x) ((UINTN)1 << (x))\r
+\r
+UINT8 gPML4BitsNum;\r
+UINT8 gPDPTEBitsNum;\r
+UINT8 gPDEBitsNum;\r
+\r
+UINTN gPageNum2M;\r
+UINTN gPageNum4K;\r
+\r
+VOID\r
+EnableNullPointerProtection (\r
+ UINT8 *PageTable\r
+ )\r
+{\r
+ X64_PAGE_TABLE_ENTRY_4K *PageTableEntry4KB;\r
+\r
+ PageTableEntry4KB = (X64_PAGE_TABLE_ENTRY_4K *) (PageTable + gPageNum2M * EFI_PAGE_SIZE_4K);\r
+ //\r
+ // Fill in the Page Table entries\r
+ // Mark 0~4K as not present\r
+ //\r
+ PageTableEntry4KB->Bits.Present = 0;\r
+\r
+ return ;\r
+}\r
+\r
+VOID\r
+X64Create4KPageTables (\r
+ UINT8 *PageTable\r
+ )\r
+/*++\r
+Routine Description:\r
+ Create 4K-Page-Table for the low 2M memory.\r
+ This will change the previously created 2M-Page-Table-Entry.\r
+--*/\r
+{\r
+ UINT64 PageAddress;\r
+ UINTN PTEIndex;\r
+ X64_PAGE_DIRECTORY_ENTRY_4K *PageDirectoryEntry4KB;\r
+ X64_PAGE_TABLE_ENTRY_4K *PageTableEntry4KB;\r
+\r
+ //\r
+ // Page Table structure 4 level 4K.\r
+ //\r
+ // PageMapLevel4Entry : bits 47-39\r
+ // PageDirectoryPointerEntry : bits 38-30\r
+ // Page Table 4K : PageDirectoryEntry4K : bits 29-21\r
+ // PageTableEntry : bits 20-12\r
+ //\r
+\r
+ PageTableEntry4KB = (X64_PAGE_TABLE_ENTRY_4K *)(PageTable + gPageNum2M * EFI_PAGE_SIZE_4K);\r
+\r
+ PageDirectoryEntry4KB = (X64_PAGE_DIRECTORY_ENTRY_4K *) (PageTable + 2 * EFI_PAGE_SIZE_4K);\r
+ PageDirectoryEntry4KB->Uint64 = (UINT64)(UINTN)PageTableEntry4KB;\r
+ PageDirectoryEntry4KB->Bits.ReadWrite = 1;\r
+ PageDirectoryEntry4KB->Bits.Present = 1;\r
+ PageDirectoryEntry4KB->Bits.MustBeZero = 0;\r
+\r
+ for (PTEIndex = 0, PageAddress = 0; \r
+ PTEIndex < ENTRY_NUM (EFI_MAX_ENTRY_BITS_NUM); \r
+ PTEIndex++, PageTableEntry4KB++, PageAddress += EFI_PAGE_SIZE_4K\r
+ ) {\r
+ //\r
+ // Fill in the Page Table entries\r
+ //\r
+ PageTableEntry4KB->Uint64 = (UINT64)PageAddress;\r
+ PageTableEntry4KB->Bits.ReadWrite = 1;\r
+ PageTableEntry4KB->Bits.Present = 1;\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+VOID\r
+X64Create2MPageTables (\r
+ UINT8 *PageTable\r
+ )\r
+{\r
+ UINT64 PageAddress;\r
+ UINT8 *TempPageTable;\r
+ UINTN PML4Index;\r
+ UINTN PDPTEIndex;\r
+ UINTN PDEIndex;\r
+ X64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *PageMapLevel4Entry;\r
+ X64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *PageDirectoryPointerEntry;\r
+ X64_PAGE_TABLE_ENTRY_2M *PageDirectoryEntry2MB;\r
+\r
+ TempPageTable = PageTable;\r
+ PageAddress = 0;\r
+\r
+ //\r
+ // Page Table structure 3 level 2MB.\r
+ //\r
+ // PageMapLevel4Entry : bits 47-39\r
+ // PageDirectoryPointerEntry : bits 38-30\r
+ // Page Table 2MB : PageDirectoryEntry2M : bits 29-21\r
+ //\r
+\r
+ PageMapLevel4Entry = (X64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *)TempPageTable;\r
+\r
+ for (PML4Index = 0; PML4Index < ENTRY_NUM (gPML4BitsNum); PML4Index++, PageMapLevel4Entry++) {\r
+ //\r
+ // Each PML4 entry points to a page of Page Directory Pointer entires.\r
+ // \r
+ TempPageTable += EFI_PAGE_SIZE_4K;\r
+ PageDirectoryPointerEntry = (X64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *)TempPageTable;\r
+\r
+ //\r
+ // Make a PML4 Entry\r
+ //\r
+ PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)(TempPageTable);\r
+ PageMapLevel4Entry->Bits.ReadWrite = 1;\r
+ PageMapLevel4Entry->Bits.Present = 1;\r
+\r
+ for (PDPTEIndex = 0; PDPTEIndex < ENTRY_NUM (gPDPTEBitsNum); PDPTEIndex++, PageDirectoryPointerEntry++) {\r
+ //\r
+ // Each Directory Pointer entries points to a page of Page Directory entires.\r
+ // \r
+ TempPageTable += EFI_PAGE_SIZE_4K;\r
+ PageDirectoryEntry2MB = (X64_PAGE_TABLE_ENTRY_2M *)TempPageTable;\r
+\r
+ //\r
+ // Fill in a Page Directory Pointer Entries\r
+ //\r
+ PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)(TempPageTable);\r
+ PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
+ PageDirectoryPointerEntry->Bits.Present = 1;\r
+\r
+ for (PDEIndex = 0; PDEIndex < ENTRY_NUM (gPDEBitsNum); PDEIndex++, PageDirectoryEntry2MB++) {\r
+ //\r
+ // Fill in the Page Directory entries\r
+ //\r
+ PageDirectoryEntry2MB->Uint64 = (UINT64)PageAddress;\r
+ PageDirectoryEntry2MB->Bits.ReadWrite = 1;\r
+ PageDirectoryEntry2MB->Bits.Present = 1;\r
+ PageDirectoryEntry2MB->Bits.MustBe1 = 1;\r
+\r
+ PageAddress += EFI_PAGE_SIZE_2M;\r
+ }\r
+ }\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+VOID *\r
+PreparePageTable (\r
+ VOID *PageNumberTop,\r
+ UINT8 SizeOfMemorySpace\r
+ )\r
+/*++\r
+Description:\r
+ Generate pagetable below PageNumberTop, \r
+ and return the bottom address of pagetable for putting other things later.\r
+--*/\r
+{\r
+ VOID *PageNumberBase;\r
+\r
+ SizeOfMemorySpace -= EFI_2M_PAGE_BITS_NUM;\r
+ gPDEBitsNum = MIN (SizeOfMemorySpace, EFI_MAX_ENTRY_BITS_NUM);\r
+ SizeOfMemorySpace = SizeOfMemorySpace - gPDEBitsNum;\r
+ gPDPTEBitsNum = MIN (SizeOfMemorySpace, EFI_MAX_ENTRY_BITS_NUM);\r
+ SizeOfMemorySpace = SizeOfMemorySpace - gPDPTEBitsNum;\r
+ gPML4BitsNum = SizeOfMemorySpace;\r
+ if (gPML4BitsNum > EFI_MAX_ENTRY_BITS_NUM) {\r
+ return NULL;\r
+ }\r
+\r
+ //\r
+ // Suppose we have:\r
+ // 2MPage:\r
+ // Entry: PML4 -> PDPTE -> PDE -> Page\r
+ // EntryNum: a b c\r
+ // then\r
+ // Occupy4KPage: 1 a a*b\r
+ // \r
+ // 2M 4KPage:\r
+ // Entry: PTE -> Page\r
+ // EntryNum: 512\r
+ // then\r
+ // Occupy4KPage: 1\r
+ // \r
+\r
+ gPageNum2M = 1 + ENTRY_NUM (gPML4BitsNum) + ENTRY_NUM (gPML4BitsNum + gPDPTEBitsNum);\r
+ gPageNum4K = 1;\r
+\r
+\r
+ PageNumberBase = (VOID *)((UINTN)PageNumberTop - (gPageNum2M + gPageNum4K) * EFI_PAGE_SIZE_4K);\r
+ ZeroMem (PageNumberBase, (gPageNum2M + gPageNum4K) * EFI_PAGE_SIZE_4K);\r
+\r
+ X64Create2MPageTables (PageNumberBase);\r
+ X64Create4KPageTables (PageNumberBase);\r
+ //\r
+ // Not enable NULL Pointer Protection if using INTx call\r
+ //\r
+// EnableNullPointerProtection (PageNumberBase);\r
+\r
+ return PageNumberBase;\r
+}\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ VirtualMemory.h\r
+\r
+Abstract:\r
+\r
+Revision History:\r
+\r
+--*/\r
+ \r
+#ifndef _VIRTUAL_MEMORY_H_\r
+#define _VIRTUAL_MEMORY_H_\r
+\r
+#pragma pack(1)\r
+\r
+//\r
+// Page Map Level 4 Offset (PML4) and\r
+// Page Directory Pointer Table (PDPE) entries 4K & 2M\r
+//\r
+\r
+typedef union {\r
+ struct {\r
+ UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
+ UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
+ UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
+ UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+ UINT64 Reserved:1; // Reserved\r
+ UINT64 MustBeZero:2; // Must Be Zero\r
+ UINT64 Available:3; // Available for use by system software\r
+ UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
+ UINT64 AvabilableHigh:11; // Available for use by system software\r
+ UINT64 Nx:1; // No Execute bit\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} X64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K;\r
+\r
+//\r
+// Page Directory Entry 4K\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
+ UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
+ UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
+ UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+ UINT64 MustBeZero:3; // Must Be Zero\r
+ UINT64 Available:3; // Available for use by system software\r
+ UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
+ UINT64 AvabilableHigh:11; // Available for use by system software\r
+ UINT64 Nx:1; // No Execute bit\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} X64_PAGE_DIRECTORY_ENTRY_4K;\r
+\r
+//\r
+// Page Table Entry 4K\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
+ UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
+ UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
+ UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+ UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
+ UINT64 PAT:1; // 0 = Ignore Page Attribute Table \r
+ UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
+ UINT64 Available:3; // Available for use by system software\r
+ UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
+ UINT64 AvabilableHigh:11; // Available for use by system software\r
+ UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} X64_PAGE_TABLE_ENTRY_4K;\r
+\r
+//\r
+// Page Table Entry 2M\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
+ UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
+ UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
+ UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
+ UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
+ UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+ UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
+ UINT64 MustBe1:1; // Must be 1 \r
+ UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
+ UINT64 Available:3; // Available for use by system software\r
+ UINT64 PAT:1; //\r
+ UINT64 MustBeZero:8; // Must be zero;\r
+ UINT64 PageTableBaseAddress:31; // Page Table Base Address\r
+ UINT64 AvabilableHigh:11; // Available for use by system software\r
+ UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} X64_PAGE_TABLE_ENTRY_2M;\r
+\r
+#pragma pack()\r
+\r
+#endif \r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation. All rights reserved.\r
+This software and associated documentation (if any) is furnished\r
+under a license and may only be used or copied in accordance\r
+with the terms of the license. Except as permitted by such\r
+license, no part of this software or documentation may be\r
+reproduced, stored in a retrieval system, or transmitted in any\r
+form or by any means without the express written consent of\r
+Intel Corporation.\r
+\r
+Module Name:\r
+\r
+ CpuIA32.h\r
+\r
+Abstract:\r
+\r
+ Basic Definition for IA32 Architecture.\r
+\r
+--*/\r
+\r
+#ifndef _CPU_IA32_H_\r
+#define _CPU_IA32_H_\r
+\r
+typedef struct {\r
+ UINT32 RegEax;\r
+ UINT32 RegEbx;\r
+ UINT32 RegEcx;\r
+ UINT32 RegEdx;\r
+} EFI_CPUID_REGISTER;\r
+\r
+#pragma pack(1)\r
+//\r
+// Definition for IA32 microcode format\r
+//\r
+typedef struct {\r
+ UINT32 HeaderVersion;\r
+ UINT32 UpdateRevision;\r
+ UINT32 Date;\r
+ UINT32 ProcessorId;\r
+ UINT32 Checksum;\r
+ UINT32 LoaderRevision;\r
+ UINT32 ProcessorFlags;\r
+ UINT32 DataSize;\r
+ UINT32 TotalSize;\r
+ UINT8 Reserved[12];\r
+} EFI_CPU_MICROCODE_HEADER;\r
+\r
+typedef struct {\r
+ UINT32 ExtendedSignatureCount;\r
+ UINT32 ExtendedTableChecksum;\r
+ UINT8 Reserved[12];\r
+} EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;\r
+\r
+typedef struct {\r
+ UINT32 ProcessorSignature;\r
+ UINT32 ProcessorFlag;\r
+ UINT32 ProcessorChecksum;\r
+} EFI_CPU_MICROCODE_EXTENDED_TABLE;\r
+\r
+//\r
+// The MS compiler doesn't handle QWORDs very well. So break\r
+// them into DWORDs to circumvent the problem.\r
+//\r
+typedef union _MSR_REGISTER {\r
+ UINT64 Qword;\r
+\r
+ struct _DWORDS {\r
+ UINT32 Low;\r
+ UINT32 High;\r
+ } Dwords;\r
+\r
+ struct _BYTES {\r
+ UINT8 FirstByte;\r
+ UINT8 SecondByte;\r
+ UINT8 ThirdByte;\r
+ UINT8 FouthByte;\r
+ UINT8 FifthByte;\r
+ UINT8 SixthByte;\r
+ UINT8 SeventhByte;\r
+ UINT8 EighthByte;\r
+ } Bytes;\r
+\r
+} MSR_REGISTER;\r
+\r
+#pragma pack()\r
+\r
+//\r
+// Definition for CPUID Index\r
+//\r
+#define EFI_CPUID_SIGNATURE 0x0\r
+#define EFI_CPUID_VERSION_INFO 0x1\r
+#define EFI_CPUID_CACHE_INFO 0x2\r
+#define EFI_CPUID_SERIAL_NUMBER 0x3\r
+#define EFI_CPUID_EXTENDED_FUNCTION 0x80000000\r
+#define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001\r
+#define EFI_CPUID_BRAND_STRING1 0x80000002\r
+#define EFI_CPUID_BRAND_STRING2 0x80000003\r
+#define EFI_CPUID_BRAND_STRING3 0x80000004\r
+#define EFI_CPUID_ADDRESS_SIZE 0x80000008\r
+\r
+//\r
+// Definition for MSR address\r
+//\r
+#define EFI_MSR_IA32_PLATFORM_ID 0x17\r
+#define EFI_MSR_IA32_APIC_BASE 0x1B\r
+#define EFI_MSR_EBC_HARD_POWERON 0x2A\r
+#define EFI_MSR_EBC_SOFT_POWERON 0x2B\r
+#define EFI_MSR_EBC_FREQUENCY_ID 0x2C\r
+#define MSR_IA32_FEATURE_CONTROL 0x3A\r
+#define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79\r
+#define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B\r
+#define EFI_MSR_PSB_CLOCK_STATUS 0xCD\r
+#define MSR_EXT_CONFIG 0xEE\r
+#define EFI_IA32_MCG_CAP 0x179\r
+#define EFI_IA32_MCG_CTL 0x17B\r
+\r
+#define EFI_MSR_IA32_PERF_STS 0x198\r
+#define EFI_MSR_IA32_PERF_CTL 0x199\r
+#define EFI_MSR_IA32_CLOCK_MODULATION 0x19A\r
+#define MSR_IA32_THERMAL_INTERRUPT 0x19B\r
+#define EFI_MSR_IA32_THERM_STATUS 0x19C\r
+#define EFI_MSR_GV_THERM 0x19D\r
+#define MSR_IA32_MISC_ENABLE 0x1A0\r
+#define MSR_PIC_SENS_CFG 0x1AA\r
+\r
+#define EFI_IA32_MC0_CTL 0x400\r
+#define EFI_IA32_MC0_STATUS 0x401\r
+#define MSR_PECI_CONTROL 0x5A0\r
+\r
+//\r
+// Definition for MTRR address and related values\r
+//\r
+#define EFI_IA32_MTRR_FIX64K_00000 0x250\r
+#define EFI_IA32_MTRR_FIX16K_80000 0x258\r
+#define EFI_IA32_MTRR_FIX16K_A0000 0x259\r
+#define EFI_IA32_MTRR_FIX4K_C0000 0x268\r
+#define EFI_IA32_MTRR_FIX4K_C8000 0x269\r
+#define EFI_IA32_MTRR_FIX4K_D0000 0x26A\r
+#define EFI_IA32_MTRR_FIX4K_D8000 0x26B\r
+#define EFI_IA32_MTRR_FIX4K_E0000 0x26C\r
+#define EFI_IA32_MTRR_FIX4K_E8000 0x26D\r
+#define EFI_IA32_MTRR_FIX4K_F0000 0x26E\r
+#define EFI_IA32_MTRR_FIX4K_F8000 0x26F\r
+#define EFI_CACHE_VARIABLE_MTRR_BASE 0x200\r
+#define EFI_CACHE_VARIABLE_MTRR_END 0x20F\r
+#define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF\r
+\r
+#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000\r
+#define EFI_MSR_VALID_MASK 0xFFFFFFFFF\r
+#define EFI_CACHE_MTRR_VALID 0x800\r
+#define EFI_CACHE_FIXED_MTRR_VALID 0x400\r
+\r
+#define EFI_CACHE_UNCACHEABLE 0\r
+#define EFI_CACHE_WRITECOMBINING 1\r
+#define EFI_CACHE_WRITETHROUGH 4\r
+#define EFI_CACHE_WRITEPROTECTED 5\r
+#define EFI_CACHE_WRITEBACK 6\r
+\r
+//\r
+// Definition for Local APIC registers and related values\r
+//\r
+#define LOCAL_APIC_LVT_TIMER 0x320\r
+#define LOCAL_APIC_TIMER_INIT_COUNT 0x380\r
+#define LOCAL_APIC_TIMER_COUNT 0x390\r
+#define LOCAL_APIC_TIMER_DIVIDE 0x3E0\r
+\r
+\r
+#define DELIVERY_MODE_FIXED 0x0\r
+#define DELIVERY_MODE_LOWEST_PRIORITY 0x1\r
+#define DELIVERY_MODE_SMI 0x2\r
+#define DELIVERY_MODE_REMOTE_READ 0x3\r
+#define DELIVERY_MODE_NMI 0x4\r
+#define DELIVERY_MODE_INIT 0x5\r
+#define DELIVERY_MODE_SIPI 0x6\r
+\r
+#define TRIGGER_MODE_EDGE 0x0\r
+#define TRIGGER_MODE_LEVEL 0x1\r
+\r
+//\r
+// CPU System Memory Map Definition\r
+//\r
+#define CPU_MSI_MEMORY_BASE 0xFEE00000\r
+#define CPU_MSI_MEMORY_SIZE 0x100000\r
+\r
+\r
+#endif\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2004 - 2007, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+\r
+ EfiFlashMap.h\r
+\r
+Abstract:\r
+\r
+ Defines for the EFI Flash Map functionality\r
+ \r
+--*/\r
+\r
+#ifndef _EFI_FLASHMAP_H_\r
+#define _EFI_FLASHMAP_H_\r
+\r
+\r
+//\r
+// Definition for flash map GUIDed HOBs\r
+//\r
+typedef UINT32 EFI_FLASH_AREA_ATTRIBUTES;\r
+\r
+#define EFI_FLASH_AREA_FV 0x0001\r
+#define EFI_FLASH_AREA_SUBFV 0x0002\r
+#define EFI_FLASH_AREA_MEMMAPPED_FV 0x0004\r
+#define EFI_FLASH_AREA_REQUIRED 0x0008\r
+#define EFI_FLASH_AREA_CORRUPT 0x0010\r
+\r
+typedef UINT8 EFI_FLASH_AREA_TYPE;\r
+\r
+#define EFI_FLASH_AREA_RECOVERY_BIOS 0x0 // Recovery code\r
+#define EFI_FLASH_AREA_MAIN_BIOS 0x1 // Regular BIOS code\r
+#define EFI_FLASH_AREA_PAL_B 0x2 // PAL-B\r
+#define EFI_FLASH_AREA_RESERVED_03 0x3 // Reserved for backwards compatibility\r
+#define EFI_FLASH_AREA_RESERVED_04 0x4 // Reserved for backwards compatibility\r
+#define EFI_FLASH_AREA_DMI_FRU 0x5 // DMI FRU information\r
+#define EFI_FLASH_AREA_OEM_BINARY 0x6 // OEM Binary Code/data\r
+#define EFI_FLASH_AREA_RESERVED_07 0x7 // Reserved for backwards compatibility\r
+#define EFI_FLASH_AREA_RESERVED_08 0x8 // Reserved for backwards compatibility\r
+#define EFI_FLASH_AREA_RESERVED_09 0x9 // Reserved for backwards compatibility\r
+#define EFI_FLASH_AREA_RESERVED_0A 0x0a // Reserved for backwards compatibility\r
+#define EFI_FLASH_AREA_EFI_VARIABLES 0x0b // EFI variables\r
+#define EFI_FLASH_AREA_MCA_LOG 0x0c // MCA error log\r
+#define EFI_FLASH_AREA_SMBIOS_LOG 0x0d // SMBIOS error log\r
+#define EFI_FLASH_AREA_FTW_BACKUP 0x0e // A backup block during FTW operations\r
+#define EFI_FLASH_AREA_FTW_STATE 0x0f // State information during FTW operations\r
+#define EFI_FLASH_AREA_UNUSED 0x0fd // Not used\r
+#define EFI_FLASH_AREA_GUID_DEFINED 0x0fe // Usage defined by a GUID\r
+#pragma pack(1)\r
+//\r
+// An individual sub-area Entry.\r
+// A single flash area may consist of more than one sub-area.\r
+//\r
+typedef struct {\r
+ EFI_FLASH_AREA_ATTRIBUTES Attributes;\r
+ UINT32 Reserved;\r
+ EFI_PHYSICAL_ADDRESS Base;\r
+ EFI_PHYSICAL_ADDRESS Length;\r
+ EFI_GUID FileSystem;\r
+} EFI_FLASH_SUBAREA_ENTRY;\r
+\r
+typedef struct {\r
+ UINT8 Reserved[3];\r
+ EFI_FLASH_AREA_TYPE AreaType;\r
+ EFI_GUID AreaTypeGuid;\r
+ UINT32 NumEntries;\r
+ EFI_FLASH_SUBAREA_ENTRY Entries[1];\r
+} EFI_FLASH_MAP_ENTRY_DATA;\r
+\r
+typedef struct {\r
+ UINT8 Reserved[3];\r
+ EFI_FLASH_AREA_TYPE AreaType;\r
+ EFI_GUID AreaTypeGuid;\r
+ UINT32 NumberOfEntries;\r
+ EFI_FLASH_SUBAREA_ENTRY Entries[1];\r
+ //\r
+ // Extended Hob data.\r
+ //\r
+ // VolumeId and FilePath indicating a unique file.\r
+ //\r
+ UINT32 VolumeId;\r
+ CHAR16 FilePath[256];\r
+ UINT32 ActuralSize;\r
+ UINT32 Offset;\r
+} EFI_FLASH_MAP_FS_ENTRY_DATA;\r
+\r
+typedef struct {\r
+ EFI_HOB_GENERIC_HEADER Header;\r
+ EFI_GUID Name;\r
+ UINT8 Reserved[3];\r
+ EFI_FLASH_AREA_TYPE AreaType;\r
+ EFI_GUID AreaTypeGuid;\r
+ UINT32 NumEntries;\r
+ EFI_FLASH_SUBAREA_ENTRY Entries[1];\r
+} EFI_HOB_FLASH_MAP_ENTRY_TYPE;\r
+\r
+//\r
+// Internal definitions\r
+//\r
+typedef struct {\r
+ UINT8 Reserved[3];\r
+ EFI_FLASH_AREA_TYPE AreaType;\r
+ EFI_GUID AreaTypeGuid;\r
+ UINT32 NumberOfEntries;\r
+ EFI_FLASH_SUBAREA_ENTRY SubAreaData;\r
+} EFI_FLASH_AREA_HOB_DATA;\r
+\r
+typedef struct {\r
+ UINTN Base;\r
+ UINTN Length;\r
+ EFI_FLASH_AREA_ATTRIBUTES Attributes;\r
+ EFI_FLASH_AREA_TYPE AreaType;\r
+ UINT8 Reserved[3];\r
+ EFI_GUID AreaTypeGuid;\r
+} EFI_FLASH_AREA_DATA;\r
+\r
+#pragma pack()\r
+\r
+#endif // #ifndef _EFI_FLASHMAP_H_\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ EfiLdrHandoff.h\r
+\r
+Abstract:\r
+\r
+Revision History:\r
+\r
+--*/\r
+\r
+#ifndef _EFILDR_HANDOFF_H_\r
+#define _EFILDR_HANDOFF_H_\r
+\r
+#include <Base.h>\r
+#include <Uefi.h>\r
+\r
+#define EFILDR_BASE_SEGMENT 0x2000\r
+#define EFILDR_LOAD_ADDRESS (EFILDR_BASE_SEGMENT << 4)\r
+#define EFILDR_HEADER_ADDRESS (EFILDR_LOAD_ADDRESS+0x2000)\r
+\r
+#define EFILDR_CB_VA 0x00\r
+\r
+typedef struct _EFILDRHANDOFF {\r
+ UINTN MemDescCount;\r
+ EFI_MEMORY_DESCRIPTOR *MemDesc;\r
+ VOID *BfvBase;\r
+ UINTN BfvSize;\r
+ VOID *DxeIplImageBase;\r
+ UINTN DxeIplImageSize;\r
+ VOID *DxeCoreImageBase;\r
+ UINTN DxeCoreImageSize;\r
+ VOID *DxeCoreEntryPoint;\r
+} EFILDRHANDOFF;\r
+\r
+typedef struct {\r
+ UINT32 CheckSum;\r
+ UINT32 Offset;\r
+ UINT32 Length;\r
+ UINT8 FileName[52];\r
+} EFILDR_IMAGE;\r
+\r
+typedef struct { \r
+ UINT32 Signature; \r
+ UINT32 HeaderCheckSum;\r
+ UINT32 FileLength;\r
+ UINT32 NumberOfImages;\r
+} EFILDR_HEADER;\r
+\r
+#endif\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2007, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+\r
+ FlashLayout.h\r
+ \r
+Abstract:\r
+\r
+ Platform specific flash layout\r
+\r
+--*/\r
+\r
+#ifndef _EFI_FLASH_LAYOUT\r
+#define _EFI_FLASH_LAYOUT\r
+\r
+#include "EfiFlashMap.h"\r
+\r
+//\r
+// Firmware Volume Information for DUET\r
+//\r
+#define FV_BLOCK_SIZE 0x10000\r
+#define FV_BLOCK_MASK 0x0FFFF\r
+#define EFI_RUNTIME_UPDATABLE_FV_HEADER_LENGTH (sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY))\r
+\r
+#define NV_STORAGE_SIZE 0x4000\r
+#define NV_STORAGE_FVB_SIZE ((NV_STORAGE_SIZE + EFI_RUNTIME_UPDATABLE_FV_HEADER_LENGTH + FV_BLOCK_MASK) & ~FV_BLOCK_MASK)\r
+#define NV_STORAGE_FVB_BLOCK_NUM (NV_STORAGE_FVB_SIZE / FV_BLOCK_SIZE)\r
+\r
+#define NV_FTW_WORKING_SIZE 0x2000\r
+#define NV_FTW_SPARE_SIZE 0x10000\r
+#define NV_FTW_FVB_SIZE ((NV_FTW_WORKING_SIZE + NV_FTW_SPARE_SIZE + EFI_RUNTIME_UPDATABLE_FV_HEADER_LENGTH + FV_BLOCK_MASK) & ~FV_BLOCK_MASK)\r
+#define NV_FTW_FVB_BLOCK_NUM (NV_FTW_FVB_SIZE / FV_BLOCK_SIZE)\r
+\r
+#define NV_STORAGE_FILE_PATH L"\\Efivar.bin"\r
+#endif // _EFI_FLASH_LAYOUT\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006 - 2007, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ \r
+ AcpiDescription.h\r
+ \r
+Abstract:\r
+\r
+\r
+ GUIDs used for ACPI Description\r
+\r
+--*/\r
+\r
+#ifndef _EFI_ACPI_DESCRIPTION_H_\r
+#define _EFI_ACPI_DESCRIPTION_H_\r
+\r
+#define EFI_ACPI_DESCRIPTION_GUID \\r
+ { \\r
+ 0x3c699197, 0x93c, 0x4c69, 0xb0, 0x6b, 0x12, 0x8a, 0xe3, 0x48, 0x1d, 0xc9 \\r
+ }\r
+\r
+typedef struct {\r
+ UINT8 AddressSpaceId;\r
+ UINT8 RegisterBitWidth;\r
+ UINT8 RegisterBitOffset;\r
+ UINT8 AccessSize;\r
+ UINT64 Address;\r
+} EFI_ACPI_GENERIC_ADDRESS_STRUCTURE;\r
+\r
+#define ACPI_ADDRESS_ID_MEMORY 0\r
+#define ACPI_ADDRESS_ID_IO 1\r
+#define ACPI_ADDRESS_ID_PCI 2\r
+#define ACPI_ADDRESS_ID_EC 3\r
+#define ACPI_ADDRESS_ID_SMBUS 4\r
+\r
+#define ACPI_ADDRESS_ACCESS_ANY 0\r
+#define ACPI_ADDRESS_ACCESS_BYTE 1\r
+#define ACPI_ADDRESS_ACCESS_WORD 2\r
+#define ACPI_ADDRESS_ACCESS_DWORD 3\r
+#define ACPI_ADDRESS_ACCESS_QWORD 4\r
+\r
+//\r
+// Following structure defines ACPI Description information.\r
+// This information is platform specific, may be consumed by DXE generic driver.\r
+//\r
+#pragma pack(1)\r
+typedef struct _EFI_ACPI_DESCRIPTION {\r
+ //\r
+ // For Timer\r
+ //\r
+ EFI_ACPI_GENERIC_ADDRESS_STRUCTURE PM_TMR_BLK;\r
+ UINT8 PM_TMR_LEN;\r
+ UINT8 TMR_VAL_EXT;\r
+\r
+ //\r
+ // For RTC\r
+ //\r
+ UINT8 DAY_ALRM;\r
+ UINT8 MON_ALRM;\r
+ UINT8 CENTURY;\r
+\r
+ //\r
+ // For Reset\r
+ //\r
+ EFI_ACPI_GENERIC_ADDRESS_STRUCTURE RESET_REG;\r
+ UINT8 RESET_VALUE;\r
+\r
+ //\r
+ // For Shutdown\r
+ //\r
+ EFI_ACPI_GENERIC_ADDRESS_STRUCTURE PM1a_EVT_BLK;\r
+ EFI_ACPI_GENERIC_ADDRESS_STRUCTURE PM1b_EVT_BLK;\r
+ EFI_ACPI_GENERIC_ADDRESS_STRUCTURE PM1a_CNT_BLK;\r
+ EFI_ACPI_GENERIC_ADDRESS_STRUCTURE PM1b_CNT_BLK;\r
+ EFI_ACPI_GENERIC_ADDRESS_STRUCTURE PM2_CNT_BLK;\r
+ UINT8 PM1_EVT_LEN;\r
+ UINT8 PM1_CNT_LEN;\r
+ UINT8 PM2_CNT_LEN;\r
+ UINT8 SLP_TYPa;\r
+ UINT8 SLP_TYPb;\r
+\r
+ //\r
+ // For sleep\r
+ //\r
+ UINT8 SLP1_TYPa;\r
+ UINT8 SLP1_TYPb;\r
+ UINT8 SLP2_TYPa;\r
+ UINT8 SLP2_TYPb;\r
+ UINT8 SLP3_TYPa;\r
+ UINT8 SLP3_TYPb;\r
+ UINT8 SLP4_TYPa;\r
+ UINT8 SLP4_TYPb;\r
+\r
+ //\r
+ // GPE\r
+ //\r
+ EFI_ACPI_GENERIC_ADDRESS_STRUCTURE GPE0_BLK;\r
+ EFI_ACPI_GENERIC_ADDRESS_STRUCTURE GPE1_BLK;\r
+ UINT8 GPE0_BLK_LEN;\r
+ UINT8 GPE1_BLK_LEN;\r
+ UINT8 GPE1_BASE;\r
+\r
+ //\r
+ // IAPC Boot Arch\r
+ //\r
+ UINT16 IAPC_BOOT_ARCH;\r
+\r
+ //\r
+ // Flags\r
+ //\r
+ UINT32 Flags;\r
+\r
+} EFI_ACPI_DESCRIPTION;\r
+#pragma pack()\r
+\r
+extern EFI_GUID gEfiAcpiDescriptionGuid;\r
+\r
+#endif\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2004, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+\r
+ FlashMapHob.h\r
+ \r
+Abstract:\r
+\r
+ GUID used for Flash Map HOB entries in the HOB list.\r
+\r
+--*/\r
+\r
+#ifndef _FLASH_MAP_HOB_GUID_H_\r
+#define _FLASH_MAP_HOB_GUID_H_\r
+\r
+//\r
+// Definitions for Flash Map\r
+//\r
+#define EFI_FLASH_MAP_HOB_GUID \\r
+ { 0xb091e7d2, 0x5a0, 0x4198, 0x94, 0xf0, 0x74, 0xb7, 0xb8, 0xc5, 0x54, 0x59 }\r
+\r
+extern EFI_GUID gEfiFlashMapHobGuid;\r
+\r
+#endif // _FLASH_MAP_HOB_GUID_H_\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation \r
+All rights reserved. This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+ \r
+ PciExpressBaseAddress.h\r
+ \r
+Abstract:\r
+\r
+\r
+ GUIDs used for PciExpress Base Address\r
+\r
+--*/\r
+\r
+#ifndef _EFI_PCI_EXPRESS_BASE_ADDRESS_H_\r
+#define _EFI_PCI_EXPRESS_BASE_ADDRESS_H_\r
+\r
+#define EFI_PCI_EXPRESS_BASE_ADDRESS_GUID \\r
+ { \\r
+ 0x3677d529, 0x326f, 0x4603, 0xa9, 0x26, 0xea, 0xac, 0xe0, 0x1d, 0xcb, 0xb0 \\r
+ }\r
+\r
+//\r
+// Following structure defines PCI Express Base Address information.\r
+// This information is platform specific, and built into hob in PEI phase.\r
+// It can be consumed by PEI PCI driver and DXE PCI driver.\r
+//\r
+#pragma pack(1)\r
+typedef struct _EFI_PCI_EXPRESS_BASE_ADDRESS_INFORMATION {\r
+ UINT32 HostBridgeNumber;\r
+ UINT32 RootBridgeNumber;\r
+ UINT64 PciExpressBaseAddress;\r
+} EFI_PCI_EXPRESS_BASE_ADDRESS_INFORMATION;\r
+#pragma pack()\r
+\r
+extern EFI_GUID gEfiPciExpressBaseAddressGuid;\r
+\r
+#endif\r