CpuDeadLoop (\r
VOID\r
);\r
-\r
#if defined (MDE_CPU_IPF)\r
\r
/**\r
Flush a range of cache lines in the cache coherency domain of the calling\r
CPU.\r
\r
- Invalidates the cache lines specified by Address and Length. If Address is\r
- not aligned on a cache line boundary, then entire cache line containing\r
- Address is invalidated. If Address + Length is not aligned on a cache line\r
- boundary, then the entire instruction cache line containing Address + Length\r
- -1 is invalidated. This function may choose to invalidate the entire\r
- instruction cache if that is more efficient than invalidating the specified\r
- range. If Length is 0, the no instruction cache lines are invalidated.\r
- Address is returned.\r
+ Flushes the cache lines specified by Address and Length. If Address is not aligned \r
+ on a cache line boundary, then entire cache line containing Address is flushed. \r
+ If Address + Length is not aligned on a cache line boundary, then the entire cache \r
+ line containing Address + Length - 1 is flushed. This function may choose to flush \r
+ the entire cache if that is more efficient than flushing the specified range. If \r
+ Length is 0, the no cache lines are flushed. Address is returned. \r
+ This function is only available on IPF.\r
\r
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
\r
\r
@param Length The number of bytes to invalidate from the instruction cache.\r
\r
- @return Address\r
+ @return Address.\r
\r
**/\r
VOID *\r
EFIAPI\r
-IpfFlushCacheRange (\r
+AsmFlushCacheRange (\r
IN VOID *Address,\r
IN UINTN Length\r
);\r
)\r
{\r
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
- return IpfFlushCacheRange (Address, Length);\r
+ return AsmFlushCacheRange (Address, Length);\r
}\r
\r
/**\r
{\r
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
\r
- return IpfFlushCacheRange (Address, Length);\r
+ return AsmFlushCacheRange (Address, Length);\r
}\r
\r
/**\r
{\r
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
\r
- return IpfFlushCacheRange (Address, Length);\r
+ return AsmFlushCacheRange (Address, Length);\r
}\r
\r
/**\r
// Invalidation of a data cache range without writing back is not supported on\r
// IPF architecture, so write back and invalidate operation is performed.\r
//\r
- return IpfFlushCacheRange (Address, Length);\r
+ return AsmFlushCacheRange (Address, Length);\r
}\r
// invalidate the entire instruction cache if that is more efficient than\r
// invalidating the specified range. If Length is 0, the no instruction cache\r
// lines are invalidated. Address is returned.\r
+// This function is only available on IPF.\r
//\r
// If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
//\r
// \r
// VOID *\r
// EFIAPI\r
-// IpfFlushCacheRange (\r
+// AsmFlushCacheRange (\r
// IN VOID *Address,\r
// IN UINTN Length\r
// );\r
//\r
-PROCEDURE_ENTRY (IpfFlushCacheRange)\r
+PROCEDURE_ENTRY (AsmFlushCacheRange)\r
\r
NESTED_SETUP (5,8,0,0)\r
\r
mov r8 = in0 // return *Address\r
NESTED_RETURN\r
\r
-PROCEDURE_EXIT (IpfFlushCacheRange)\r
+PROCEDURE_EXIT (AsmFlushCacheRange)\r
\r