+typedef struct {\r
+ UINT64 Status;\r
+ UINT64 r9;\r
+ UINT64 r10;\r
+ UINT64 r11;\r
+} PAL_PROC_RETURN;\r
+\r
+//\r
+// IPF Specific functions\r
+//\r
+\r
+\r
+/**\r
+ Performs a PAL call using static calling convention.\r
+\r
+ An internal function to perform a PAL call using static calling convention.\r
+\r
+ @param PalEntryPoint The entry point address of PAL. The address in ar.kr5\r
+ would be used if this parameter were NULL on input.\r
+ @param Arg1 The first argument of a PAL call.\r
+ @param Arg1 The second argument of a PAL call.\r
+ @param Arg1 The third argument of a PAL call.\r
+ @param Arg1 The fourth argument of a PAL call.\r
+\r
+ @return The values returned in r8, r9, r10 and r11.\r
+\r
+**/\r
+PAL_PROC_RETURN\r
+PalCallStatic (\r
+ IN CONST VOID *PalEntryPoint,\r
+ IN UINT64 Arg1,\r
+ IN UINT64 Arg2,\r
+ IN UINT64 Arg3,\r
+ IN UINT64 Arg4\r
+ );\r
+\r
+\r
+/**\r
+ Returns the current value of ar.itc.\r
+\r
+ An internal function to return the current value of ar.itc, which is the\r
+ timer tick on IPF.\r
+\r
+ @return The currect value of ar.itc\r
+\r
+**/\r
+INT64\r
+IpfReadItc (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Invalidates a range of instruction cache lines in the cache coherency domain\r
+ of the calling CPU.\r
+\r
+ Invalidates the instruction cache lines specified by Address and Length. If\r
+ Address is not aligned on a cache line boundary, then entire instruction\r
+ cache line containing Address is invalidated. If Address + Length is not\r
+ aligned on a cache line boundary, then the entire instruction cache line\r
+ containing Address + Length -1 is invalidated. This function may choose to\r
+ invalidate the entire instruction cache if that is more efficient than\r
+ invalidating the specified range. If Length is 0, the no instruction cache\r
+ lines are invalidated. Address is returned.\r
+\r
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+ @param Address The base address of the instruction cache lines to\r
+ invalidate. If the CPU is in a physical addressing mode, then\r
+ Address is a physical address. If the CPU is in a virtual\r
+ addressing mode, then Address is a virtual address.\r
+\r
+ @param Length The number of bytes to invalidate from the instruction cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+IpfInvalidateInstructionCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ );\r
+\r