IN VOID *NewBsp\r
);\r
\r
+typedef struct {\r
+ UINT64 Status;\r
+ UINT64 r9;\r
+ UINT64 r10;\r
+ UINT64 r11;\r
+} PAL_PROC_RETURN;\r
+\r
+//\r
+// IPF Specific functions\r
+//\r
+\r
+\r
+/**\r
+ Performs a PAL call using static calling convention.\r
+\r
+ An internal function to perform a PAL call using static calling convention.\r
+\r
+ @param PalEntryPoint The entry point address of PAL. The address in ar.kr5\r
+ would be used if this parameter were NULL on input.\r
+ @param Arg1 The first argument of a PAL call.\r
+ @param Arg1 The second argument of a PAL call.\r
+ @param Arg1 The third argument of a PAL call.\r
+ @param Arg1 The fourth argument of a PAL call.\r
+\r
+ @return The values returned in r8, r9, r10 and r11.\r
+\r
+**/\r
+PAL_PROC_RETURN\r
+PalCallStatic (\r
+ IN CONST VOID *PalEntryPoint,\r
+ IN UINT64 Arg1,\r
+ IN UINT64 Arg2,\r
+ IN UINT64 Arg3,\r
+ IN UINT64 Arg4\r
+ );\r
+\r
+\r
+/**\r
+ Returns the current value of ar.itc.\r
+\r
+ An internal function to return the current value of ar.itc, which is the\r
+ timer tick on IPF.\r
+\r
+ @return The currect value of ar.itc\r
+\r
+**/\r
+INT64\r
+IpfReadItc (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Invalidates a range of instruction cache lines in the cache coherency domain\r
+ of the calling CPU.\r
+\r
+ Invalidates the instruction cache lines specified by Address and Length. If\r
+ Address is not aligned on a cache line boundary, then entire instruction\r
+ cache line containing Address is invalidated. If Address + Length is not\r
+ aligned on a cache line boundary, then the entire instruction cache line\r
+ containing Address + Length -1 is invalidated. This function may choose to\r
+ invalidate the entire instruction cache if that is more efficient than\r
+ invalidating the specified range. If Length is 0, the no instruction cache\r
+ lines are invalidated. Address is returned.\r
+\r
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+ @param Address The base address of the instruction cache lines to\r
+ invalidate. If the CPU is in a physical addressing mode, then\r
+ Address is a physical address. If the CPU is in a virtual\r
+ addressing mode, then Address is a virtual address.\r
+\r
+ @param Length The number of bytes to invalidate from the instruction cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+IpfInvalidateInstructionCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ );\r
+\r
#endif\r
<?xml version="1.0" encoding="UTF-8"?>\r
-<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0">\r
+<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">\r
<MsaHeader>\r
<ModuleName>BaseCacheMaintenanceLib</ModuleName>\r
<ModuleType>BASE</ModuleType>\r
<GuidValue>123dd843-57c9-4158-8418-ce68b3944ce7</GuidValue>\r
<Version>1.0</Version>\r
<Abstract>Component description file for Base Cache Maintenance Library</Abstract>\r
- <Description>Cache Maintenance Library that uses Base Library services to maintain caches.\r
+ <Description>Cache Maintenance Library that uses Base Library services to maintain caches.
This library assumes there are no chipset dependencies required to maintain caches.</Description>\r
<Copyright>Copyright (c) 2006, Intel Corporation</Copyright>\r
- <License>All rights reserved. This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ <License>All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>\r
<Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION 0x00000052</Specification>\r
</MsaHeader>\r
<Filename SupArchList="X64">x86Cache.c</Filename>\r
<Filename SupArchList="EBC">EbcCache.c</Filename>\r
<Filename SupArchList="IPF">IpfCache.c</Filename>\r
- <Filename SupArchList="IPF">Ipf/Cpu.s</Filename>\r
- <Filename SupArchList="IPF">Ipf/PalCallStatic.s</Filename>\r
</SourceFiles>\r
<PackageDependencies>\r
<Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>\r
\r
**/\r
\r
-typedef struct {\r
- UINT64 Status;\r
- UINT64 r9;\r
- UINT64 r10;\r
- UINT64 r11;\r
-} PAL_PROC_RETURN;\r
-\r
-PAL_PROC_RETURN\r
-PalCallStatic (\r
- IN CONST VOID *PalEntryPoint,\r
- IN UINT64 Arg1,\r
- IN UINT64 Arg2,\r
- IN UINT64 Arg3,\r
- IN UINT64 Arg4\r
- );\r
\r
/**\r
Invalidates the entire instruction cache in cache coherency domain of the\r
PalCallStatic (NULL, 1, 1, 1, 0);\r
}\r
\r
+/**\r
+ Invalidates a range of instruction cache lines in the cache coherency domain\r
+ of the calling CPU.\r
+\r
+ Invalidates the instruction cache lines specified by Address and Length. If\r
+ Address is not aligned on a cache line boundary, then entire instruction\r
+ cache line containing Address is invalidated. If Address + Length is not\r
+ aligned on a cache line boundary, then the entire instruction cache line\r
+ containing Address + Length -1 is invalidated. This function may choose to\r
+ invalidate the entire instruction cache if that is more efficient than\r
+ invalidating the specified range. If Length is 0, the no instruction cache\r
+ lines are invalidated. Address is returned.\r
+\r
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+ @param Address The base address of the instruction cache lines to\r
+ invalidate. If the CPU is in a physical addressing mode, then\r
+ Address is a physical address. If the CPU is in a virtual\r
+ addressing mode, then Address is a virtual address.\r
+\r
+ @param Length The number of bytes to invalidate from the instruction cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+InvalidateInstructionCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ return IpfInvalidateInstructionCacheRange (Address, Length);\r
+}\r
+\r
/**\r
Writes Back and Invalidates the entire data cache in cache coherency domain\r
of the calling CPU.\r
-<?xml version="1.0" encoding="UTF-8"?>\r
+<?xml version="1.0" encoding="UTF-8"?>\r
<!--\r
Copyright (c) 2006, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
<Filename SupArchList="IPF">Ipf/CpuFlushTlb.s</Filename>\r
<Filename SupArchList="IPF">Ipf/GetInterruptState.s</Filename>\r
<Filename SupArchList="IPF">Ipf/Non-existing.c</Filename>\r
+ <Filename SupArchList="IPF">Ipf/InvalidateInstructionCacheRange.s</Filename>\r
+ <Filename SupArchList="IPF">Ipf/ReadItc.s</Filename>\r
\r
<Filename SupArchList="EBC">Math64.c</Filename>\r
<Filename SupArchList="EBC">Unaligned.c</Filename>\r
#pragma intrinsic (__break)\r
#pragma intrinsic (__mfa)\r
\r
-typedef struct {\r
- UINT64 Status;\r
- UINT64 r9;\r
- UINT64 r10;\r
- UINT64 r11;\r
-} PAL_PROC_RETURN;\r
-\r
-PAL_PROC_RETURN\r
-PalCallStatic (\r
- IN CONST VOID *PalEntryPoint,\r
- IN UINT64 Arg1,\r
- IN UINT64 Arg2,\r
- IN UINT64 Arg3,\r
- IN UINT64 Arg4\r
- );\r
\r
/**\r
Generates a breakpoint on the CPU.\r
<?xml version="1.0" encoding="UTF-8"?>\r
-<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0">\r
+<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">\r
<MsaHeader>\r
<ModuleName>BaseTimerLibLocalApic</ModuleName>\r
<ModuleType>BASE</ModuleType>\r
<GuidValue>b5a05743-9b71-489b-a0ed-a0eb3950d23b</GuidValue>\r
<Version>1.0</Version>\r
<Abstract>Component description file for Baser Timer Library</Abstract>\r
- <Description>Timer Library that only uses CPU resources to provide calibrated\r
+ <Description>Timer Library that only uses CPU resources to provide calibrated
delays on IA-32 and x64.</Description>\r
<Copyright>Copyright (c) 2006, Intel Corporation.</Copyright>\r
- <License>All rights reserved. This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ <License>All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>\r
<Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION 0x00000052</Specification>\r
</MsaHeader>\r
<SourceFiles>\r
<Filename SupArchList="IA32">x86TimerLib.c</Filename>\r
<Filename SupArchList="X64">x86TimerLib.c</Filename>\r
- <Filename SupArchList="IPF">Ipf/PalCallStatic.s</Filename>\r
- <Filename SupArchList="IPF">Ipf/ReadItc.s</Filename>\r
<Filename SupArchList="IPF">Ipf/IpfTimerLib.c</Filename>\r
<Filename SupArchList="EBC">Ebc/EbcTimerLib.c</Filename>\r
</SourceFiles>\r
\r
**/\r
\r
-typedef struct {\r
- UINT64 Status;\r
- UINT64 r9;\r
- UINT64 r10;\r
- UINT64 r11;\r
-} PAL_PROC_RETURN;\r
\r
-/**\r
- Performs a PAL call using static calling convention.\r
-\r
- An internal function to perform a PAL call using static calling convention.\r
-\r
- @param PalEntryPoint The entry point address of PAL. The address in ar.kr5\r
- would be used if this parameter were NULL on input.\r
- @param Arg1 The first argument of a PAL call.\r
- @param Arg1 The second argument of a PAL call.\r
- @param Arg1 The third argument of a PAL call.\r
- @param Arg1 The fourth argument of a PAL call.\r
-\r
- @return The values returned in r8, r9, r10 and r11.\r
-\r
-**/\r
-PAL_PROC_RETURN\r
-PalCallStatic (\r
- IN CONST VOID *PalEntryPoint,\r
- IN UINT64 Arg1,\r
- IN UINT64 Arg2,\r
- IN UINT64 Arg3,\r
- IN UINT64 Arg4\r
- );\r
\r
-/**\r
- Returns the current value of ar.itc.\r
-\r
- An internal function to return the current value of ar.itc, which is the\r
- timer tick on IPF.\r
-\r
- @return The currect value of ar.itc\r
-\r
-**/\r
-INT64\r
-InternalIpfReadItc (\r
- VOID\r
- );\r
\r
/**\r
Performs a delay measured as number of ticks.\r
//\r
// The target timer count is calculated here\r
//\r
- Ticks = InternalIpfReadItc () + Delay;\r
+ Ticks = IpfReadItc () + Delay;\r
\r
//\r
// Wait until time out\r
// Delay > 2^63 could not be handled by this function\r
// Timer wrap-arounds are handled correctly by this function\r
//\r
- while (Ticks - InternalIpfReadItc () >= 0);\r
+ while (Ticks - IpfReadItc () >= 0);\r
}\r
\r
/**\r
VOID\r
)\r
{\r
- return InternalIpfReadItc ();\r
+ return IpfReadItc ();\r
}\r
\r
/**\r
+++ /dev/null
-/// @file\r
-/// Contains an implementation of CallPalProcStatic on Itanium-based\r
-/// architecture.\r
-///\r
-/// Copyright (c) 2006, Intel Corporation\r
-/// All rights reserved. This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: PalCallStatic.s\r
-///\r
-///\r
-\r
-.auto\r
-.text\r
-\r
-.proc PalCallStatic\r
-.type PalCallStatic, @function\r
-.regstk 5, 0, 0, 0\r
-PalCallStatic::\r
- cmp.eq p15 = in0, r0\r
- mov r31 = in4\r
- mov r8 = ip\r
-\r
-(p15) mov in0 = ar.k5\r
- add r8 = (_PalProcReturn - PalCallStatic), r8\r
- mov r30 = in3\r
-\r
- mov in4 = psr\r
- mov in3 = b0\r
- mov b7 = in0\r
-\r
- rsm 1 << 14 // Disable interrupts\r
- mov r29 = in2\r
- mov r28 = in1\r
-\r
- mov b0 = r8\r
- br.cond.sptk.many b7\r
-\r
-_PalProcReturn:\r
- mov psr.l = in4\r
- mov b0 = in3\r
- br.ret.sptk.many b0\r
-.endp PalCallStatic\r
+++ /dev/null
-/// @file\r
-/// Contains an implementation of InternalIpfReadItc () on Itanium-based\r
-/// architecture.\r
-///\r
-/// Copyright (c) 2006, Intel Corporation\r
-/// All rights reserved. This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: ReadItc.s\r
-///\r
-///\r
-\r
-.auto\r
-.text\r
-\r
-.proc InternalIpfReadItc\r
-.type InternalIpfReadItc, @function\r
-InternalIpfReadItc::\r
- mov r8 = ar.itc\r
- br.ret.sptk.many b0\r
-.endp InternalIpfReadItc\r
projects / mirror_edk2.git / commitdiff