OvmfPkg: PlatformPei: beautify memory HOB order in QemuInitializeRam()

Build the memory HOBs in a tight block, in increasing base address order.

Cc: Maoming <maoming.maoming@huawei.com>
Cc: Huangpeng (Peter) <peter.huangpeng@huawei.com>
Cc: Wei Liu <wei.liu2@citrix.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Maoming <maoming.maoming@huawei.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17721 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index ceff1e256385be7f78c619288a77bddb1b58e2aa..b74308f5625e6701d007a332ee512a91cfb2c782 100644 (file)
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -265,8 +265,11 @@ QemuInitializeRam (
     //\r
     // Create memory HOBs\r
     //\r
-    AddMemoryRangeHob (BASE_1MB, LowerMemorySize);\r
     AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);\r
+    AddMemoryRangeHob (BASE_1MB, LowerMemorySize);\r
+    if (UpperMemorySize != 0) {\r
+      AddUntestedMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);\r
+    }\r
   }\r
 \r
   MtrrSetMemoryAttribute (BASE_1MB, LowerMemorySize - BASE_1MB, CacheWriteBack);\r
@@ -274,10 +277,6 @@ QemuInitializeRam (
   MtrrSetMemoryAttribute (0, BASE_512KB + BASE_128KB, CacheWriteBack);\r
 \r
   if (UpperMemorySize != 0) {\r
-    if (mBootMode != BOOT_ON_S3_RESUME) {\r
-      AddUntestedMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);\r
-    }\r
-\r
     MtrrSetMemoryAttribute (BASE_4GB, UpperMemorySize, CacheWriteBack);\r
   }\r
 }\r