UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Add new MSR.

Changes includes:
  1. Add new MSRs: MSR_IA32_L2_QOS_CFG/MSR_IA32_CSTAR.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>

diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index 5d2242aa80e4bfdfab501d677c294cd359ef259e..b467ffaf2664cc0316b846aee6db2f0a81d89901 100644 (file)
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -5908,6 +5908,51 @@ typedef union {
   UINT64  Uint64;\r
 } MSR_IA32_L3_QOS_CFG_REGISTER;\r
 \r
+/**\r
+  L2 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=2):ECX.[2] = 1 ).\r
+\r
+  @param  ECX  MSR_IA32_L2_QOS_CFG (0x00000C82)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+               Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+               Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  MSR_IA32_L2_QOS_CFG_REGISTER  Msr;\r
+\r
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L2_QOS_CFG);\r
+  AsmWriteMsr64 (MSR_IA32_L2_QOS_CFG, Msr.Uint64);\r
+  @endcode\r
+  @note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM.\r
+**/\r
+#define MSR_IA32_L2_QOS_CFG                      0x00000C82\r
+\r
+/**\r
+  MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    ///\r
+    /// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate\r
+    /// in Code and Data Prioritization (CDP) mode.\r
+    ///\r
+    UINT32  Enable:1;\r
+    UINT32  Reserved1:31;\r
+    UINT32  Reserved2:32;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 32-bit value\r
+  ///\r
+  UINT32  Uint32;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} MSR_IA32_L2_QOS_CFG_REGISTER;\r
 \r
 /**\r
   Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]\r
@@ -6380,6 +6425,25 @@ typedef union {
 **/\r
 #define MSR_IA32_LSTAR                           0xC0000082\r
 \r
+/**\r
+  IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL\r
+  instruction is not recognized in compatibility mode. If\r
+  CPUID.80000001:EDX.[29] = 1.\r
+\r
+  @param  ECX  MSR_IA32_CSTAR (0xC0000083)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_IA32_CSTAR);\r
+  AsmWriteMsr64 (MSR_IA32_CSTAR, Msr);\r
+  @endcode\r
+  @note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM.\r
+**/\r
+#define MSR_IA32_CSTAR                           0xC0000083\r
 \r
 /**\r
   System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.\r