for (Count = 0; Count < Units; Count++) {\r
ASSERT (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));\r
\r
- Block->Bits[Byte] |= USB_HC_BIT (Bit);\r
+ Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | USB_HC_BIT (Bit));\r
NEXT_BIT (Byte, Bit);\r
}\r
\r
for (Count = 0; Count < Units; Count++) {\r
ASSERT (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));\r
\r
- Block->Bits[Byte] |= USB_HC_BIT (Bit);\r
+ Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | (UINT8) USB_HC_BIT (Bit));\r
NEXT_BIT (Byte, Bit);\r
}\r
\r
EFIAPI\r
PeiCore (\r
IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,\r
- IN CONST EFI_PEI_PPI_DESCRIPTOR *PpList,\r
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList,\r
IN VOID *Data\r
)\r
/*++\r
//\r
// If SEC provided any PPI services to PEI, install them.\r
//\r
- if (PpList != NULL) {\r
- Status = PeiServicesInstallPpi (PpList);\r
+ if (PpiList != NULL) {\r
+ Status = PeiServicesInstallPpi (PpiList);\r
ASSERT_EFI_ERROR (Status);\r
}\r
}\r
//\r
STATIC FVB_ENTRY *mFvbEntry;\r
STATIC EFI_EVENT mFvbRegistration;\r
-STATIC BOOLEAN mEfiFvbInitialized = FALSE;\r
STATIC UINTN mFvbCount;\r
\r
/**\r
);\r
ASSERT_EFI_ERROR (Status);\r
\r
- mEfiFvbInitialized = TRUE;\r
-\r
return EFI_SUCCESS;\r
}\r
\r
//\r
STATIC FVB_ENTRY *mFvbEntry;\r
STATIC EFI_EVENT mFvbRegistration;\r
-STATIC BOOLEAN mEfiFvbInitialized = FALSE;\r
STATIC UINTN mFvbCount;\r
\r
/**\r
);\r
ASSERT_EFI_ERROR (Status);\r
\r
- mEfiFvbInitialized = TRUE;\r
-\r
return EFI_SUCCESS;\r
}\r
\r
Vendor = (VENDOR_DEVICE_PATH *) CreateDeviceNode (\r
Type,\r
SubType,\r
- sizeof (VENDOR_DEVICE_PATH) + (UINT16) Length\r
+ (UINT16) (sizeof (VENDOR_DEVICE_PATH) + Length)\r
);\r
\r
StrToGuid (GuidStr, &Vendor->Guid);\r
HIDStr = GetNextParamStr (&TextDeviceNode);\r
CIDStr = GetNextParamStr (&TextDeviceNode);\r
UIDSTRStr = GetNextParamStr (&TextDeviceNode);\r
- Length = sizeof (ACPI_EXTENDED_HID_DEVICE_PATH) + (UINT16) StrLen (UIDSTRStr) + 3;\r
+ Length = (UINT16) (sizeof (ACPI_EXTENDED_HID_DEVICE_PATH) + StrLen (UIDSTRStr) + 3);\r
AcpiExt = (ACPI_EXTENDED_HID_DEVICE_PATH_WITH_STR *) CreateDeviceNode (\r
ACPI_DEVICE_PATH,\r
ACPI_EXTENDED_DP,\r
Info |= 0x0001;\r
} else {\r
Info |= 0x0002;\r
- Info |= (Xtoi (DriveBayStr) << 8);\r
+ Info = (UINT16) (Info | (Xtoi (DriveBayStr) << 8));\r
}\r
\r
if (StrCmp (SASSATAStr, L"SATA") == 0) {\r
iSCSI = (ISCSI_DEVICE_PATH_WITH_NAME *) CreateDeviceNode (\r
MESSAGING_DEVICE_PATH,\r
MSG_ISCSI_DP,\r
- sizeof (ISCSI_DEVICE_PATH_WITH_NAME) + (UINT16) (StrLen (NameStr) * 2)\r
+ (UINT16) (sizeof (ISCSI_DEVICE_PATH_WITH_NAME) + StrLen (NameStr) * 2)\r
);\r
\r
StrCpy (iSCSI->iSCSITargetName, NameStr);\r
File = (FILEPATH_DEVICE_PATH *) CreateDeviceNode (\r
MEDIA_DEVICE_PATH,\r
MEDIA_FILEPATH_DP,\r
- sizeof (FILEPATH_DEVICE_PATH) + (UINT16) (StrLen (TextDeviceNode) * 2)\r
+ (UINT16) (sizeof (FILEPATH_DEVICE_PATH) + StrLen (TextDeviceNode) * 2)\r
);\r
\r
StrCpy (File->PathName, TextDeviceNode);\r
Bbs = (BBS_BBS_DEVICE_PATH *) CreateDeviceNode (\r
BBS_DEVICE_PATH,\r
BBS_BBS_DP,\r
- sizeof (BBS_BBS_DEVICE_PATH) + (UINT16) (StrLen (IdStr))\r
+ (UINT16) (sizeof (BBS_BBS_DEVICE_PATH) + StrLen (IdStr))\r
);\r
\r
if (StrCmp (TypeStr, L"Floppy") == 0) {\r
\r
Option->Flag = 0;\r
\r
- TotalLen = (Tcp->HeadLen << 2) - sizeof (TCP_HEAD);\r
+ TotalLen = (UINT8) ((Tcp->HeadLen << 2) - sizeof (TCP_HEAD));\r
if (TotalLen <= 0) {\r
return 0;\r
}\r
IoHighLevel.c\r
IoLibGcc.c | GCC\r
IoLibMsc.c | MSFT\r
+ IoLibIcc.c | INTEL\r
IoLib.c\r
\r
[Sources.X64]\r
IoHighLevel.c\r
IoLibGcc.c | GCC\r
IoLibMsc.c | MSFT\r
+ IoLibIcc.c | INTEL\r
IoLib.c\r
\r
[Sources.IPF]\r
--- /dev/null
+/** @file\r
+ I/O Library. This file has compiler specifics for ICC as there\r
+ is no ANSI C standard for doing IO.\r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation<BR> All rights\r
+ reserved. This program and the accompanying materials are\r
+ licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+#include "BaseIoLibIntrinsicInternal.h"\r
+\r
+/**\r
+ Reads an 8-bit MMIO register.\r
+\r
+ Reads the 8-bit MMIO register specified by Address. The 8-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ If 8-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioRead8 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ return *(volatile UINT8*)Address;\r
+}\r
+\r
+/**\r
+ Writes an 8-bit MMIO register.\r
+\r
+ Writes the 8-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ If 8-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Value The value to write to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioWrite8 (\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ return *(volatile UINT8*)Address = Value;\r
+}\r
+\r
+/**\r
+ Reads a 16-bit MMIO register.\r
+\r
+ Reads the 16-bit MMIO register specified by Address. The 16-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ If 16-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioRead16 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ ASSERT ((Address & 1) == 0);\r
+ return *(volatile UINT16*)Address;\r
+}\r
+\r
+/**\r
+ Writes a 16-bit MMIO register.\r
+\r
+ Writes the 16-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ If 16-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Value The value to write to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioWrite16 (\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ ASSERT ((Address & 1) == 0);\r
+ return *(volatile UINT16*)Address = Value;\r
+}\r
+\r
+/**\r
+ Reads a 32-bit MMIO register.\r
+\r
+ Reads the 32-bit MMIO register specified by Address. The 32-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ If 32-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioRead32 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ ASSERT ((Address & 3) == 0);\r
+ return *(volatile UINT32*)Address;\r
+}\r
+\r
+/**\r
+ Writes a 32-bit MMIO register.\r
+\r
+ Writes the 32-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ If 32-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Value The value to write to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioWrite32 (\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ ASSERT ((Address & 3) == 0);\r
+ return *(volatile UINT32*)Address = Value;\r
+}\r
+\r
+/**\r
+ Reads a 64-bit MMIO register.\r
+\r
+ Reads the 64-bit MMIO register specified by Address. The 64-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ If 64-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioRead64 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ ASSERT ((Address & 7) == 0);\r
+ return *(volatile UINT64*)Address;\r
+}\r
+\r
+/**\r
+ Writes a 64-bit MMIO register.\r
+\r
+ Writes the 64-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ If 64-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Value The value to write to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioWrite64 (\r
+ IN UINTN Address,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ ASSERT ((Address & 7) == 0);\r
+ return *(volatile UINT64*)Address = Value;\r
+}\r
+\r
+\r
+\r
+/**\r
+ Reads an 8-bit I/O port.\r
+\r
+ Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ If 8-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoRead8 (\r
+ IN UINTN Port\r
+ )\r
+{\r
+ UINT8 Data;\r
+\r
+ __asm {\r
+ mov dx, word ptr [Port]\r
+ in al, dx\r
+\r
+ mov Data, al\r
+ }\r
+ return Data;\r
+}\r
+\r
+/**\r
+ Writes an 8-bit I/O port.\r
+\r
+ Writes the 8-bit I/O port specified by Port with the value specified by Value\r
+ and returns Value. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 8-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param Value The value to write to the I/O port.\r
+\r
+ @return The value written the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoWrite8 (\r
+ IN UINTN Port,\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ __asm {\r
+ mov al, byte ptr [Value]\r
+ mov dx, word ptr [Port]\r
+ out dx, al\r
+ }\r
+ return Value; \r
+}\r
+\r
+/**\r
+ Reads a 16-bit I/O port.\r
+\r
+ Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ If 16-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoRead16 (\r
+ IN UINTN Port\r
+ )\r
+{\r
+ UINT16 Data;\r
+\r
+ ASSERT ((Port & 1) == 0);\r
+\r
+ __asm {\r
+ mov dx, word ptr [Port]\r
+ in ax, dx\r
+ mov word ptr [Data], ax\r
+ }\r
+\r
+ return Data;\r
+}\r
+\r
+/**\r
+ Writes a 16-bit I/O port.\r
+\r
+ Writes the 16-bit I/O port specified by Port with the value specified by Value\r
+ and returns Value. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 16-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param Value The value to write to the I/O port.\r
+\r
+ @return The value written the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoWrite16 (\r
+ IN UINTN Port,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ ASSERT ((Port & 1) == 0);\r
+\r
+ __asm {\r
+ mov ax, word ptr [Value]\r
+ mov dx, word ptr [Port]\r
+ out dx, ax\r
+ }\r
+\r
+ //\r
+ // Never reached return statement.\r
+ //\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Reads a 32-bit I/O port.\r
+\r
+ Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ If 32-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoRead32 (\r
+ IN UINTN Port\r
+ )\r
+{\r
+ UINT32 Data;\r
+\r
+ ASSERT ((Port & 3) == 0);\r
+\r
+ __asm {\r
+ mov dx, word ptr [Port]\r
+ in eax, dx\r
+ mov dword ptr [Data], eax\r
+ }\r
+ \r
+ return Data;\r
+}\r
+\r
+/**\r
+ Writes a 32-bit I/O port.\r
+\r
+ Writes the 32-bit I/O port specified by Port with the value specified by Value\r
+ and returns Value. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 32-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param Value The value to write to the I/O port.\r
+\r
+ @return The value written the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoWrite32 (\r
+ IN UINTN Port,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ ASSERT ((Port & 3) == 0);\r
+ \r
+ __asm {\r
+ mov eax, dword ptr [Value]\r
+ mov dx, word ptr [Port]\r
+ out dx, eax\r
+ }\r
+\r
+ return Value;\r
+}\r
+\r
Ia32/WriteCr2.c | MSFT \r
Ia32/WriteCr0.c | MSFT \r
Ia32/WriteMsr64.c | MSFT \r
- Ia32/Thunk16.asm\r
Ia32/SwapBytes64.c | MSFT \r
Ia32/SetJump.c | MSFT \r
Ia32/RRotU64.c | MSFT \r
Ia32/FxRestore.c | MSFT \r
Ia32/FxSave.c | MSFT \r
Ia32/FlushCacheLine.c | MSFT \r
- Ia32/EnablePaging64.asm\r
Ia32/EnablePaging32.c | MSFT \r
Ia32/EnableInterrupts.c | MSFT \r
Ia32/EnableDisableInterrupts.c | MSFT \r
Ia32/CpuFlushTlb.c | MSFT \r
Ia32/CpuBreakpoint.c | MSFT \r
Ia32/ARShiftU64.c | MSFT \r
+ SynchronizationMsc.c | MSFT\r
+\r
+ Ia32/Wbinvd.asm | INTEL \r
+ Ia32/WriteMm7.asm | INTEL \r
+ Ia32/WriteMm6.asm | INTEL \r
+ Ia32/WriteMm5.asm | INTEL \r
+ Ia32/WriteMm4.asm | INTEL \r
+ Ia32/WriteMm3.asm | INTEL \r
+ Ia32/WriteMm2.asm | INTEL \r
+ Ia32/WriteMm1.asm | INTEL \r
+ Ia32/WriteMm0.asm | INTEL \r
+ Ia32/WriteLdtr.asm | INTEL \r
+ Ia32/WriteIdtr.asm | INTEL \r
+ Ia32/WriteGdtr.asm | INTEL \r
+ Ia32/WriteDr7.asm | INTEL \r
+ Ia32/WriteDr6.asm | INTEL \r
+ Ia32/WriteDr5.asm | INTEL \r
+ Ia32/WriteDr4.asm | INTEL \r
+ Ia32/WriteDr3.asm | INTEL \r
+ Ia32/WriteDr2.asm | INTEL \r
+ Ia32/WriteDr1.asm | INTEL \r
+ Ia32/WriteDr0.asm | INTEL \r
+ Ia32/WriteCr4.asm | INTEL \r
+ Ia32/WriteCr3.asm | INTEL \r
+ Ia32/WriteCr2.asm | INTEL \r
+ Ia32/WriteCr0.asm | INTEL \r
+ Ia32/WriteMsr64.asm | INTEL \r
+ Ia32/SwapBytes64.asm | INTEL \r
+ Ia32/SetJump.asm | INTEL \r
+ Ia32/RRotU64.asm | INTEL \r
+ Ia32/RShiftU64.asm | INTEL \r
+ Ia32/ReadPmc.asm | INTEL \r
+ Ia32/ReadTsc.asm | INTEL \r
+ Ia32/ReadLdtr.asm | INTEL \r
+ Ia32/ReadIdtr.asm | INTEL \r
+ Ia32/ReadGdtr.asm | INTEL \r
+ Ia32/ReadTr.asm | INTEL \r
+ Ia32/ReadSs.asm | INTEL \r
+ Ia32/ReadGs.asm | INTEL \r
+ Ia32/ReadFs.asm | INTEL \r
+ Ia32/ReadEs.asm | INTEL \r
+ Ia32/ReadDs.asm | INTEL \r
+ Ia32/ReadCs.asm | INTEL \r
+ Ia32/ReadMsr64.asm | INTEL \r
+ Ia32/ReadMm7.asm | INTEL \r
+ Ia32/ReadMm6.asm | INTEL \r
+ Ia32/ReadMm5.asm | INTEL \r
+ Ia32/ReadMm4.asm | INTEL \r
+ Ia32/ReadMm3.asm | INTEL \r
+ Ia32/ReadMm2.asm | INTEL \r
+ Ia32/ReadMm1.asm | INTEL \r
+ Ia32/ReadMm0.asm | INTEL \r
+ Ia32/ReadEflags.asm | INTEL \r
+ Ia32/ReadDr7.asm | INTEL \r
+ Ia32/ReadDr6.asm | INTEL \r
+ Ia32/ReadDr5.asm | INTEL \r
+ Ia32/ReadDr4.asm | INTEL \r
+ Ia32/ReadDr3.asm | INTEL \r
+ Ia32/ReadDr2.asm | INTEL \r
+ Ia32/ReadDr1.asm | INTEL \r
+ Ia32/ReadDr0.asm | INTEL \r
+ Ia32/ReadCr4.asm | INTEL \r
+ Ia32/ReadCr3.asm | INTEL \r
+ Ia32/ReadCr2.asm | INTEL \r
+ Ia32/ReadCr0.asm | INTEL \r
+ Ia32/Mwait.asm | INTEL \r
+ Ia32/Monitor.asm | INTEL \r
+ Ia32/ModU64x32.asm | INTEL \r
+ Ia32/MultU64x64.asm | INTEL \r
+ Ia32/MultU64x32.asm | INTEL \r
+ Ia32/LShiftU64.asm | INTEL \r
+ Ia32/LRotU64.asm | INTEL \r
+ Ia32/LongJump.asm | INTEL \r
+ Ia32/Invd.asm | INTEL \r
+ Ia32/InterlockedCompareExchange64.asm | INTEL \r
+ Ia32/InterlockedCompareExchange32.asm | INTEL \r
+ Ia32/InterlockedDecrement.asm | INTEL \r
+ Ia32/InterlockedIncrement.asm | INTEL \r
+ Ia32/FxRestore.asm | INTEL \r
+ Ia32/FxSave.asm | INTEL \r
+ Ia32/FlushCacheLine.asm | INTEL \r
+ Ia32/EnablePaging32.asm | INTEL \r
+ Ia32/EnableInterrupts.asm | INTEL \r
+ Ia32/EnableDisableInterrupts.asm | INTEL \r
+ Ia32/DivU64x64Remainder.asm | INTEL \r
+ Ia32/DivU64x32Remainder.asm | INTEL \r
+ Ia32/DivU64x32.asm | INTEL \r
+ Ia32/DisablePaging32.asm | INTEL \r
+ Ia32/DisableInterrupts.asm | INTEL \r
+ Ia32/CpuPause.asm | INTEL \r
+ Ia32/CpuIdEx.asm | INTEL \r
+ Ia32/CpuId.asm | INTEL \r
+ Ia32/CpuSleep.asm | INTEL \r
+ Ia32/CpuFlushTlb.asm | INTEL \r
+ Ia32/CpuBreakpoint.asm | INTEL \r
+ Ia32/ARShiftU64.asm | INTEL \r
+ Synchronization.c | INTEL\r
+\r
+ Ia32/Thunk16.asm\r
+ Ia32/EnablePaging64.asm\r
+\r
Ia32/Thunk16.S | GCC \r
Ia32/CpuFlushTlb.S | GCC \r
Ia32/CpuBreakpoint.S | GCC \r
Ia32/ARShiftU64.S | GCC \r
Ia32/RShiftU64.S | GCC \r
Ia32/LShiftU64.S | GCC \r
+ SynchronizationGcc.c | GCC\r
+\r
Ia32/DivS64x64Remainder.c\r
Ia32/InternalSwitchStack.c\r
Ia32/Non-existing.c\r
x86EnablePaging32.c\r
x86DisablePaging64.c\r
x86DisablePaging32.c\r
- Synchronization.c | INTEL\r
- SynchronizationMsc.c | MSFT\r
- SynchronizationGcc.c | GCC\r
\r
[Sources.X64]\r
X64/Thunk16.asm\r
X64/CpuFlushTlb.asm\r
- X64/CpuBreakpoint.c | MSFT \r
X64/CpuPause.asm\r
X64/CpuSleep.asm\r
X64/EnableDisableInterrupts.asm\r
X64/DisableInterrupts.asm\r
X64/EnableInterrupts.asm\r
- X64/InterlockedCompareExchange64.asm | MSFT \r
- X64/InterlockedCompareExchange32.asm | MSFT \r
- X64/InterlockedDecrement.c | MSFT \r
- X64/InterlockedIncrement.c | MSFT \r
X64/FlushCacheLine.asm\r
X64/Invd.asm\r
X64/Wbinvd.asm\r
X64/ReadCr3.asm\r
X64/ReadCr2.asm\r
X64/ReadCr0.asm\r
- X64/WriteMsr64.c | MSFT \r
- X64/ReadMsr64.c | MSFT \r
X64/ReadEflags.asm\r
X64/CpuIdEx.asm\r
X64/CpuId.asm\r
X64/LongJump.asm\r
X64/SetJump.asm\r
X64/SwitchStack.asm\r
+ X64/InterlockedCompareExchange64.asm \r
+ X64/InterlockedCompareExchange32.asm \r
+\r
+ X64/InterlockedDecrement.c | MSFT \r
+ X64/InterlockedIncrement.c | MSFT \r
+ X64/CpuBreakpoint.c | MSFT \r
+ X64/WriteMsr64.c | MSFT \r
+ X64/ReadMsr64.c | MSFT \r
+ SynchronizationMsc.c | MSFT \r
+\r
+ X64/InterlockedDecrement.asm | INTEL \r
+ X64/InterlockedIncrement.asm | INTEL \r
+ X64/CpuBreakpoint.asm | INTEL \r
+ X64/WriteMsr64.asm | INTEL \r
+ X64/ReadMsr64.asm | INTEL \r
+ Synchronization.c | INTEL \r
+\r
X64/Non-existing.c\r
Math64.c\r
Unaligned.c\r
X64/CpuIdEx.S | GCC \r
X64/CpuFlushTlb.S | GCC \r
X64/CpuBreakpoint.S | GCC \r
- Synchronization.c | INTEL \r
- SynchronizationMsc.c | MSFT \r
SynchronizationGcc.c | GCC \r
\r
[Sources.IPF]\r
IN CONST GUID *Guid2\r
)\r
{\r
- return (BOOLEAN)(\r
- ReadUnaligned64 ((CONST UINT64*)Guid1)\r
- == ReadUnaligned64 ((CONST UINT64*)Guid2) &&\r
- ReadUnaligned64 ((CONST UINT64*)Guid1 + 1)\r
- == ReadUnaligned64 ((CONST UINT64*)Guid2 + 1)\r
+ UINT64 Guid1ValueLo;\r
+ UINT64 Guid1ValueHi;\r
+ UINT64 Guid2ValueLo;\r
+ UINT64 Guid2ValueHi;\r
+\r
+ Guid1ValueLo = ReadUnaligned64 ((CONST UINT64*)Guid1);\r
+ Guid2ValueLo = ReadUnaligned64 ((CONST UINT64*)Guid2);\r
+\r
+ Guid1ValueHi = ReadUnaligned64 ((CONST UINT64*)Guid1 + 1);\r
+ Guid2ValueHi = ReadUnaligned64 ((CONST UINT64*)Guid2 + 1);\r
+\r
+\r
+ return (BOOLEAN)\r
+ ((Guid1ValueLo == Guid2ValueLo) &&\r
+ (Guid1ValueHi == Guid2ValueHi)\r
);\r
}\r
\r
IN CONST GUID *Guid2\r
)\r
{\r
- return (BOOLEAN)(\r
- ReadUnaligned64 ((CONST UINT64*)Guid1)\r
- == ReadUnaligned64 ((CONST UINT64*)Guid2) &&\r
- ReadUnaligned64 ((CONST UINT64*)Guid1 + 1)\r
- == ReadUnaligned64 ((CONST UINT64*)Guid2 + 1)\r
+ UINT64 Guid1ValueLo;\r
+ UINT64 Guid1ValueHi;\r
+ UINT64 Guid2ValueLo;\r
+ UINT64 Guid2ValueHi;\r
+\r
+ Guid1ValueLo = ReadUnaligned64 ((CONST UINT64*)Guid1);\r
+ Guid2ValueLo = ReadUnaligned64 ((CONST UINT64*)Guid2);\r
+\r
+ Guid1ValueHi = ReadUnaligned64 ((CONST UINT64*)Guid1 + 1);\r
+ Guid2ValueHi = ReadUnaligned64 ((CONST UINT64*)Guid2 + 1);\r
+\r
+\r
+ return (BOOLEAN)\r
+ ((Guid1ValueLo == Guid2ValueLo) &&\r
+ (Guid1ValueHi == Guid2ValueHi)\r
);\r
}\r
\r