--- /dev/null
+/** @file\r
+ EFI SMM CPU Protocol as defined in the PI 1.2 specification.\r
+\r
+ This protocol allows SMM drivers to access architecture-standard registers from any of the CPU \r
+ save state areas. In some cases, difference processors provide the same information in the save state, \r
+ but not in the same format. These so-called pseudo-registers provide this information in a standard \r
+ format. \r
+\r
+ Copyright (c) 2009, Intel Corporation \r
+ All rights reserved. This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+**/\r
+\r
+#ifndef _SMM_CPU_H_\r
+#define _SMM_CPU_H_\r
+\r
+#include <Pi/PiSmmCis.h>\r
+\r
+#define EFI_SMM_CPU_PROTOCOL_GUID \\r
+ { \\r
+ 0xeb346b97, 0x975f, 0x4a9f, { 0x8b, 0x22, 0xf8, 0xe9, 0x2b, 0xb3, 0xd5, 0x69 } \\r
+ }\r
+\r
+///\r
+/// Save State register index\r
+///\r
+typedef enum {\r
+ ///\r
+ /// x86/X64 standard registers\r
+ ///\r
+ EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4,\r
+ EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5,\r
+ EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6,\r
+ EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7,\r
+ EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8,\r
+ EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9,\r
+ EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10,\r
+ EFI_SMM_SAVE_STATE_REGISTER_ES = 20,\r
+ EFI_SMM_SAVE_STATE_REGISTER_CS = 21,\r
+ EFI_SMM_SAVE_STATE_REGISTER_SS = 22,\r
+ EFI_SMM_SAVE_STATE_REGISTER_DS = 23,\r
+ EFI_SMM_SAVE_STATE_REGISTER_FS = 24,\r
+ EFI_SMM_SAVE_STATE_REGISTER_GS = 25,\r
+ EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26,\r
+ EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27,\r
+ EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28,\r
+ EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29,\r
+ EFI_SMM_SAVE_STATE_REGISTER_R8 = 30,\r
+ EFI_SMM_SAVE_STATE_REGISTER_R9 = 31,\r
+ EFI_SMM_SAVE_STATE_REGISTER_R10 = 32,\r
+ EFI_SMM_SAVE_STATE_REGISTER_R11 = 33,\r
+ EFI_SMM_SAVE_STATE_REGISTER_R12 = 34,\r
+ EFI_SMM_SAVE_STATE_REGISTER_R13 = 35,\r
+ EFI_SMM_SAVE_STATE_REGISTER_R14 = 36,\r
+ EFI_SMM_SAVE_STATE_REGISTER_R15 = 37, \r
+ EFI_SMM_SAVE_STATE_REGISTER_RAX = 38,\r
+ EFI_SMM_SAVE_STATE_REGISTER_RBX = 39,\r
+ EFI_SMM_SAVE_STATE_REGISTER_RCX = 40,\r
+ EFI_SMM_SAVE_STATE_REGISTER_RDX = 41,\r
+ EFI_SMM_SAVE_STATE_REGISTER_RSP = 42,\r
+ EFI_SMM_SAVE_STATE_REGISTER_RBP = 43,\r
+ EFI_SMM_SAVE_STATE_REGISTER_RSI = 44,\r
+ EFI_SMM_SAVE_STATE_REGISTER_RDI = 45,\r
+ EFI_SMM_SAVE_STATE_REGISTER_RIP = 46,\r
+ EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51,\r
+ EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52,\r
+ EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53,\r
+ EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54,\r
+ EFI_SMM_SAVE_STATE_REGISTER_FCW = 256,\r
+ EFI_SMM_SAVE_STATE_REGISTER_FSW = 257,\r
+ EFI_SMM_SAVE_STATE_REGISTER_FTW = 258, \r
+ EFI_SMM_SAVE_STATE_REGISTER_OPCODE = 259,\r
+ EFI_SMM_SAVE_STATE_REGISTER_FP_EIP = 260,\r
+ EFI_SMM_SAVE_STATE_REGISTER_FP_CS = 261,\r
+ EFI_SMM_SAVE_STATE_REGISTER_DATAOFFSET = 262,\r
+ EFI_SMM_SAVE_STATE_REGISTER_FP_DS = 263,\r
+ EFI_SMM_SAVE_STATE_REGISTER_MM0 = 264,\r
+ EFI_SMM_SAVE_STATE_REGISTER_MM1 = 265,\r
+ EFI_SMM_SAVE_STATE_REGISTER_MM2 = 266,\r
+ EFI_SMM_SAVE_STATE_REGISTER_MM3 = 267,\r
+ EFI_SMM_SAVE_STATE_REGISTER_MM4 = 268,\r
+ EFI_SMM_SAVE_STATE_REGISTER_MM5 = 269,\r
+ EFI_SMM_SAVE_STATE_REGISTER_MM6 = 270,\r
+ EFI_SMM_SAVE_STATE_REGISTER_MM7 = 271,\r
+ EFI_SMM_SAVE_STATE_REGISTER_XMM0 = 272,\r
+ EFI_SMM_SAVE_STATE_REGISTER_XMM1 = 273,\r
+ EFI_SMM_SAVE_STATE_REGISTER_XMM2 = 274,\r
+ EFI_SMM_SAVE_STATE_REGISTER_XMM3 = 275,\r
+ EFI_SMM_SAVE_STATE_REGISTER_XMM4 = 276,\r
+ EFI_SMM_SAVE_STATE_REGISTER_XMM5 = 277,\r
+ EFI_SMM_SAVE_STATE_REGISTER_XMM6 = 278,\r
+ EFI_SMM_SAVE_STATE_REGISTER_XMM7 = 279,\r
+ EFI_SMM_SAVE_STATE_REGISTER_XMM8 = 280,\r
+ EFI_SMM_SAVE_STATE_REGISTER_XMM9 = 281,\r
+ EFI_SMM_SAVE_STATE_REGISTER_XMM10 = 282,\r
+ EFI_SMM_SAVE_STATE_REGISTER_XMM11 = 283,\r
+ EFI_SMM_SAVE_STATE_REGISTER_XMM12 = 284,\r
+ EFI_SMM_SAVE_STATE_REGISTER_XMM13 = 285,\r
+ EFI_SMM_SAVE_STATE_REGISTER_XMM14 = 286,\r
+ EFI_SMM_SAVE_STATE_REGISTER_XMM15 = 287, \r
+ ///\r
+ /// Pseudo-Registers\r
+ ///\r
+ EFI_SMM_SAVE_STATE_REGISTER_IO = 512,\r
+ EFI_SMM_SAVE_STATE_REGISTER_LMA = 513\r
+} EFI_SMM_SAVE_STATE_REGISTER; \r
+\r
+///\r
+/// The EFI_SMM_SAVE_STATE_REGISTER_LMA pseudo-register values\r
+/// If the processor acts in 32-bit mode at the time the SMI occurred, the pseudo register value \r
+/// EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT is returned in Buffer. Otherwise, \r
+/// EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT is returned in Buffer.\r
+///\r
+#define EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT 32\r
+#define EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT 64\r
+\r
+///\r
+/// Size width of I/O instruction\r
+///\r
+typedef enum {\r
+ EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 = 0,\r
+ EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 = 1,\r
+ EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32 = 2,\r
+ EFI_SMM_SAVE_STATE_IO_WIDTH_UINT64 = 3\r
+} EFI_SMM_SAVE_STATE_IO_WIDTH;\r
+\r
+///\r
+/// Types of I/O instruction\r
+///\r
+typedef enum {\r
+ EFI_SMM_SAVE_STATE_IO_TYPE_INPUT = 1,\r
+ EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT = 2,\r
+ EFI_SMM_SAVE_STATE_IO_TYPE_STRING = 4,\r
+ EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX = 8\r
+} EFI_SMM_SAVE_STATE_IO_TYPE;\r
+\r
+///\r
+/// Structure of the data which is returned when ReadSaveState() is called with \r
+/// EFI_SMM_SAVE_STATE_REGISTER_IO. If there was no I/O then ReadSaveState() will \r
+/// return EFI_NOT_FOUND.\r
+///\r
+/// This structure describes the I/O operation which was in process when the SMI was generated.\r
+///\r
+typedef struct _EFI_SMM_SAVE_STATE_IO_INFO {\r
+ ///\r
+ /// For input instruction (IN, INS), this is data read before the SMI occurred. For output \r
+ /// instructions (OUT, OUTS) this is data that was written before the SMI occurred. The \r
+ /// width of the data is specified by IoWidth.\r
+ ///\r
+ /// Note: inconsistency with PI 1.2 spec here. wait for spec update.\r
+ ///\r
+ UINTN IoData;\r
+ ///\r
+ /// The I/O port that was being accessed when the SMI was triggered.\r
+ ///\r
+ UINT16 IoPort;\r
+ ///\r
+ /// Defines the size width (UINT8, UINT16, UINT32, UINT64) for IoData.\r
+ ///\r
+ EFI_SMM_SAVE_STATE_IO_WIDTH IoWidth;\r
+ ///\r
+ /// Defines type of I/O instruction.\r
+ ///\r
+ EFI_SMM_SAVE_STATE_IO_TYPE IoType;\r
+} EFI_SMM_SAVE_STATE_IO_INFO;\r
+ \r
+typedef struct _EFI_SMM_CPU_PROTOCOL EFI_SMM_CPU_PROTOCOL;\r
+\r
+/**\r
+ Read data from the CPU save state.\r
+\r
+ This function is used to read the specified number of bytes of the specified register from the CPU \r
+ save state of the specified CPU and place the value into the buffer. If the CPU does not support the\r
+ specified register Register, then EFI_NOT_FOUND should be returned. If the CPU does not \r
+ support the specified register width Width, then EFI_INVALID_PARAMETER is returned.\r
+\r
+ @param[in] This The EFI_SMM_CPU_PROTOCOL instance.\r
+ @param[in] Width The number of bytes to read from the CPU save state.\r
+ @param[in] Register Specifies the CPU register to read form the save state.\r
+ @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
+ @param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r
+ \r
+ @retval EFI_SUCCESS The register was read from Save State.\r
+ @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
+ @retval EFI_INVALID_PARAMETER Input parameters are not valid, for example, Processor No or register width \r
+ is not correct.This or Buffer is NULL.\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SMM_READ_SAVE_STATE)(\r
+ IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
+ IN UINTN Width,\r
+ IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
+ IN UINTN CpuIndex,\r
+ OUT VOID *Buffer\r
+ );\r
+\r
+\r
+/**\r
+ Write data to the CPU save state.\r
+\r
+ This function is used to write the specified number of bytes of the specified register to the CPU save \r
+ state of the specified CPU and place the value into the buffer. If the CPU does not support the \r
+ specified register Register, then EFI_UNSUPPORTED should be returned. If the CPU does not \r
+ support the specified register width Width, then EFI_INVALID_PARAMETER is returned.\r
+\r
+ @param[in] This The EFI_SMM_CPU_PROTOCOL instance.\r
+ @param[in] Width The number of bytes to write to the CPU save state.\r
+ @param[in] Register Specifies the CPU register to write to the save state.\r
+ @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
+ @param[in] Buffer Upon entry, this holds the new CPU register value.\r
+ \r
+ @retval EFI_SUCCESS The register was written to Save State.\r
+ @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
+ @retval EFI_INVALID_PARAMETER Input parameters are not valid. For example: \r
+ ProcessorIndex or Width is not correct.\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SMM_WRITE_SAVE_STATE)(\r
+ IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
+ IN UINTN Width, \r
+ IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
+ IN UINTN CpuIndex,\r
+ IN CONST VOID *Buffer\r
+ );\r
+\r
+///\r
+/// EFI SMM CPU Protocol provides access to CPU-related information while in SMM.\r
+///\r
+/// This protocol allows SMM drivers to access architecture-standard registers from any of the CPU \r
+/// save state areas. In some cases, difference processors provide the same information in the save state, \r
+/// but not in the same format. These so-called pseudo-registers provide this information in a standard \r
+/// format. \r
+///\r
+struct _EFI_SMM_CPU_PROTOCOL {\r
+ EFI_SMM_READ_SAVE_STATE ReadSaveState;\r
+ EFI_SMM_WRITE_SAVE_STATE WriteSaveState;\r
+};\r
+\r
+extern EFI_GUID gEfiSmmCpuProtocolGuid;\r
+\r
+#endif\r
+\r
gEfiDiskInfoProtocolGuid = { 0xD432A67F, 0x14DC, 0x484B, { 0xB3, 0xBB, 0x3F, 0x02, 0x91, 0x84, 0x93, 0x27 }}\r
\r
## Include/Protocol/Smbios.h\r
- gEfiSmbiosProtocolGuid = {0x3583ff6, 0xcb36, 0x4940, {0x94, 0x7e, 0xb9, 0xb3, 0x9f, 0x4a, 0xfa, 0xf7}}\r
+ gEfiSmbiosProtocolGuid = {0x3583ff6, 0xcb36, 0x4940, { 0x94, 0x7e, 0xb9, 0xb3, 0x9f, 0x4a, 0xfa, 0xf7}}\r
\r
## Include/Protocol/S3SaveState.h\r
- gEfiS3SaveStateProtocolGuid = {0xe857caf6, 0xc046, 0x45dc, {0xbe, 0x3f, 0xee, 0x7, 0x65, 0xfb, 0xa8, 0x87}}\r
+ gEfiS3SaveStateProtocolGuid = {0xe857caf6, 0xc046, 0x45dc, { 0xbe, 0x3f, 0xee, 0x7, 0x65, 0xfb, 0xa8, 0x87}}\r
\r
## Include/Protocol/S3SmmSaveState.h\r
gEfiS3SmmSaveStateProtocolGuid = {0x320afe62, 0xe593, 0x49cb, { 0xa9, 0xf1, 0xd4, 0xc2, 0xf4, 0xaf, 0x1, 0x4c}}\r
gEfiSmmCpuIoProtocolGuid = { 0x3242a9d8, 0xce70, 0x4aa0, { 0x95, 0x5d, 0x5e, 0x7b, 0x14, 0x0d, 0xe4, 0xd2 }}\r
\r
## Include/Protocol/SmmBase2.h\r
- gEfiSmmBase2ProtocolGuid = { 0xf4ccbfb7, 0xf6e0, 0x47fd, {0x9d, 0xd4, 0x10, 0xa8, 0xf1, 0x50, 0xc1, 0x91 }}\r
+ gEfiSmmBase2ProtocolGuid = { 0xf4ccbfb7, 0xf6e0, 0x47fd, { 0x9d, 0xd4, 0x10, 0xa8, 0xf1, 0x50, 0xc1, 0x91 }}\r
\r
## Include/Protocol/SmmAccess2.h\r
- gEfiSmmAccess2ProtocolGuid = { 0xc2702b74, 0x800c, 0x4131, {0x87, 0x46, 0x8f, 0xb5, 0xb8, 0x9c, 0xe4, 0xac }}\r
+ gEfiSmmAccess2ProtocolGuid = { 0xc2702b74, 0x800c, 0x4131, { 0x87, 0x46, 0x8f, 0xb5, 0xb8, 0x9c, 0xe4, 0xac }}\r
\r
## Include/Protocol/SmmControl2.h\r
- gEfiSmmControl2ProtocolGuid = { 0x843dc720, 0xab1e, 0x42cb, {0x93, 0x57, 0x8a, 0x0, 0x78, 0xf3, 0x56, 0x1b}}\r
+ gEfiSmmControl2ProtocolGuid = { 0x843dc720, 0xab1e, 0x42cb, { 0x93, 0x57, 0x8a, 0x0, 0x78, 0xf3, 0x56, 0x1b}}\r
\r
## Include/Protocol/SmmConfiguration.h\r
- gEfiSmmConfigurationProtocolGuid= { 0x26eeb3de, 0xb689, 0x492e, {0x80, 0xf0, 0xbe, 0x8b, 0xd7, 0xda, 0x4b, 0xa7 }}\r
+ gEfiSmmConfigurationProtocolGuid= { 0x26eeb3de, 0xb689, 0x492e, { 0x80, 0xf0, 0xbe, 0x8b, 0xd7, 0xda, 0x4b, 0xa7 }}\r
\r
## Include/Protocol/SmmReadyToLock.h\r
gEfiSmmReadyToLockProtocolGuid = { 0x47b7fa8c, 0xf4bd, 0x4af6, { 0x82, 0x00, 0x33, 0x30, 0x86, 0xf0, 0xd2, 0xc8 }}\r
gEfiSmmCommunicationProtocolGuid = { 0xc68ed8e2, 0x9dc6, 0x4cbd, { 0x9d, 0x94, 0xdb, 0x65, 0xac, 0xc5, 0xc3, 0x32 }}\r
\r
## Include/Protocol/SmmStatusCode.h\r
- gEfiSmmStatusCodeProtocolGuid = { 0x6afd2b77, 0x98c1, 0x4acd, {0xa6, 0xf9, 0x8a, 0x94, 0x39, 0xde, 0xf, 0xb1}}\r
+ gEfiSmmStatusCodeProtocolGuid = { 0x6afd2b77, 0x98c1, 0x4acd, { 0xa6, 0xf9, 0x8a, 0x94, 0x39, 0xde, 0xf, 0xb1}}\r
+\r
+ ## Include/Protocol/SmmCpu.h\r
+ gEfiSmmCpuProtocolGuid = { 0xeb346b97, 0x975f, 0x4a9f, { 0x8b, 0x22, 0xf8, 0xe9, 0x2b, 0xb3, 0xd5, 0x69 }}\r
\r
#\r
# Protocols defined in UEFI2.1/UEFI2.0/EFI1.1\r
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