NASM introduced FXSAVE / FXRSTOR support in commit
900fa5b26b8f ("NASM
0.98p3-hpa", 2002-04-30), which commit stands for the nasm-0.98p3-hpa
release.
NASM introduced FXSAVE64 / FXRSTOR64 support in commit
3a014348ca15
("insns: add FXSAVE64/FXRSTOR64, drop np prefix", 2010-07-07), which was
part of the "nasm-2.09" release.
Edk2 requires nasm-2.10 or later for use with the GCC toolchain family,
and nasm-2.12.01 or later for use with all other toolchain families.
Replace the binary encoding of the FXSAVE(64)/FXRSTOR(64) instructions
with mnemonics.
I verified that the "Ia32/SmiException.obj", "X64/SmiEntry.obj" and
"X64/SmiException.obj" files are rebuilt after this patch, without any
change in content.
This patch removes the last instructions encoded with DBs from
PiSmmCpuDxeSmm.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
;; FX_SAVE_STATE_IA32 FxSaveState;\r
sub esp, 512\r
mov edi, esp\r
- db 0xf, 0xae, 0x7 ;fxsave [edi]\r
+ fxsave [edi]\r
\r
; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear\r
cld\r
\r
;; FX_SAVE_STATE_IA32 FxSaveState;\r
mov esi, esp\r
- db 0xf, 0xae, 0xe ; fxrstor [esi]\r
+ fxrstor [esi]\r
add esp, 512\r
\r
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
clts\r
sub esp, 512\r
mov edi, esp\r
- db 0xf, 0xae, 0x7 ;fxsave [edi]\r
+ fxsave [edi]\r
\r
; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear\r
cld\r
\r
;; FX_SAVE_STATE_IA32 FxSaveState;\r
mov esi, esp\r
- db 0xf, 0xae, 0xe ; fxrstor [esi]\r
+ fxrstor [esi]\r
add esp, 512\r
\r
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
; Save FP registers\r
;\r
sub rsp, 0x200\r
- DB 0x48 ; FXSAVE64\r
- fxsave [rsp]\r
+ fxsave64 [rsp]\r
\r
add rsp, -0x20\r
\r
;\r
; Restore FP registers\r
;\r
- DB 0x48 ; FXRSTOR64\r
- fxrstor [rsp]\r
+ fxrstor64 [rsp]\r
\r
add rsp, 0x200\r
\r
\r
sub rsp, 512\r
mov rdi, rsp\r
- db 0xf, 0xae, 00000111y ;fxsave [rdi]\r
+ fxsave [rdi]\r
\r
; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear\r
cld\r
;; FX_SAVE_STATE_X64 FxSaveState;\r
\r
mov rsi, rsp\r
- db 0xf, 0xae, 00001110y ; fxrstor [rsi]\r
+ fxrstor [rsi]\r
add rsp, 512\r
\r
;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r