UefiCpuPkg/CpuCommonFeaturesLib: Register MSR base on scope Info.

Because MSR has scope attribute, driver has no needs to set
MSR for all APs if MSR scope is core or package type. This patch
updates code to base on the MSR scope value to add MSR to the register
table.

Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
index 47116355a8ff392d0277a18f49d3f3cf8a5f3382..1beaebe69c8baea5507ca5dc0d5f8b300a3d38e9 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
@@ -67,6 +67,14 @@ C1eInitialize (
   IN BOOLEAN                           State\r
   )\r
 {\r
+  //\r
+  // The scope of C1EEnable bit in the MSR_NEHALEM_POWER_CTL is Package, only program\r
+  // MSR_FEATURE_CONFIG for thread 0 core 0 in each package.\r
+  //\r
+  if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {\r
+  return RETURN_SUCCESS;\r
+  }\r
+\r
   CPU_REGISTER_TABLE_WRITE_FIELD (\r
     ProcessorNumber,\r
     Msr,\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
index 2038171a14c3e207bf91612c9740225bbcc0e8d9..f30117d2c510a004759b02dd32281031c9b2bc7e 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
@@ -69,6 +69,18 @@ EistInitialize (
   IN BOOLEAN                           State\r
   )\r
 {\r
+  //\r
+  // The scope of the MSR_IA32_MISC_ENABLE is core for below processor type, only program\r
+  // MSR_IA32_MISC_ENABLE for thread 0 in each core.\r
+  //\r
+  if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+    if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+      return RETURN_SUCCESS;\r
+    }\r
+  }\r
+\r
   CPU_REGISTER_TABLE_WRITE_FIELD (\r
     ProcessorNumber,\r
     Msr,\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
index 921656a1e86989e27117e3db01c7a49c18138cd2..ff06cb9b6099d3174060e3e2811a6a7331d5fa97 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
@@ -79,6 +79,16 @@ ExecuteDisableInitialize (
   IN BOOLEAN                           State\r
   )\r
 {\r
+  //\r
+  // The scope of the MSR_IA32_EFER is core for below processor type, only program\r
+  // MSR_IA32_EFER for thread 0 in each core.\r
+  //\r
+  if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+    if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+      return RETURN_SUCCESS;\r
+    }\r
+  }\r
+\r
   CPU_REGISTER_TABLE_WRITE_FIELD (\r
     ProcessorNumber,\r
     Msr,\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
index 029bcf87b3ce7dfa5f6aafc67f1f1c5f9cf7fa15..2682093c2393335ae18092d5e3713d165ad43290 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
@@ -40,6 +40,18 @@ FastStringsInitialize (
   IN BOOLEAN                           State\r
   )\r
 {\r
+  //\r
+  // The scope of FastStrings bit in the MSR_IA32_MISC_ENABLE is core for below processor type, only program\r
+  // MSR_IA32_MISC_ENABLE for thread 0 in each core.\r
+  //\r
+  if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+    if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+      return RETURN_SUCCESS;\r
+    }\r
+  }\r
+\r
   CPU_REGISTER_TABLE_WRITE_FIELD (\r
     ProcessorNumber,\r
     Msr,\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
index d28c4ec51a04164480ffbae86a01f457151eee84..8c1eb5eb4f80a1996b177a8b2ee4d559a8598d23 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
@@ -96,6 +96,19 @@ VmxInitialize (
 {\r
   MSR_IA32_FEATURE_CONTROL_REGISTER    *MsrRegister;\r
 \r
+  //\r
+  // The scope of EnableVmxOutsideSmx bit in the MSR_IA32_FEATURE_CONTROL is core for\r
+  // below processor type, only program MSR_IA32_FEATURE_CONTROL for thread 0 in each\r
+  // core.\r
+  //\r
+  if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+    if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+      return RETURN_SUCCESS;\r
+    }\r
+  }\r
+\r
   ASSERT (ConfigData != NULL);\r
   MsrRegister = (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData;\r
   if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {\r
@@ -171,6 +184,19 @@ LockFeatureControlRegisterInitialize (
 {\r
   MSR_IA32_FEATURE_CONTROL_REGISTER    *MsrRegister;\r
 \r
+  //\r
+  // The scope of Lock bit in the MSR_IA32_FEATURE_CONTROL is core for\r
+  // below processor type, only program MSR_IA32_FEATURE_CONTROL for thread 0 in each\r
+  // core.\r
+  //\r
+  if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+    if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+      return RETURN_SUCCESS;\r
+    }\r
+  }\r
+\r
   ASSERT (ConfigData != NULL);\r
   MsrRegister = (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData;\r
   if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {\r
@@ -248,6 +274,18 @@ SmxInitialize (
   MSR_IA32_FEATURE_CONTROL_REGISTER    *MsrRegister;\r
   RETURN_STATUS                        Status;\r
 \r
+  //\r
+  // The scope of Lock bit in the MSR_IA32_FEATURE_CONTROL is core for\r
+  // below processor type, only program MSR_IA32_FEATURE_CONTROL for thread 0 in each\r
+  // core.\r
+  //\r
+  if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+    if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+      return RETURN_SUCCESS;\r
+    }\r
+  }\r
+\r
   Status = RETURN_SUCCESS;\r
 \r
   if (State && (!IsCpuFeatureInSetting (CPU_FEATURE_VMX))) {\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
index 3d41efe9e993804a2e05d2fe6fe7f9635999718e..eab1fb538c3dafa0946855e9ba19c3d285a35af6 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
@@ -70,6 +70,20 @@ LimitCpuidMaxvalInitialize (
   IN BOOLEAN                           State\r
   )\r
 {\r
+  //\r
+  // The scope of LimitCpuidMaxval bit in the MSR_IA32_MISC_ENABLE is core for below\r
+  // processor type, only program MSR_IA32_MISC_ENABLE for thread 0 in each core.\r
+  //\r
+  if (IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r\r
+      IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+    if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+      return RETURN_SUCCESS;\r
+    }\r
+  }\r
+\r
   CPU_REGISTER_TABLE_WRITE_FIELD (\r
     ProcessorNumber,\r
     Msr,\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
index c4eca062fdcdecda72235e9035ff4805c6161c2e..f8bee53819f476bb2bcc41db2d4bcf26693674f8 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
@@ -140,6 +140,32 @@ McaInitialize (
   MSR_IA32_MCG_CAP_REGISTER  McgCap;\r
   UINT32                     BankIndex;\r
 \r
+  //\r
+  // The scope of MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS is core for below processor type, only program\r
+  // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS for thread 0 in each core.\r
+  //\r
+  if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_SANDY_BRIDGE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_SKYLAKE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_XEON_PHI_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+    if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+      return RETURN_SUCCESS;\r
+    }\r
+  }\r
+\r
+  //\r
+  // The scope of MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS is package for below processor type, only program\r
+  // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS for thread 0 core 0 in each package.\r
+  //\r
+  if (IS_NEHALEM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+    if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {\r
+      return RETURN_SUCCESS;\r
+    }\r
+  }\r
+\r
   if (State) {\r
     McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r
     for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) {\r
@@ -301,6 +327,18 @@ LmceInitialize (
 {\r
   MSR_IA32_FEATURE_CONTROL_REGISTER    *MsrRegister;\r
 \r
+  //\r
+  // The scope of FastStrings bit in the MSR_IA32_MISC_ENABLE is core for below processor type, only program \r
+  // MSR_IA32_MISC_ENABLE for thread 0 in each core.\r
+  //\r
+  if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+    if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+      return RETURN_SUCCESS;\r
+    }\r
+  }\r
+\r
   ASSERT (ConfigData != NULL);\r
   MsrRegister = (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData;\r
   if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c
index 1d43bd128afe8a31b6c157e73325facda02fac88..530748bf46bb5a75df5a59096980f70a2ef4e31e 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c
@@ -67,6 +67,21 @@ MonitorMwaitInitialize (
   IN BOOLEAN                           State\r
   )\r
 {\r
+  //\r
+  // The scope of the MSR_IA32_MISC_ENABLE is core for below processor type, only program\r
+  // MSR_IA32_MISC_ENABLE for thread 0 in each core.\r
+  //\r
+  if (IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+    if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+      return RETURN_SUCCESS;\r
+    }\r
+  }\r
+\r
   CPU_REGISTER_TABLE_WRITE_FIELD (\r
     ProcessorNumber,\r
     Msr,\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c
index 8cafba4f4a87991206605c96d23b821bd5aa43d7..2e0d2bdeca9d95623c1fa9b49dc6ac5f8c83610b 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c
@@ -74,6 +74,17 @@ PendingBreakInitialize (
   IN BOOLEAN                           State\r
   )\r
 {\r
+  //\r
+  // The scope of the MSR_ATOM_IA32_MISC_ENABLE is core for below processor type, only program\r
+  // MSR_ATOM_IA32_MISC_ENABLE for thread 0 in each core.\r
+  //\r
+  // Support function has check the processer type for this feature, no need to check again\r
+  // here.\r
+  //\r
+  if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+    return RETURN_SUCCESS;\r
+  }\r
+\r
   //\r
   // ATOM, CORE2, CORE, PENTIUM_4 and IS_PENTIUM_M_PROCESSOR have the same MSR index,\r
   // Simply use MSR_ATOM_IA32_MISC_ENABLE here\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
index 721470cdfe9c844e5f31b198ad8a3a33cfbb3879..d6219f4f3f23e6103ba528cb9e2a576d09f27924 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
@@ -101,6 +101,17 @@ PpinInitialize (
     return MsrPpinCtrl.Bits.Enable_PPIN == State ? RETURN_SUCCESS : RETURN_DEVICE_ERROR;\r
   }\r
 \r
+  //\r
+  // Support function already check the processor which support PPIN feature, so this function not need\r
+  // to check the processor again.\r
+  //\r
+  // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only program MSR_IVY_BRIDGE_PPIN_CTL for\r
+  // thread 0 core 0 in each package.\r
+  //\r
+  if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {\r
+    return RETURN_SUCCESS;\r
+  }\r
+\r
   CPU_REGISTER_TABLE_WRITE_FIELD (\r
     ProcessorNumber,\r
     Msr,\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
index 98490c67776c45ed6df9f34ac1d5114282a17241..cf34ad4d1fdb25a5979e10be70fe7ab8858d2f2f 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
@@ -191,6 +191,17 @@ ProcTraceInitialize (
   MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER  OutputMaskPtrsReg;\r
   RTIT_TOPA_TABLE_ENTRY                *TopaEntryPtr;\r
 \r
+  //\r
+  // The scope of the MSR_IA32_RTIT_* is core for below processor type, only program\r
+  // MSR_IA32_RTIT_* for thread 0 in each core.\r
+  //\r
+  if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+    if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+      return RETURN_SUCCESS;\r
+    }\r
+  }\r
+\r
   ProcTraceData = (PROC_TRACE_DATA *) ConfigData;\r
   ASSERT (ProcTraceData != NULL);\r
 \r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
index b4a453c3525c4c9acf6b3af5ae665fb98c725610..342b45f25b63c6ceee5ab44757e5a41230a353e8 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
@@ -102,6 +102,16 @@ X2ApicInitialize (
 {\r
   BOOLEAN                            *X2ApicEnabled;\r
 \r
+  //\r
+  // The scope of the MSR_IA32_APIC_BASE is core for below processor type, only program\r
+  // MSR_IA32_APIC_BASE for thread 0 in each core.\r
+  //\r
+  if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+    if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+      return RETURN_SUCCESS;\r
+    }\r
+  }\r
+\r
   ASSERT (ConfigData != NULL);\r
   X2ApicEnabled = (BOOLEAN *) ConfigData;\r
   if (X2ApicEnabled[ProcessorNumber]) {\r