MdePkg/Include: RISC-V definitions.

Add RISC-V processor related definitions.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

diff --git a/MdePkg/Include/IndustryStandard/PeImage.h b/MdePkg/Include/IndustryStandard/PeImage.h
index a3d9bbed757b94488824d80ef6f9e42231ce6f03..9b267002a17f79fec3da42ff09248e56c494fc9e 100644 (file)
--- a/MdePkg/Include/IndustryStandard/PeImage.h
+++ b/MdePkg/Include/IndustryStandard/PeImage.h
@@ -9,6 +9,8 @@
 \r
 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+Portions Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+\r
 SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
@@ -34,6 +36,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #define IMAGE_FILE_MACHINE_X64             0x8664\r
 #define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED  0x01c2\r
 #define IMAGE_FILE_MACHINE_ARM64           0xAA64\r
+#define IMAGE_FILE_MACHINE_RISCV32         0x5032\r
+#define IMAGE_FILE_MACHINE_RISCV64         0x5064\r
+#define IMAGE_FILE_MACHINE_RISCV128        0x5128\r
 \r
 //\r
 // EXE file formats\r
@@ -493,6 +498,13 @@ typedef struct {
 #define EFI_IMAGE_REL_BASED_MIPS_JMPADDR16  9\r
 #define EFI_IMAGE_REL_BASED_DIR64           10\r
 \r
+///\r
+/// Relocation types of RISC-V processor.\r
+///\r
+#define EFI_IMAGE_REL_BASED_RISCV_HI20      5\r
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12I    7\r
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12S    8\r
+\r
 ///\r
 /// Line number format.\r
 ///\r

diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protocol/DebugSupport.h
index 800e7710e6efa9e63e08fcf154770a5f5d16dfe1..7fb1d3b3e45f52426fb6a0cf4ddfdbc48e83fdb8 100644 (file)
--- a/MdePkg/Include/Protocol/DebugSupport.h
+++ b/MdePkg/Include/Protocol/DebugSupport.h
@@ -7,6 +7,7 @@
 \r
 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
 Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
+Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
 \r
 SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
@@ -603,6 +604,59 @@ typedef struct {
   UINT64  FAR;  // Fault Address Register\r
 } EFI_SYSTEM_CONTEXT_AARCH64;\r
 \r
+///\r
+/// RISC-V processor exception types.\r
+///\r
+#define EXCEPT_RISCV_INST_MISALIGNED              0\r
+#define EXCEPT_RISCV_INST_ACCESS_FAULT            1\r
+#define EXCEPT_RISCV_ILLEGAL_INST                 2\r
+#define EXCEPT_RISCV_BREAKPOINT                   3\r
+#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED      4\r
+#define EXCEPT_RISCV_LOAD_ACCESS_FAULT            5\r
+#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6\r
+#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT       7\r
+#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE          8\r
+#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE          9\r
+#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE          10\r
+#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE          11\r
+\r
+#define EXCEPT_RISCV_SOFTWARE_INT       0x0\r
+#define EXCEPT_RISCV_TIMER_INT          0x1\r
+\r
+typedef struct {\r
+  UINT64  X0;\r
+  UINT64  X1;\r
+  UINT64  X2;\r
+  UINT64  X3;\r
+  UINT64  X4;\r
+  UINT64  X5;\r
+  UINT64  X6;\r
+  UINT64  X7;\r
+  UINT64  X8;\r
+  UINT64  X9;\r
+  UINT64  X10;\r
+  UINT64  X11;\r
+  UINT64  X12;\r
+  UINT64  X13;\r
+  UINT64  X14;\r
+  UINT64  X15;\r
+  UINT64  X16;\r
+  UINT64  X17;\r
+  UINT64  X18;\r
+  UINT64  X19;\r
+  UINT64  X20;\r
+  UINT64  X21;\r
+  UINT64  X22;\r
+  UINT64  X23;\r
+  UINT64  X24;\r
+  UINT64  X25;\r
+  UINT64  X26;\r
+  UINT64  X27;\r
+  UINT64  X28;\r
+  UINT64  X29;\r
+  UINT64  X30;\r
+  UINT64  X31;\r
+} EFI_SYSTEM_CONTEXT_RISCV64;\r
 \r
 ///\r
 /// Universal EFI_SYSTEM_CONTEXT definition.\r
@@ -614,6 +668,7 @@ typedef union {
   EFI_SYSTEM_CONTEXT_IPF  *SystemContextIpf;\r
   EFI_SYSTEM_CONTEXT_ARM  *SystemContextArm;\r
   EFI_SYSTEM_CONTEXT_AARCH64  *SystemContextAArch64;\r
+  EFI_SYSTEM_CONTEXT_RISCV64  *SystemContextRiscV64;\r
 } EFI_SYSTEM_CONTEXT;\r
 \r
 //\r

diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h b/MdePkg/Include/Protocol/PxeBaseCode.h
index b02d27013428d6c1394575a2a082c581fe47c8dc..c666d312b5805effbb8e3a3e985982eb32e74e62 100644 (file)
--- a/MdePkg/Include/Protocol/PxeBaseCode.h
+++ b/MdePkg/Include/Protocol/PxeBaseCode.h
@@ -3,6 +3,8 @@
   devices for network access and network booting.\r
 \r
 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+\r
 SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
   @par Revision Reference:\r
@@ -153,6 +155,8 @@ typedef UINT16  EFI_PXE_BASE_CODE_UDP_PORT;
 #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE    0x000A\r
 #elif defined (MDE_CPU_AARCH64)\r
 #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE    0x000B\r
+#elif defined (MDE_CPU_RISCV64)\r
+#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE    0x001B\r
 #endif\r
 \r
 \r

diff --git a/MdePkg/Include/Uefi/UefiBaseType.h b/MdePkg/Include/Uefi/UefiBaseType.h
index a62f13dd064fa88e1bb775b88407b93658ca5eb7..934fc07285d99e59588513502356363e6b4e2c35 100644 (file)
--- a/MdePkg/Include/Uefi/UefiBaseType.h
+++ b/MdePkg/Include/Uefi/UefiBaseType.h
@@ -3,6 +3,7 @@
 \r
 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
 Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
+Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
 \r
 SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
@@ -240,6 +241,12 @@ typedef union {
 ///\r
 #define EFI_IMAGE_MACHINE_AARCH64  0xAA64\r
 \r
+///\r
+/// PE32+ Machine type for RISC-V 32/64/128\r
+///\r
+#define EFI_IMAGE_MACHINE_RISCV32   0x5032\r
+#define EFI_IMAGE_MACHINE_RISCV64   0x5064\r
+#define EFI_IMAGE_MACHINE_RISCV128  0x5128\r
 \r
 #if   defined (MDE_CPU_IA32)\r
 \r
@@ -268,6 +275,12 @@ typedef union {
 \r
 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)\r
 \r
+#elif defined (MDE_CPU_RISCV64)\r
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \\r
+  ((Machine) == EFI_IMAGE_MACHINE_RISCV64)\r
+\r
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)\r
+\r
 #elif defined (MDE_CPU_EBC)\r
 \r
 ///\r

diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h
index 444aa35ecab1adf313c83f451b28f94c9d517455..8ffaf97515924c3e6a37fc4916dc67fdc7a5d83c 100644 (file)
--- a/MdePkg/Include/Uefi/UefiSpec.h
+++ b/MdePkg/Include/Uefi/UefiSpec.h
@@ -6,6 +6,8 @@
   by this include file.\r
 \r
 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
+Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+\r
 SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
@@ -2198,6 +2200,7 @@ typedef struct {
 #define EFI_REMOVABLE_MEDIA_FILE_NAME_X64     L"\\EFI\\BOOT\\BOOTX64.EFI"\r
 #define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM     L"\\EFI\\BOOT\\BOOTARM.EFI"\r
 #define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI"\r
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.EFI"\r
 \r
 #if   defined (MDE_CPU_IA32)\r
   #define EFI_REMOVABLE_MEDIA_FILE_NAME   EFI_REMOVABLE_MEDIA_FILE_NAME_IA32\r
@@ -2208,6 +2211,8 @@ typedef struct {
   #define EFI_REMOVABLE_MEDIA_FILE_NAME   EFI_REMOVABLE_MEDIA_FILE_NAME_ARM\r
 #elif defined (MDE_CPU_AARCH64)\r
   #define EFI_REMOVABLE_MEDIA_FILE_NAME   EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64\r
+#elif defined (MDE_CPU_RISCV64)\r
+  #define EFI_REMOVABLE_MEDIA_FILE_NAME   EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64\r
 #else\r
   #error Unknown Processor Type\r
 #endif\r