Fix bugs in the PCI bus driver to support SR-IOV.

1. Expand the type of Offset in the _PCI_BAR structure from UINT8 to UINT16, because a VF BAR’s offset may be >= 0x100;
2. Enable ARI Capable Hierarchy for SR-IOV devices at earlier time because FirstVFOffset and VFStride of a SR-IOV device may change after its ARI Capable Hierarchy is set;
3. Change type of PcdSrIovSupport, PcdAriSupport, PcdMrIovSupport from FeatureFlag to [FixAtBuild, PcdDynamics], which allows SR-IOV/MR-IOV/ARI feature can be turn on/off dynamically, typically via a setup option.
4. Change PCI bus scan algorithm in PciScanBus() to prevent the case where some ARI extended functions may be skipped in the scan loop.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10644 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
index 6c17767623adb0d14c545e0b08dba3a16ea6052e..8517c60f72cf13ab57f3b0625a814855ee1d8e31 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
@@ -1,7 +1,7 @@
 /** @file\r
   Header files and data structures needed by PCI Bus module.\r
 \r
-Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -104,7 +104,7 @@ struct _PCI_BAR {
   PCI_BAR_TYPE  BarType;\r
   BOOLEAN       Prefetchable;\r
   UINT8         MemType;\r
-  UINT8         Offset;\r
+  UINT16        Offset;\r
 };\r
 \r
 //\r

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
index 214611181dc845bec2d4bbc5c44679ae618a5b35..7096b116181777b5e4dde4082ad03f002d9a78ea 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
@@ -100,13 +100,13 @@
 \r
 [FeaturePcd]\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport\r
-  gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport\r
-  gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport\r
-  gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdPciBridgeIoAlignmentProbe\r
 \r
 [Pcd]\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport\r
 \r
 # [Event]\r
 #   ##\r

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
index 0d1518a43d01c99bf1a68cfecf73ce6ceaffdde7..1ad863c96673642cb2f6d267dc08573785dd97d8 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
@@ -1,7 +1,7 @@
 /** @file\r
   Supporting functions implementaion for PCI devices management.\r
 \r
-Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -215,10 +215,6 @@ RegisterPciDevice (
   EFI_PCI_IO_PROTOCOL *PciIo;\r
   UINT8               Data8;\r
   BOOLEAN             HasEfiImage;\r
-  PCI_IO_DEVICE       *ParrentPciIoDevice;\r
-  EFI_PCI_IO_PROTOCOL *ParrentPciIo;\r
-  UINT16              Data16;\r
-  UINT32              Data32;\r
 \r
   //\r
   // Install the pciio protocol, device path protocol\r
@@ -255,35 +251,7 @@ RegisterPciDevice (
   PciIo = &(PciIoDevice->PciIo);\r
   Data8 = PCI_INT_LINE_UNKNOWN;\r
   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);\r
-  \r
-  //\r
-  // PCI-IOV programming\r
-  //\r
-  if (((FeaturePcdGet(PcdAriSupport) & EFI_PCI_IOV_POLICY_ARI) != 0) && (PciIoDevice->AriCapabilityOffset != 0) && ((FeaturePcdGet(PcdSrIovSupport) & EFI_PCI_IOV_POLICY_SRIOV) != 0) &&\r
-      (PciIoDevice->SrIovCapabilityOffset != 0)) {\r
-    //\r
-    // Check its parrent ARI forwarding capability\r
-    //\r
-    ParrentPciIoDevice = PciIoDevice->Parent;\r
-    ParrentPciIo = &(ParrentPciIoDevice->PciIo);\r
-    ParrentPciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ParrentPciIoDevice->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET, 1, &Data32);\r
-    if ((Data32 & EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) != 0) {\r
-      //\r
-      // ARI forward support in bridge, so enable it.\r
-      //\r
-      ParrentPciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ParrentPciIoDevice->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET, 1, &Data32);\r
-      Data32 |= EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING;\r
-      ParrentPciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, ParrentPciIoDevice->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET, 1, &Data32);\r
-\r
-      //\r
-      // Set ARI Capable Hierarchy for device\r
-      //\r
-      PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL, 1, &Data16);\r
-      Data16 |= EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY;\r
-      PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL, 1, &Data16);\r
-    }\r
-  }\r
-  \r
+ \r
   //\r
   // Process OpRom\r
   //\r

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
index e67777fab112b58b4d96e0dadc2d6d70a30511b0..f2108284d3aa7631b205b53bfef093033d8dd48b 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
@@ -328,11 +328,9 @@ GatherDeviceInfo (
   UINTN                           Offset;\r
   UINTN                           BarIndex;\r
   PCI_IO_DEVICE                   *PciIoDevice;\r
-  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
 \r
-  PciRootBridgeIo = Bridge->PciRootBridgeIo;\r
   PciIoDevice = CreatePciIoDevice (\r
-                  PciRootBridgeIo,\r
+                  Bridge,\r
                   Pci,\r
                   Bus,\r
                   Device,\r
@@ -370,7 +368,7 @@ GatherDeviceInfo (
   //\r
   // Parse the SR-IOV VF bars\r
   //\r
-  if ((PciIoDevice->SrIovCapabilityOffset != 0) && ((FeaturePcdGet(PcdSrIovSupport)& EFI_PCI_IOV_POLICY_SRIOV) != 0)) {\r
+  if (PcdGetBool (PcdSrIovSupport) && PciIoDevice->SrIovCapabilityOffset != 0) {\r
     for (Offset = PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0, BarIndex = 0;\r
          Offset <= PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5;\r
          BarIndex++) {\r
@@ -403,16 +401,14 @@ GatherPpbInfo (
   IN UINT8                            Func\r
   )\r
 {\r
-  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
   PCI_IO_DEVICE                   *PciIoDevice;\r
   EFI_STATUS                      Status;\r
   UINT8                           Value;\r
   EFI_PCI_IO_PROTOCOL             *PciIo;\r
   UINT8                           Temp;\r
 \r
-  PciRootBridgeIo = Bridge->PciRootBridgeIo;\r
   PciIoDevice = CreatePciIoDevice (\r
-                  PciRootBridgeIo,\r
+                  Bridge,\r
                   Pci,\r
                   Bus,\r
                   Device,\r
@@ -558,12 +554,10 @@ GatherP2CInfo (
   IN UINT8                            Func\r
   )\r
 {\r
-  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
   PCI_IO_DEVICE                   *PciIoDevice;\r
 \r
-  PciRootBridgeIo = Bridge->PciRootBridgeIo;\r
   PciIoDevice = CreatePciIoDevice (\r
-                  PciRootBridgeIo,\r
+                  Bridge,\r
                   Pci,\r
                   Bus,\r
                   Device,\r
@@ -1415,11 +1409,11 @@ PciIovParseVfBar (
     //\r
     // Scan all the BARs anyway\r
     //\r
-    PciIoDevice->VfPciBar[BarIndex].Offset = (UINT8) Offset;\r
+    PciIoDevice->VfPciBar[BarIndex].Offset = (UINT16) Offset;\r
     return Offset + 4;\r
   }\r
 \r
-  PciIoDevice->VfPciBar[BarIndex].Offset = (UINT8) Offset;\r
+  PciIoDevice->VfPciBar[BarIndex].Offset = (UINT16) Offset;\r
   if ((Value & 0x01) != 0) {\r
     //\r
     // Device I/Os. Impossible\r
@@ -1905,14 +1899,14 @@ InitializeP2C (
 **/\r
 PCI_IO_DEVICE *\r
 CreatePciIoDevice (\r
-  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *PciRootBridgeIo,\r
+  IN PCI_IO_DEVICE                    *Bridge,\r
   IN PCI_TYPE00                       *Pci,\r
   IN UINT8                            Bus,\r
   IN UINT8                            Device,\r
   IN UINT8                            Func\r
   )\r
 {\r
-  PCI_IO_DEVICE *PciIoDevice;\r
+  PCI_IO_DEVICE        *PciIoDevice;\r
   EFI_PCI_IO_PROTOCOL  *PciIo;\r
   EFI_STATUS           Status;\r
 \r
@@ -1923,7 +1917,7 @@ CreatePciIoDevice (
 \r
   PciIoDevice->Signature        = PCI_IO_DEVICE_SIGNATURE;\r
   PciIoDevice->Handle           = NULL;\r
-  PciIoDevice->PciRootBridgeIo  = PciRootBridgeIo;\r
+  PciIoDevice->PciRootBridgeIo  = Bridge->PciRootBridgeIo;\r
   PciIoDevice->DevicePath       = NULL;\r
   PciIoDevice->BusNumber        = Bus;\r
   PciIoDevice->DeviceNumber     = Device;\r
@@ -1968,146 +1962,261 @@ CreatePciIoDevice (
     PciIoDevice->IsPciExp = TRUE;\r
   }\r
 \r
-  //\r
-  // Initialize for PCI IOV\r
-  //\r
-\r
-  //\r
-  // Check ARI for function 0 only\r
-  //\r
-  Status = LocatePciExpressCapabilityRegBlock (\r
-             PciIoDevice,\r
-             EFI_PCIE_CAPABILITY_ID_ARI,\r
-             &PciIoDevice->AriCapabilityOffset,\r
-             NULL\r
-             );\r
-  if (!EFI_ERROR (Status)) {\r
-    DEBUG ((\r
-      EFI_D_INFO,\r
-      "PCI-IOV B%x.D%x.F%x - ARI Cap offset - 0x%x\n",\r
-      (UINTN)Bus,\r
-      (UINTN)Device,\r
-      (UINTN)Func,\r
-      (UINTN)PciIoDevice->AriCapabilityOffset\r
-      ));\r
-  }\r
+  if (PcdGetBool (PcdAriSupport)) {\r
+    //\r
+    // Check if the device is an ARI device.\r
+    //\r
+    Status = LocatePciExpressCapabilityRegBlock (\r
+               PciIoDevice,\r
+               EFI_PCIE_CAPABILITY_ID_ARI,\r
+               &PciIoDevice->AriCapabilityOffset,\r
+               NULL\r
+               );\r
+    if (!EFI_ERROR (Status)) {\r
+      //\r
+      // We need to enable ARI feature before calculate BusReservation,\r
+      // because FirstVFOffset and VFStride may change after that.\r
+      //\r
+      EFI_PCI_IO_PROTOCOL  *ParentPciIo;\r
+      UINT32               Data32;\r
 \r
-  Status = LocatePciExpressCapabilityRegBlock (\r
-             PciIoDevice,\r
-             EFI_PCIE_CAPABILITY_ID_SRIOV,\r
-             &PciIoDevice->SrIovCapabilityOffset,\r
-             NULL\r
-             );\r
-  if (!EFI_ERROR (Status)) {\r
-    DEBUG ((\r
-      EFI_D_INFO,\r
-      "PCI-IOV B%x.D%x.F%x - SRIOV Cap offset - 0x%x\n",\r
-      (UINTN)Bus,\r
-      (UINTN)Device,\r
-      (UINTN)Func,\r
-      (UINTN)PciIoDevice->SrIovCapabilityOffset\r
-      ));\r
-  }\r
+      //\r
+      // Check if its parent supports ARI forwarding.\r
+      //\r
+      ParentPciIo = &Bridge->PciIo;\r
+      ParentPciIo->Pci.Read (\r
+                          ParentPciIo, \r
+                          EfiPciIoWidthUint32,\r
+                          Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET,\r
+                          1,\r
+                          &Data32\r
+                          );\r
+      if ((Data32 & EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) != 0) {\r
+        //\r
+        // ARI forward support in bridge, so enable it.\r
+        //\r
+        ParentPciIo->Pci.Read (\r
+                            ParentPciIo,\r
+                            EfiPciIoWidthUint32,\r
+                            Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET,\r
+                            1,\r
+                            &Data32\r
+                            );\r
+        if ((Data32 & EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING) == 0) {\r
+          Data32 |= EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING;\r
+          ParentPciIo->Pci.Write (\r
+                              ParentPciIo,\r
+                              EfiPciIoWidthUint32,\r
+                              Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET,\r
+                              1,\r
+                              &Data32\r
+                              );\r
+          DEBUG ((\r
+            EFI_D_INFO,\r
+            "PCI B%x.D%x.F%x - ARI forwarding enabled\n",\r
+            (UINTN)Bridge->BusNumber,\r
+            (UINTN)Bridge->DeviceNumber,\r
+            (UINTN)Bridge->FunctionNumber\r
+            ));\r
+        }\r
+      }\r
 \r
-  Status = LocatePciExpressCapabilityRegBlock (\r
-             PciIoDevice,\r
-             EFI_PCIE_CAPABILITY_ID_MRIOV,\r
-             &PciIoDevice->MrIovCapabilityOffset,\r
-             NULL\r
-             );\r
-  if (!EFI_ERROR (Status)) {\r
-    DEBUG ((\r
-      EFI_D_INFO,\r
-      "PCI-IOV B%x.D%x.F%x - MRIOV Cap offset - 0x%x\n",\r
-      (UINTN)Bus,\r
-      (UINTN)Device,\r
-      (UINTN)Func,\r
-      (UINTN)PciIoDevice->MrIovCapabilityOffset\r
-      ));\r
+      DEBUG ((\r
+        EFI_D_INFO,\r
+        "PCI ARI B%x.D%x.F%x - ARI Cap offset - 0x%x\n",\r
+        (UINTN)Bus,\r
+        (UINTN)Device,\r
+        (UINTN)Func,\r
+        (UINTN)PciIoDevice->AriCapabilityOffset\r
+        ));\r
+    }\r
   }\r
 \r
   //\r
-  // Calculate SystemPageSize\r
+  // Initialization for SR-IOV\r
   //\r
-  if ((PciIoDevice->SrIovCapabilityOffset != 0) && ((FeaturePcdGet(PcdSrIovSupport)& EFI_PCI_IOV_POLICY_SRIOV) != 0)) {\r
 \r
-    PciIo->Pci.Read (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE,\r
-                 1,\r
-                 &PciIoDevice->SystemPageSize\r
-                 );\r
-    DEBUG ((EFI_D_INFO, "PCI-IOV B%x.D%x.F%x - SupportedPageSize - 0x%x\n", (UINTN)Bus, (UINTN)Device, (UINTN)Func, PciIoDevice->SystemPageSize));\r
+  if (PcdGetBool (PcdSrIovSupport)) {\r
+    Status = LocatePciExpressCapabilityRegBlock (\r
+               PciIoDevice,\r
+               EFI_PCIE_CAPABILITY_ID_SRIOV,\r
+               &PciIoDevice->SrIovCapabilityOffset,\r
+               NULL\r
+               );\r
+    if (!EFI_ERROR (Status)) {\r
+      UINT16    VFStride;\r
+      UINT16    FirstVFOffset;\r
+      UINT16    Data16;\r
+      UINT32    PFRid;\r
+      UINT32    LastVF;\r
 \r
-    PciIoDevice->SystemPageSize = (PcdGet32 (PcdSrIovSystemPageSize) & PciIoDevice->SystemPageSize);\r
-    ASSERT (PciIoDevice->SystemPageSize != 0);\r
+      //\r
+      // If the SR-IOV device is an ARI device, then Set ARI Capable Hierarchy for the device.\r
+      //\r
+      if (PcdGetBool (PcdAriSupport) && PciIoDevice->AriCapabilityOffset != 0) {\r
+        PciIo->Pci.Read (\r
+                     PciIo,\r
+                     EfiPciIoWidthUint16,\r
+                     PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL,\r
+                     1,\r
+                     &Data16\r
+                     );\r
+        Data16 |= EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY;\r
+        PciIo->Pci.Write (\r
+                     PciIo,\r
+                     EfiPciIoWidthUint16,\r
+                     PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL,\r
+                     1,\r
+                     &Data16\r
+                     );\r
+      }\r
 \r
-    PciIo->Pci.Write (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint32,\r
-                 PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE,\r
-                 1,\r
-                 &PciIoDevice->SystemPageSize\r
-                 );\r
-    DEBUG ((EFI_D_INFO, "PCI-IOV B%x.D%x.F%x - SystemPageSize - 0x%x\n", (UINTN)Bus, (UINTN)Device, (UINTN)Func, PciIoDevice->SystemPageSize));\r
-    //\r
-    // Adjust SystemPageSize for Alignment usage later\r
-    //\r
-    PciIoDevice->SystemPageSize <<= 12;\r
-  }\r
+      //\r
+      // Calculate SystemPageSize\r
+      //\r
 \r
-  // Calculate BusReservation for PCI IOV\r
-  //\r
-  if ((PciIoDevice->SrIovCapabilityOffset != 0) && ((FeaturePcdGet(PcdSrIovSupport)& EFI_PCI_IOV_POLICY_SRIOV) != 0)) {\r
-    UINT16    VFStride;\r
-    UINT16    FirstVFOffset;\r
-    UINT32    PFRid;\r
-    UINT32    LastVF;\r
+      PciIo->Pci.Read (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint32,\r
+                   PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE,\r
+                   1,\r
+                   &PciIoDevice->SystemPageSize\r
+                   );\r
+      DEBUG ((\r
+        EFI_D_INFO,\r
+        "PCI SR-IOV B%x.D%x.F%x - SupportedPageSize - 0x%x\n",\r
+        (UINTN)Bus,\r
+        (UINTN)Device,\r
+        (UINTN)Func,\r
+        PciIoDevice->SystemPageSize\r
+        ));\r
+\r
+      PciIoDevice->SystemPageSize = (PcdGet32 (PcdSrIovSystemPageSize) & PciIoDevice->SystemPageSize);\r
+      ASSERT (PciIoDevice->SystemPageSize != 0);\r
+\r
+      PciIo->Pci.Write (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint32,\r
+                   PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE,\r
+                   1,\r
+                   &PciIoDevice->SystemPageSize\r
+                   );\r
+      DEBUG ((\r
+        EFI_D_INFO,\r
+        "PCI SR-IOV B%x.D%x.F%x - SystemPageSize - 0x%x\n",\r
+        (UINTN)Bus,\r
+        (UINTN)Device,\r
+        (UINTN)Func,\r
+        PciIoDevice->SystemPageSize\r
+        ));\r
+      //\r
+      // Adjust SystemPageSize for Alignment usage later\r
+      //\r
+      PciIoDevice->SystemPageSize <<= 12;\r
 \r
-    //\r
-    // Read First FirstVFOffset, InitialVFs, and VFStride\r
-    //\r
-    PciIo->Pci.Read (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint16,\r
-                 PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF,\r
-                 1,\r
-                 &FirstVFOffset\r
-                 );\r
-    DEBUG ((EFI_D_INFO, "PCI-IOV B%x.D%x.F%x - FirstVFOffset - 0x%x\n", (UINTN)Bus, (UINTN)Device, (UINTN)Func, (UINTN)FirstVFOffset));\r
-\r
-    PciIo->Pci.Read (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint16,\r
-                 PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS,\r
-                 1,\r
-                 &PciIoDevice->InitialVFs\r
-                 );\r
-    DEBUG ((EFI_D_INFO, "PCI-IOV B%x.D%x.F%x - InitialVFs - 0x%x\n", (UINTN)Bus, (UINTN)Device, (UINTN)Func, (UINTN)PciIoDevice->InitialVFs));\r
-\r
-    PciIo->Pci.Read (\r
-                 PciIo,\r
-                 EfiPciIoWidthUint16,\r
-                 PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE,\r
-                 1,\r
-                 &VFStride\r
-                 );\r
-    DEBUG ((EFI_D_INFO, "PCI-IOV B%x.D%x.F%x - VFStride - 0x%x\n", (UINTN)Bus, (UINTN)Device, (UINTN)Func, (UINTN)VFStride));\r
+      //\r
+      // Calculate BusReservation for PCI IOV\r
+      //\r
 \r
-    //\r
-    // Calculate LastVF\r
-    //\r
-    PFRid = EFI_PCI_RID(Bus, Device, Func);\r
-    LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride;\r
+      //\r
+      // Read First FirstVFOffset, InitialVFs, and VFStride\r
+      //\r
+      PciIo->Pci.Read (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint16,\r
+                   PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF,\r
+                   1,\r
+                   &FirstVFOffset\r
+                   );\r
+      DEBUG ((\r
+        EFI_D_INFO,\r
+        "PCI SR-IOV B%x.D%x.F%x - FirstVFOffset - 0x%x\n",\r
+        (UINTN)Bus,\r
+        (UINTN)Device,\r
+        (UINTN)Func,\r
+        (UINTN)FirstVFOffset\r
+        ));\r
+\r
+      PciIo->Pci.Read (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint16,\r
+                   PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS,\r
+                   1,\r
+                   &PciIoDevice->InitialVFs\r
+                   );\r
+      DEBUG ((\r
+        EFI_D_INFO,\r
+        "PCI SR-IOV B%x.D%x.F%x - InitialVFs - 0x%x\n",\r
+        (UINTN)Bus,\r
+        (UINTN)Device,\r
+        (UINTN)Func,\r
+        (UINTN)PciIoDevice->InitialVFs\r
+        ));\r
+\r
+      PciIo->Pci.Read (\r
+                   PciIo,\r
+                   EfiPciIoWidthUint16,\r
+                   PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE,\r
+                   1,\r
+                   &VFStride\r
+                   );\r
+      DEBUG ((\r
+        EFI_D_INFO,\r
+        "PCI SR-IOV B%x.D%x.F%x - VFStride - 0x%x\n",\r
+        (UINTN)Bus,\r
+        (UINTN)Device,\r
+        (UINTN)Func,\r
+        (UINTN)VFStride\r
+        ));\r
 \r
-    //\r
-    // Calculate ReservedBusNum for this PF\r
-    //\r
-    PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1);\r
-    DEBUG ((EFI_D_INFO, "PCI-IOV B%x.D%x.F%x - reserved bus number - 0x%x\n", (UINTN)Bus, (UINTN)Device, (UINTN)Func, (UINTN)PciIoDevice->ReservedBusNum));\r
+      //\r
+      // Calculate LastVF\r
+      //\r
+      PFRid = EFI_PCI_RID(Bus, Device, Func);\r
+      LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride;\r
+\r
+      //\r
+      // Calculate ReservedBusNum for this PF\r
+      //\r
+      PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1);\r
+      DEBUG ((\r
+        EFI_D_INFO,\r
+        "PCI SR-IOV B%x.D%x.F%x - reserved bus number - 0x%x\n",\r
+        (UINTN)Bus,\r
+        (UINTN)Device,\r
+        (UINTN)Func,\r
+        (UINTN)PciIoDevice->ReservedBusNum\r
+        ));\r
+\r
+      DEBUG ((\r
+        EFI_D_INFO,\r
+        "PCI SR-IOV B%x.D%x.F%x - SRIOV Cap offset - 0x%x\n",\r
+        (UINTN)Bus,\r
+        (UINTN)Device,\r
+        (UINTN)Func,\r
+        (UINTN)PciIoDevice->SrIovCapabilityOffset\r
+        ));\r
+    }\r
   }\r
 \r
+  if (PcdGetBool (PcdMrIovSupport)) {\r
+    Status = LocatePciExpressCapabilityRegBlock (\r
+               PciIoDevice,\r
+               EFI_PCIE_CAPABILITY_ID_MRIOV,\r
+               &PciIoDevice->MrIovCapabilityOffset,\r
+               NULL\r
+               );\r
+    if (!EFI_ERROR (Status)) {\r
+      DEBUG ((\r
+        EFI_D_INFO,\r
+        "PCI MR-IOV B%x.D%x.F%x - MRIOV Cap offset - 0x%x\n",\r
+        (UINTN)Bus,\r
+        (UINTN)Device,\r
+        (UINTN)Func,\r
+        (UINTN)PciIoDevice->MrIovCapabilityOffset\r
+        ));\r
+    }\r
+  }\r
 \r
   //\r
   // Initialize the reserved resource list\r

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h
index fa3a3992fdb3674cd8336f7414e522581af743f2..a4489b895fc49dd478710b4df7ddf907ce7554df 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h
@@ -1,7 +1,7 @@
 /** @file\r
   PCI emumeration support functions declaration for PCI Bus module.\r
 \r
-Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -364,7 +364,7 @@ InitializeP2C (
   Create and initiliaze general PCI I/O device instance for\r
   PCI device/bridge device/hotplug bridge device.\r
 \r
-  @param PciRootBridgeIo   Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+  @param Bridge            Parent bridge instance.\r
   @param Pci               Input Pci information block.\r
   @param Bus               Device Bus NO.\r
   @param Device            Device device NO.\r
@@ -375,7 +375,7 @@ InitializeP2C (
 **/\r
 PCI_IO_DEVICE *\r
 CreatePciIoDevice (\r
-  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *PciRootBridgeIo,\r
+  IN PCI_IO_DEVICE                    *Bridge,\r
   IN PCI_TYPE00                       *Pci,\r
   IN UINT8                            Bus,\r
   IN UINT8                            Device,\r

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
index 8397a405823b934d64fa83cfe01313614e7cc57f..4717140255c1bce3970c4e71a9ca160d601d2b88 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
@@ -1,7 +1,7 @@
 /** @file\r
   Internal library implementation for PCI Bus module.\r
 \r
-Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -738,50 +738,43 @@ PciScanBus (
                 );\r
 \r
       if (EFI_ERROR (Status)) {\r
-        if (Func == 0) {\r
-          //\r
-          // Skip sub functions, this is not a multi function device\r
-          //\r
-          Func = PCI_MAX_FUNC;\r
-        }\r
-\r
         continue;\r
       }\r
 \r
       DEBUG((EFI_D_INFO, "Found DEV(%02d,%02d,%02d)\n", StartBusNumber, Device, Func ));\r
 \r
-      if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
-        //\r
-        // Get the PCI device information\r
-        //\r
-        Status = PciSearchDevice (\r
-                  Bridge,\r
-                  &Pci,\r
-                  StartBusNumber,\r
-                  Device,\r
-                  Func,\r
-                  &PciDevice\r
-                  );\r
+      //\r
+      // Get the PCI device information\r
+      //\r
+      Status = PciSearchDevice (\r
+                Bridge,\r
+                &Pci,\r
+                StartBusNumber,\r
+                Device,\r
+                Func,\r
+                &PciDevice\r
+                );\r
 \r
-        ASSERT (!EFI_ERROR (Status));\r
+      ASSERT (!EFI_ERROR (Status));\r
 \r
-        PciAddress = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0);\r
+      PciAddress = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0);\r
 \r
-        if (!IS_PCI_BRIDGE (&Pci)) {\r
-          //\r
-          // PCI bridges will be called later\r
-          // Here just need for PCI device or PCI to cardbus controller\r
-          // EfiPciBeforeChildBusEnumeration for PCI Device Node\r
-          //\r
-          PreprocessController (\r
-              PciDevice,\r
-              PciDevice->BusNumber,\r
-              PciDevice->DeviceNumber,\r
-              PciDevice->FunctionNumber,\r
-              EfiPciBeforeChildBusEnumeration\r
-              );\r
-        }\r
+      if (!IS_PCI_BRIDGE (&Pci)) {\r
+        //\r
+        // PCI bridges will be called later\r
+        // Here just need for PCI device or PCI to cardbus controller\r
+        // EfiPciBeforeChildBusEnumeration for PCI Device Node\r
+        //\r
+        PreprocessController (\r
+            PciDevice,\r
+            PciDevice->BusNumber,\r
+            PciDevice->DeviceNumber,\r
+            PciDevice->FunctionNumber,\r
+            EfiPciBeforeChildBusEnumeration\r
+            );\r
+      }\r
 \r
+      if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
         //\r
         // For Pci Hotplug controller devcie only\r
         //\r
@@ -976,18 +969,9 @@ PciScanBus (
       } else  {\r
         //\r
         // It is device. Check PCI IOV for Bus reservation\r
-        //\r
-        if (PciDevice == NULL) {\r
-          //\r
-          // No PciDevice found, conitue Scan\r
-          //\r
-          continue;\r
-        }\r
-        //\r
         // Go through each function, just reserve the MAX ReservedBusNum for one device\r
         //\r
-        if ((PciDevice->AriCapabilityOffset != 0) && ((FeaturePcdGet(PcdSrIovSupport)& EFI_PCI_IOV_POLICY_SRIOV) != 0)) {\r
-\r
+        if (PcdGetBool (PcdSrIovSupport) && PciDevice->SrIovCapabilityOffset != 0) {\r
           if (TempReservedBusNum < PciDevice->ReservedBusNum) {\r
 \r
             (*SubBusNumber) = (UINT8)((*SubBusNumber) + PciDevice->ReservedBusNum - TempReservedBusNum);\r