IntelSiliconPkg: Fixed bug in IgdOpregion spec

Spec documents Mailbox3 - RM31 size as 0x45(69) instead of 0x46(70)

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>

diff --git a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
index c66a45261a4801e94de76bb8a8e0886963d22d94..fd6f813a94d3dd05dc3759c92ba5888950a3727d 100644 (file)
--- a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
+++ b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
@@ -4,6 +4,8 @@
 \r
   https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf\r
 \r
+  @note Fixed bug in the spec Mailbox3 - RM31 size from 0x45(69) to 0x46(70)\r
+\r
   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
@@ -116,7 +118,7 @@ typedef struct {
   UINT64 FDSS;          ///< Offset 0x3AA DSS Buffer address allocated for IFFS feature\r
   UINT32 FDSP;          ///< Offset 0x3B2 Size of DSS buffer\r
   UINT32 STAT;          ///< Offset 0x3B6 State Indicator\r
-  UINT8  RM31[0x45];    ///< Offset 0x3BA - 0x3FF  Reserved Must be zero\r
+  UINT8  RM31[0x46];    ///< Offset 0x3BA - 0x3FF  Reserved Must be zero. Bug in spec 0x45(69)\r
 } IGD_OPREGION_MBOX3;\r
 \r
 ///\r