// you need to subtact out the size of the PE/COFF header to get\r
// get the offset that matches the link map. \r
//\r
- DEBUG ((EFI_D_ERROR, "loadded at 0x%08x (PE/COFF offset) 0x%x (ELF or Mach-O offset) 0x%x", ImageBase, Offset, Offset - PeCoffSizeOfHeader));\r
+ DEBUG ((EFI_D_ERROR, "loaded at 0x%08x (PE/COFF offset) 0x%x (ELF or Mach-O offset) 0x%x", ImageBase, Offset, Offset - PeCoffSizeOfHeader));\r
+ \r
+ // If we come from an image it is safe to show the instruction. We know it should not fault\r
+ if ((SystemContext.SystemContextArm->CPSR & 0x20) == 0) {\r
+ // ARM\r
+ DEBUG ((EFI_D_ERROR, "\nFaulting Instruction 0x%08x", *(UINT32 *)(UINTN)SystemContext.SystemContextArm->PC));\r
+ } else {\r
+ // Thumb\r
+ DEBUG ((EFI_D_ERROR, "\nFaulting Instruction 0x%04x", *(UINT16 *)(UINTN)SystemContext.SystemContextArm->PC));\r
+ }\r
}\r
DEBUG_CODE_END ();\r
DEBUG ((EFI_D_ERROR, "\n R0 0x%08x R1 0x%08x R2 0x%08x R3 0x%08x\n", SystemContext.SystemContextArm->R0, SystemContext.SystemContextArm->R1, SystemContext.SystemContextArm->R2, SystemContext.SystemContextArm->R3));\r
\r
// EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
// EntryValue: values at bit positions specified by EntryMask\r
-\r
+ EntryMask = ARM_PAGE_DESC_TYPE_MASK;\r
+ EntryValue = ARM_PAGE_TYPE_SMALL;\r
// Although the PI spec is unclear on this the GCD guarantees that only\r
// one Attribute bit is set at a time, so we can safely use a switch statement\r
switch (Attributes) {\r
case EFI_MEMORY_UC:\r
// modify cacheability attributes\r
- EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+ EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
// map to strongly ordered\r
- EntryValue = 0; // TEX[2:0] = 0, C=0, B=0\r
+ EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0\r
break;\r
\r
case EFI_MEMORY_WC:\r
// modify cacheability attributes\r
- EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+ EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
// map to normal non-cachable\r
- EntryValue = (0x1 << ARM_SMALL_PAGE_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r
+ EntryValue |= (0x1 << ARM_SMALL_PAGE_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r
break;\r
\r
case EFI_MEMORY_WT:\r
// modify cacheability attributes\r
- EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+ EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
// write through with no-allocate\r
- EntryValue = ARM_PAGE_C; // TEX [2:0] = 0, C=1, B=0\r
+ EntryValue |= ARM_PAGE_C; // TEX [2:0] = 0, C=1, B=0\r
break;\r
\r
case EFI_MEMORY_WB:\r
// modify cacheability attributes\r
- EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+ EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
// write back (with allocate)\r
- EntryValue = (0x1 << ARM_SMALL_PAGE_TEX_SHIFT) | ARM_PAGE_C | ARM_PAGE_B; // TEX [2:0] = 001, C=1, B=1\r
+ EntryValue |= (0x1 << ARM_SMALL_PAGE_TEX_SHIFT) | ARM_PAGE_C | ARM_PAGE_B; // TEX [2:0] = 001, C=1, B=1\r
break;\r
\r
case EFI_MEMORY_WP:\r
case EFI_MEMORY_UCE:\r
// cannot be implemented UEFI definition unclear for ARM\r
// Cause a page fault if these ranges are accessed.\r
- EntryMask = 0x3;\r
- EntryValue = 0;\r
+ EntryValue = ARM_PAGE_TYPE_FAULT;\r
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r
break;\r
\r
)\r
{\r
EFI_STATUS Status;\r
- \r
- //\r
+DEBUG ((EFI_D_ERROR, "CpuReconvertPagesPages(%lx, %x, %lx, %lx)\n", Address, Length, VirtualMask, Attributes));\r
+ASSERT (FALSE);\r
+//\r
// Unmap the alaised Address\r
//\r
Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0);\r