Missed a fix in the Cpu Driver. Added some more debug for Execption handling and...

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9789 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Drivers/CpuDxe/Exception.c b/ArmPkg/Drivers/CpuDxe/Exception.c
index f0b682d18d69592dc08c2233c6e37ae5014d7067..d46971b33cc6e05636c0c4c938096818081ef3bd 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/Exception.c
+++ b/ArmPkg/Drivers/CpuDxe/Exception.c
@@ -311,7 +311,16 @@ CommonCExceptionHandler (
       // you need to subtact out the size of the PE/COFF header to get\r
       // get the offset that matches the link map. \r
       //\r
-      DEBUG ((EFI_D_ERROR, "loadded at 0x%08x (PE/COFF offset) 0x%x (ELF or Mach-O offset) 0x%x", ImageBase, Offset, Offset - PeCoffSizeOfHeader));\r
+      DEBUG ((EFI_D_ERROR, "loaded at 0x%08x (PE/COFF offset) 0x%x (ELF or Mach-O offset) 0x%x", ImageBase, Offset, Offset - PeCoffSizeOfHeader));\r
+      \r
+      // If we come from an image it is safe to show the instruction. We know it should not fault\r
+      if ((SystemContext.SystemContextArm->CPSR & 0x20) == 0) {\r
+        // ARM\r
+        DEBUG ((EFI_D_ERROR, "\nFaulting Instruction 0x%08x", *(UINT32 *)(UINTN)SystemContext.SystemContextArm->PC));\r
+      } else {\r
+        // Thumb\r
+        DEBUG ((EFI_D_ERROR, "\nFaulting Instruction 0x%04x", *(UINT16 *)(UINTN)SystemContext.SystemContextArm->PC));\r
+      }\r
     }\r
   DEBUG_CODE_END ();\r
   DEBUG ((EFI_D_ERROR, "\n  R0 0x%08x   R1 0x%08x   R2 0x%08x   R3 0x%08x\n", SystemContext.SystemContextArm->R0, SystemContext.SystemContextArm->R1, SystemContext.SystemContextArm->R2, SystemContext.SystemContextArm->R3));\r

diff --git a/ArmPkg/Drivers/CpuDxe/Mmu.c b/ArmPkg/Drivers/CpuDxe/Mmu.c
index 55e049850f6570f0bb03ccea71e673456047cbbe..6d512592c29bc05c2daa82fc3b5153f8ffcf2bbe 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/Mmu.c
+++ b/ArmPkg/Drivers/CpuDxe/Mmu.c
@@ -440,36 +440,37 @@ UpdatePageEntries (
 \r
   // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
   // EntryValue: values at bit positions specified by EntryMask\r
-\r
+  EntryMask = ARM_PAGE_DESC_TYPE_MASK;\r
+  EntryValue = ARM_PAGE_TYPE_SMALL;\r
   // Although the PI spec is unclear on this the GCD guarantees that only\r
   // one Attribute bit is set at a time, so we can safely use a switch statement\r
   switch (Attributes) {\r
     case EFI_MEMORY_UC:\r
       // modify cacheability attributes\r
-      EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+      EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
       // map to strongly ordered\r
-      EntryValue = 0; // TEX[2:0] = 0, C=0, B=0\r
+      EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0\r
       break;\r
 \r
     case EFI_MEMORY_WC:\r
       // modify cacheability attributes\r
-      EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+      EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
       // map to normal non-cachable\r
-      EntryValue = (0x1 << ARM_SMALL_PAGE_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r
+      EntryValue |= (0x1 << ARM_SMALL_PAGE_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r
       break;\r
 \r
     case EFI_MEMORY_WT:\r
       // modify cacheability attributes\r
-      EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+      EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
       // write through with no-allocate\r
-      EntryValue = ARM_PAGE_C; // TEX [2:0] = 0, C=1, B=0\r
+      EntryValue |= ARM_PAGE_C; // TEX [2:0] = 0, C=1, B=0\r
       break;\r
 \r
     case EFI_MEMORY_WB:\r
       // modify cacheability attributes\r
-      EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+      EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
       // write back (with allocate)\r
-      EntryValue = (0x1 << ARM_SMALL_PAGE_TEX_SHIFT) | ARM_PAGE_C | ARM_PAGE_B; // TEX [2:0] = 001, C=1, B=1\r
+      EntryValue |= (0x1 << ARM_SMALL_PAGE_TEX_SHIFT) | ARM_PAGE_C | ARM_PAGE_B; // TEX [2:0] = 001, C=1, B=1\r
       break;\r
 \r
     case EFI_MEMORY_WP:\r
@@ -477,8 +478,7 @@ UpdatePageEntries (
     case EFI_MEMORY_UCE:\r
       // cannot be implemented UEFI definition unclear for ARM\r
       // Cause a page fault if these ranges are accessed.\r
-      EntryMask   = 0x3;\r
-      EntryValue = 0;\r
+      EntryValue = ARM_PAGE_TYPE_FAULT;\r
       DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r
       break;\r
 \r
@@ -861,8 +861,9 @@ CpuReconvertPagesPages (
   )\r
 {\r
   EFI_STATUS      Status;\r
-  \r
-  //\r
+DEBUG ((EFI_D_ERROR, "CpuReconvertPagesPages(%lx, %x, %lx, %lx)\n", Address, Length, VirtualMask, Attributes));\r
+ASSERT (FALSE);\r
+//\r
   // Unmap the alaised Address\r
   //\r
   Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0);\r

diff --git a/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.c b/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.c
index 80e7c8c4729c4a611766aba4395eca350769c2f0..cdf6a85137c65b44359d818b4c865bb4ecedbd32 100644 (file)
--- a/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.c
+++ b/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.c
@@ -292,7 +292,7 @@ UncachedFreeAlignedPages (
   Status = gVirtualUncachedPages->RevertPages (gVirtualUncachedPages, Memory, Pages * EFI_PAGE_SIZE, PcdGet64 (PcdArmUncachedMemoryMask), gAttributes);\r
 \r
   \r
-  Status = gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) Buffer, Pages);\r
+  Status = gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) Memory, Pages);\r
   ASSERT_EFI_ERROR (Status);\r
 }\r
 \r

diff --git a/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c b/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c
index 060ba6bf980ea596cdf907941ec868f8023f68a7..830212e4d7ade9139c275304783db51c4fea92ee 100644 (file)
--- a/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c
+++ b/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c
@@ -207,7 +207,7 @@ UncachedInternalAllocateAlignedPages (
   }\r
   \r
   if (AlignedMemory != 0) {\r
-    FlushCache(AlignedMemory, EFI_PAGES_TO_SIZE(Pages));\r
+    FlushCache (AlignedMemory, EFI_PAGES_TO_SIZE(Pages));\r
     AlignedMemory = (UINTN)ConvertToUncachedAddress((VOID *)AlignedMemory);\r
   }\r
   \r
@@ -318,7 +318,7 @@ UncachedInternalAllocateAlignedPool (
   *FreePointer        = RawAddress;\r
 \r
   if (AlignedAddress != 0) {\r
-    FlushCache(AlignedAddress, AllocationSize);\r
+    FlushCache (AlignedAddress, AllocationSize);\r
     AlignedAddress = (UINTN)ConvertToUncachedAddress((VOID *)AlignedAddress);\r
   }\r
 \r

diff --git a/BeagleBoardPkg/PciEmulation/PciEmulation.c b/BeagleBoardPkg/PciEmulation/PciEmulation.c
index dee054197163650a3f3cebae8e545503666ef982..f558597932f7d81837e48606232054a2f27bde8d 100644 (file)
--- a/BeagleBoardPkg/PciEmulation/PciEmulation.c
+++ b/BeagleBoardPkg/PciEmulation/PciEmulation.c
@@ -318,12 +318,7 @@ PciIoUnmap (
     // Make sure we read buffer from uncached memory and not the cache
     //
     gCpu->FlushDataCache (gCpu, Map->HostAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);
-  } else if (Map->Operation == EfiPciOperationBusMasterCommonBuffer) {
-    //
-    // CPU was using uncached address, so anything in the cached range is bogus
-    //
-    gCpu->FlushDataCache (gCpu, Map->DeviceAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);   
-  }
+  } 
   
   FreePool (Map);