+/** @file\r
+ MSR Definitions for Intel processors based on the Broadwell microarchitecture.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
+ December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-12.\r
+\r
+**/\r
+\r
+#ifndef __BROADWELL_MSR_H__\r
+#define __BROADWELL_MSR_H__\r
+\r
+#include <Register/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
+ Facilities.".\r
+\r
+ @param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS);\r
+ AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Ovf_PMC0.\r
+ ///\r
+ UINT32 Ovf_PMC0:1;\r
+ ///\r
+ /// [Bit 1] Ovf_PMC1.\r
+ ///\r
+ UINT32 Ovf_PMC1:1;\r
+ ///\r
+ /// [Bit 2] Ovf_PMC2.\r
+ ///\r
+ UINT32 Ovf_PMC2:1;\r
+ ///\r
+ /// [Bit 3] Ovf_PMC3.\r
+ ///\r
+ UINT32 Ovf_PMC3:1;\r
+ UINT32 Reserved1:28;\r
+ ///\r
+ /// [Bit 32] Ovf_FixedCtr0.\r
+ ///\r
+ UINT32 Ovf_FixedCtr0:1;\r
+ ///\r
+ /// [Bit 33] Ovf_FixedCtr1.\r
+ ///\r
+ UINT32 Ovf_FixedCtr1:1;\r
+ ///\r
+ /// [Bit 34] Ovf_FixedCtr2.\r
+ ///\r
+ UINT32 Ovf_FixedCtr2:1;\r
+ UINT32 Reserved2:20;\r
+ ///\r
+ /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.4.2, "Table of Physical\r
+ /// Addresses (ToPA).".\r
+ ///\r
+ UINT32 Trace_ToPA_PMI:1;\r
+ UINT32 Reserved3:5;\r
+ ///\r
+ /// [Bit 61] Ovf_Uncore.\r
+ ///\r
+ UINT32 Ovf_Uncore:1;\r
+ ///\r
+ /// [Bit 62] Ovf_BufDSSAVE.\r
+ ///\r
+ UINT32 OvfBuf:1;\r
+ ///\r
+ /// [Bit 63] CondChgd.\r
+ ///\r
+ UINT32 CondChgd:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER;\r
+\r
+\r
+/**\r
+ Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
+ specific C-state code names, unrelated to MWAIT extension C-state parameters\r
+ or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
+\r
+ @param ECX MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);\r
+ AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r
+ /// processor-specific C-state code name (consuming the least power) for\r
+ /// the package. The default is set as factory-configured package C-state\r
+ /// limit. The following C-state code name encodings are supported: 0000b:\r
+ /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6\r
+ /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.\r
+ ///\r
+ UINT32 Limit:4;\r
+ UINT32 Reserved1:6;\r
+ ///\r
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
+ ///\r
+ UINT32 IO_MWAIT:1;\r
+ UINT32 Reserved2:4;\r
+ ///\r
+ /// [Bit 15] CFG Lock (R/WO).\r
+ ///\r
+ UINT32 CFGLock:1;\r
+ UINT32 Reserved3:9;\r
+ ///\r
+ /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
+ ///\r
+ UINT32 C3AutoDemotion:1;\r
+ ///\r
+ /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
+ ///\r
+ UINT32 C1AutoDemotion:1;\r
+ ///\r
+ /// [Bit 27] Enable C3 Undemotion (R/W).\r
+ ///\r
+ UINT32 C3Undemotion:1;\r
+ ///\r
+ /// [Bit 28] Enable C1 Undemotion (R/W).\r
+ ///\r
+ UINT32 C1Undemotion:1;\r
+ ///\r
+ /// [Bit 29] Enable Package C-State Auto-demotion (R/W).\r
+ ///\r
+ UINT32 CStateAutoDemotion:1;\r
+ ///\r
+ /// [Bit 30] Enable Package C-State Undemotion (R/W).\r
+ ///\r
+ UINT32 CStateUndemotion:1;\r
+ UINT32 Reserved4:1;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);\r
+ @endcode\r
+**/\r
+#define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
+ /// limit of 1 core active.\r
+ ///\r
+ UINT32 Maximum1C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
+ /// limit of 2 core active.\r
+ ///\r
+ UINT32 Maximum2C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
+ /// limit of 3 core active.\r
+ ///\r
+ UINT32 Maximum3C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
+ /// limit of 4 core active.\r
+ ///\r
+ UINT32 Maximum4C:8;\r
+ ///\r
+ /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
+ /// limit of 5core active.\r
+ ///\r
+ UINT32 Maximum5C:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
+ /// limit of 6core active.\r
+ ///\r
+ UINT32 Maximum6C:8;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;\r
+\r
+#endif\r
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