-;------------------------------------------------------------------------------\r
+;; @file\r
+; Provide FSP API entry points.\r
;\r
-; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
;\r
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Abstract:\r
-;\r
-; Provide FSP API entry points.\r
-;\r
-;------------------------------------------------------------------------------\r
+;;\r
\r
.586p\r
.model flat,C\r
EXTERN PcdGet32(PcdTemporaryRamBase):DWORD\r
EXTERN PcdGet32(PcdTemporaryRamSize):DWORD\r
EXTERN PcdGet32(PcdFspTemporaryRamSize):DWORD\r
+EXTERN PcdGet32(PcdFspAreaSize):DWORD\r
\r
;\r
; Following functions will be provided in C\r
;\r
-EXTERN FspImageSizeOffset:DWORD\r
+\r
EXTERN SecStartup:PROC\r
EXTERN FspApiCallingCheck:PROC\r
\r
;\r
EXTERN GetFspBaseAddress:PROC\r
EXTERN GetBootFirmwareVolumeOffset:PROC\r
-EXTERN PlatformTempRamInit:PROC\r
EXTERN Pei2LoaderSwitchStack:PROC\r
EXTERN FspSelfCheck(FspSelfCheckDflt):PROC\r
EXTERN PlatformBasicInit(PlatformBasicInitDflt):PROC\r
EXTERN LoadUcode(LoadUcodeDflt):PROC\r
+EXTERN SecPlatformInit:PROC\r
+EXTERN SecCarInit:PROC\r
\r
;\r
; Define the data length that we saved on the stack top\r
DATA_LEN_OF_MCUD EQU 18h\r
DATA_LEN_AT_STACK_TOP EQU (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4)\r
\r
+;\r
+; Define SSE macros\r
+;\r
+LOAD_MMX_EXT MACRO ReturnAddress, MmxRegister\r
+ mov esi, ReturnAddress\r
+ movd MmxRegister, esi ; save ReturnAddress into MM7 \r
+ENDM\r
+\r
+CALL_MMX_EXT MACRO RoutineLabel, MmxRegister\r
+ local ReturnAddress\r
+ mov esi, offset ReturnAddress\r
+ movd MmxRegister, esi ; save ReturnAddress into MM7\r
+ jmp RoutineLabel\r
+ReturnAddress:\r
+ENDM\r
+\r
+RET_ESI_EXT MACRO MmxRegister\r
+ movd esi, MmxRegister ; restore ESP from MM7\r
+ jmp esi\r
+ENDM\r
+\r
+CALL_MMX MACRO RoutineLabel\r
+ CALL_MMX_EXT RoutineLabel, mm7\r
+ENDM\r
+\r
+RET_ESI MACRO\r
+ RET_ESI_EXT mm7 \r
+ENDM\r
+\r
;------------------------------------------------------------------------------\r
FspSelfCheckDflt PROC NEAR PUBLIC\r
; Inputs:\r
;\r
;\r
; Save return address to EBP\r
- mov ebp, eax\r
+ movd ebp, mm7\r
\r
cmp esp, 0\r
jz paramerror\r
\r
LoadUcodeDflt ENDP\r
\r
+EstablishStackFsp PROC NEAR PRIVATE\r
+ ; Following is the code copied from BYTFSP, need to figure out what it is doing..\r
+ ;\r
+ ; Save parameter pointer in edx \r
+ ;\r
+ mov edx, dword ptr [esp + 4] \r
+ \r
+ ;\r
+ ; Enable FSP STACK\r
+ ;\r
+ mov esp, PcdGet32 (PcdTemporaryRamBase)\r
+ add esp, PcdGet32 (PcdTemporaryRamSize) \r
+\r
+ push DATA_LEN_OF_MCUD ; Size of the data region \r
+ push 4455434Dh ; Signature of the data region 'MCUD'\r
+ push dword ptr [edx + 12] ; Code size\r
+ push dword ptr [edx + 8] ; Code base\r
+ cmp edx, 0 ; Is parameter pointer valid ?\r
+ jz InvalidMicrocodeRegion\r
+ push dword ptr [edx + 4] ; Microcode size\r
+ push dword ptr [edx] ; Microcode base \r
+ jmp @F\r
+\r
+InvalidMicrocodeRegion:\r
+ push 0 ; Microcode size\r
+ push 0 ; Microcode base\r
+ \r
+@@:\r
+ ;\r
+ ; Save API entry/exit timestamp into stack\r
+ ;\r
+ push DATA_LEN_OF_PER0 ; Size of the data region \r
+ push 30524550h ; Signature of the data region 'PER0'\r
+ movd eax, xmm4\r
+ push eax\r
+ movd eax, xmm5\r
+ push eax\r
+ rdtsc\r
+ push edx\r
+ push eax\r
+\r
+ ;\r
+ ; Terminator for the data on stack\r
+ ; \r
+ push 0\r
+\r
+ ;\r
+ ; Set ECX/EDX to the bootloader temporary memory range\r
+ ;\r
+ mov ecx, PcdGet32 (PcdTemporaryRamBase)\r
+ mov edx, ecx\r
+ add edx, PcdGet32 (PcdTemporaryRamSize)\r
+ sub edx, PcdGet32 (PcdFspTemporaryRamSize)\r
+\r
+ xor eax, eax\r
+ \r
+ RET_ESI\r
+\r
+EstablishStackFsp ENDP\r
+\r
+\r
;----------------------------------------------------------------------------\r
; TempRamInit API\r
;\r
; Save timestamp into XMM4 & XMM5\r
;\r
rdtsc\r
- SAVE_EAX\r
- SAVE_EDX\r
-\r
- ;\r
- ; Check Parameter\r
- ;\r
- mov eax, dword ptr [esp + 4]\r
- cmp eax, 0\r
- mov eax, 80000002h\r
- jz NemInitExit\r
-\r
+ movd xmm4, edx\r
+ movd xmm5, eax\r
+ \r
;\r
; CPUID/DeviceID check\r
;\r
cmp eax, 0\r
jnz NemInitExit\r
\r
- ;\r
- ; Platform Basic Init.\r
- ;\r
- mov eax, @F\r
- jmp PlatformBasicInit\r
-@@:\r
- cmp eax, 0\r
- jnz NemInitExit\r
+ CALL_MMX SecPlatformInit\r
\r
- ;\r
+ ; Call Sec CAR Init\r
+ CALL_MMX SecCarInit\r
+ \r
+ ; @todo: ESP has been modified, we need to restore here.\r
+ LOAD_REGS\r
+ SAVE_REGS\r
; Load microcode\r
- ;\r
- mov eax, @F\r
- add esp, 4\r
- jmp LoadUcode\r
-@@:\r
- LOAD_ESP\r
- cmp eax, 0\r
- jnz NemInitExit\r
-\r
- ;\r
- ; Call platform NEM init\r
- ;\r
- mov eax, @F\r
- add esp, 4\r
- jmp PlatformTempRamInit\r
-@@:\r
- LOAD_ESP\r
- cmp eax, 0\r
- jnz NemInitExit\r
-\r
- ;\r
- ; Save parameter pointer in edx\r
- ;\r
- mov edx, dword ptr [esp + 4]\r
-\r
- ;\r
- ; Enable FSP STACK\r
- ;\r
- mov esp, PcdGet32(PcdTemporaryRamBase)\r
- add esp, PcdGet32(PcdTemporaryRamSize)\r
-\r
- push DATA_LEN_OF_MCUD ; Size of the data region\r
- push 4455434Dh ; Signature of the data region 'MCUD'\r
- push dword ptr [edx + 4] ; Microcode size\r
- push dword ptr [edx + 0] ; Microcode base\r
- push dword ptr [edx + 12] ; Code size\r
- push dword ptr [edx + 8] ; Code base\r
-\r
- ;\r
- ; Save API entry/exit timestamp into stack\r
- ;\r
- push DATA_LEN_OF_PER0 ; Size of the data region\r
- push 30524550h ; Signature of the data region 'PER0'\r
- rdtsc\r
- push edx\r
- push eax\r
- LOAD_EAX\r
- LOAD_EDX\r
- push edx\r
- push eax\r
-\r
- ;\r
- ; Terminator for the data on stack\r
- ;\r
- push 0\r
+ CALL_MMX LoadUcode\r
\r
- ;\r
- ; Set ECX/EDX to the bootloader temporary memory range\r
- ;\r
- mov ecx, PcdGet32(PcdTemporaryRamBase)\r
- mov edx, ecx\r
- add edx, PcdGet32(PcdTemporaryRamSize)\r
- sub edx, PcdGet32(PcdFspTemporaryRamSize)\r
-\r
- xor eax, eax\r
+ CALL_MMX EstablishStackFsp\r
\r
NemInitExit:\r
;\r
;\r
;----------------------------------------------------------------------------\r
FspInitApi PROC NEAR PUBLIC\r
+ mov eax, 1\r
+ jmp FspApiCommon\r
+ FspInitApi ENDP\r
+\r
+;----------------------------------------------------------------------------\r
+; NotifyPhase API\r
+;\r
+; This FSP API will notify the FSP about the different phases in the boot\r
+; process\r
+;\r
+;----------------------------------------------------------------------------\r
+NotifyPhaseApi PROC C PUBLIC\r
+ mov eax, 2\r
+ jmp FspApiCommon\r
+NotifyPhaseApi ENDP\r
+\r
+;----------------------------------------------------------------------------\r
+; FspMemoryInit API\r
+;\r
+; This FSP API is called after TempRamInit and initializes the memory.\r
+;\r
+;----------------------------------------------------------------------------\r
+FspMemoryInitApi PROC NEAR PUBLIC\r
+ mov eax, 3\r
+ jmp FspApiCommon\r
+FspMemoryInitApi ENDP\r
+\r
+\r
+;----------------------------------------------------------------------------\r
+; TempRamExitApi API\r
+;\r
+; This API tears down temporary RAM\r
+;\r
+;----------------------------------------------------------------------------\r
+TempRamExitApi PROC C PUBLIC\r
+ mov eax, 4\r
+ jmp FspApiCommon\r
+TempRamExitApi ENDP\r
+\r
+\r
+;----------------------------------------------------------------------------\r
+; FspSiliconInit API\r
+;\r
+; This FSP API initializes the CPU and the chipset including the IO\r
+; controllers in the chipset to enable normal operation of these devices.\r
+;\r
+;----------------------------------------------------------------------------\r
+FspSiliconInitApi PROC C PUBLIC\r
+ mov eax, 5\r
+ jmp FspApiCommon\r
+FspSiliconInitApi ENDP\r
+\r
+;----------------------------------------------------------------------------\r
+; FspApiCommon API\r
+;\r
+; This is the FSP API common entry point to resume the FSP execution\r
+;\r
+;----------------------------------------------------------------------------\r
+FspApiCommon PROC C PUBLIC\r
;\r
- ; Stack must be ready\r
+ ; EAX holds the API index\r
;\r
- push 087654321h\r
- pop eax\r
- cmp eax, 087654321h\r
+\r
+ ;\r
+ ; Stack must be ready\r
+ ; \r
+ push eax\r
+ add esp, 4\r
+ cmp eax, dword ptr [esp - 4]\r
jz @F\r
mov eax, 080000003h\r
jmp exit\r
\r
@@:\r
;\r
- ; Additional check\r
+ ; Verify the calling condition\r
;\r
pushad\r
- push 1\r
+ push eax\r
call FspApiCallingCheck\r
add esp, 4\r
- mov dword ptr [esp + 4 * 7], eax\r
- popad\r
cmp eax, 0\r
jz @F\r
- jmp exit\r
+ mov dword ptr [esp + 4 * 7], eax\r
+ popad\r
+ ret\r
\r
@@:\r
+ popad\r
+ cmp eax, 1 ; FspInit API\r
+ jz @F\r
+ cmp eax, 3 ; FspMemoryInit API\r
+ jz @F\r
+ jmp Pei2LoaderSwitchStack\r
+\r
+@@: \r
+ ;\r
+ ; FspInit and FspMemoryInit APIs, setup the initial stack frame\r
+ ; \r
+ \r
;\r
; Store the address in FSP which will return control to the BL\r
;\r
\r
; Reserve 8 bytes for IDT save/restore\r
sub esp, 8\r
- sidt fword ptr [esp]\r
+ sidt fword ptr [esp] \r
\r
;\r
; Setup new FSP stack\r
;\r
- mov eax, esp\r
+ mov edi, esp\r
mov esp, PcdGet32(PcdTemporaryRamBase)\r
add esp, PcdGet32(PcdTemporaryRamSize)\r
sub esp, (DATA_LEN_AT_STACK_TOP + 40h)\r
\r
;\r
- ; Save the bootloader's stack pointer\r
+ ; Pass the API Idx to SecStartup\r
;\r
push eax\r
+ \r
+ ;\r
+ ; Pass the bootloader stack to SecStartup\r
+ ;\r
+ push edi\r
\r
;\r
; Pass entry point of the PEI core\r
;\r
call GetFspBaseAddress\r
- mov edi, FspImageSizeOffset\r
- mov edi, DWORD PTR [eax + edi]\r
- add edi, eax\r
+ mov edi, eax\r
+ add edi, PcdGet32 (PcdFspAreaSize) \r
sub edi, 20h\r
- add eax, DWORD PTR [edi]\r
+ add eax, DWORD PTR ds:[edi]\r
push eax\r
\r
;\r
;\r
call SecStartup\r
\r
-exit:\r
+exit: \r
ret\r
\r
-FspInitApi ENDP\r
-\r
-;----------------------------------------------------------------------------\r
-; NotifyPhase API\r
-;\r
-; This FSP API will notify the FSP about the different phases in the boot\r
-; process\r
-;\r
-;----------------------------------------------------------------------------\r
-NotifyPhaseApi PROC C PUBLIC\r
- ;\r
- ; Stack must be ready\r
- ;\r
- push 087654321h\r
- pop eax\r
- cmp eax, 087654321h\r
- jz @F\r
- mov eax, 080000003h\r
- jmp err_exit\r
-\r
-@@:\r
- ;\r
- ; Verify the calling condition\r
- ;\r
- pushad\r
- push 2\r
- call FspApiCallingCheck\r
- add esp, 4\r
- mov dword ptr [esp + 4 * 7], eax\r
- popad\r
-\r
- cmp eax, 0\r
- jz @F\r
-\r
- ;\r
- ; Error return\r
- ;\r
-err_exit:\r
- ret\r
-\r
-@@:\r
- jmp Pei2LoaderSwitchStack\r
-\r
-NotifyPhaseApi ENDP\r
-\r
+FspApiCommon ENDP\r
\r
END\r
#------------------------------------------------------------------------------\r
#\r
-# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
#\r
# Following functions will be provided in C\r
#\r
-ASM_GLOBAL ASM_PFX(FspImageSizeOffset)\r
ASM_GLOBAL ASM_PFX(SecStartup)\r
ASM_GLOBAL ASM_PFX(FspApiCallingCheck)\r
\r
#\r
# Save return address to EBP\r
#\r
- movl %eax, %ebp\r
+ movd %xmm7, %ebp\r
+\r
cmpl $0x00, %esp\r
jz ParamError\r
movl (%esp), %eax #dword ptr [] Parameter pointer\r
jmp *%ebp\r
\r
\r
+#----------------------------------------------------------------------------\r
+# EstablishStackFsp\r
+#\r
+# Following is the code copied from BYTFSP, need to figure out what it is doing..\r
+#\r
+#----------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(EstablishStackFsp)\r
+ASM_PFX(EstablishStackFsp):\r
+ #\r
+ # Save parameter pointer in edx \r
+ #\r
+ movl 4(%esp), %edx\r
+ \r
+ #\r
+ # Enable FSP STACK\r
+ #\r
+ movl PcdGet32(PcdTemporaryRamBase), %esp\r
+ addl PcdGet32(PcdTemporaryRamSize), %esp\r
+\r
+ pushl $DATA_LEN_OF_MCUD # Size of the data region\r
+ pushl $0x4455434D # Signature of the data region 'MCUD'\r
+ pushl 12(%edx) # Code size\r
+ pushl 8(%edx) # Code base\r
+ cmpl $0, %edx # Is parameter pointer valid ?\r
+ jz InvalidMicrocodeRegion\r
+ pushl 4(%edx) # Microcode size\r
+ pushl (%edx) # Microcode base\r
+ jmp EstablishStackFspExit\r
+\r
+InvalidMicrocodeRegion:\r
+ push $0 # Microcode size\r
+ push $0 # Microcode base\r
+ \r
+EstablishStackFspExit:\r
+ #\r
+ # Save API entry/exit timestamp into stack\r
+ #\r
+ pushl $DATA_LEN_OF_PER0 # Size of the data region\r
+ pushl $0x30524550 # Signature of the data region 'PER0'\r
+ movd %xmm4, %eax\r
+ pushl %eax\r
+ movd %xmm5, %eax\r
+ pushl %eax\r
+ rdtsc\r
+ pushl %edx\r
+ pushl %eax\r
+\r
+ #\r
+ # Terminator for the data on stack\r
+ # \r
+ push $0x00\r
+\r
+ #\r
+ # Set ECX/EDX to the bootloader temporary memory range\r
+ #\r
+ movl PcdGet32 (PcdTemporaryRamBase), %ecx\r
+ movl %ecx, %edx\r
+ addl PcdGet32 (PcdTemporaryRamSize), %edx\r
+ subl PcdGet32 (PcdFspTemporaryRamSize), %edx\r
+\r
+ xorl %eax, %eax\r
+ \r
+ movd %mm7, %esi #RET_ESI\r
+ jmp *%esi\r
+\r
#----------------------------------------------------------------------------\r
# TempRamInit API\r
#\r
# Save timestamp into XMM4 & XMM5\r
#\r
rdtsc\r
- SAVE_EAX\r
- SAVE_EDX\r
-\r
- #\r
- # Check Parameter\r
- #\r
- movl 4(%esp), %eax\r
- cmpl $0x00, %eax\r
- movl $0x80000002, %eax\r
- jz NemInitExit\r
+ movd %edx, %xmm4\r
+ movd %eax, %xmm5\r
\r
#\r
# CPUID/DeviceID check\r
#\r
movl $TempRamInitApiL0, %eax\r
- jmp ASM_PFX(FspSelfCheckDflt) # Note: ESP can not be changed.\r
+ jmp ASM_PFX(FspSelfCheckDflt) # @note: ESP can not be changed.\r
TempRamInitApiL0:\r
cmpl $0x00, %eax\r
jnz NemInitExit\r
\r
#\r
- # Platform Basic Init.\r
+ # Sec Platform Init\r
#\r
- movl $TempRamInitApiL1, %eax\r
- jmp ASM_PFX(PlatformBasicInitDflt)\r
+ movl $TempRamInitApiL1, %esi #CALL_MMX SecPlatformInit\r
+ movd %mm7, %esi\r
+ jmp ASM_PFX(SecPlatformInit)\r
TempRamInitApiL1:\r
- cmpl $0x00, %eax\r
- jnz NemInitExit\r
\r
#\r
- # Load microcode\r
+ # Call Sec CAR Init\r
#\r
- movl $TempRamInitApiL2, %eax\r
- addl $0x04, %esp\r
- jmp LoadUcode\r
-\r
+ movl $TempRamInitApiL2, %esi #CALL_MMX SecCarInit\r
+ movd %mm7, %esi\r
+ jmp ASM_PFX(SecCarInit)\r
TempRamInitApiL2:\r
- LOAD_ESP\r
- cmpl $0x00, %eax\r
- jnz NemInitExit\r
-\r
- #\r
- # Call platform NEM init\r
- #\r
- movl $TempRamInitApiL3, %eax\r
- addl $0x04, %esp\r
- jmp ASM_PFX(PlatformTempRamInit)\r
-TempRamInitApiL3:\r
- subl $0x04, %esp\r
- cmpl $0x00, %eax\r
- jnz NemInitExit\r
-\r
- #\r
- # Save parameter pointer in edx\r
- #\r
- movl 4(%esp), %edx\r
-\r
- #\r
- # Enable FSP STACK\r
- #\r
- movl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase), %esp\r
- addl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize), %esp\r
\r
- pushl $DATA_LEN_OF_MCUD # Size of the data region\r
- pushl $0x4455434D # Signature of the data region 'MCUD'\r
- pushl 4(%edx) # Microcode size\r
- pushl (%edx) # Microcode base\r
- pushl 12(%edx) # Code size\r
- pushl 8(%edx) # Code base\r
+ # @todo: ESP has been modified, we need to restore here.\r
\r
- #\r
- # Save API entry/exit timestamp into stack\r
- #\r
- pushl $DATA_LEN_OF_PER0 # Size of the data region\r
- pushl $0x30524550 # Signature of the data region 'PER0'\r
- rdtsc\r
- pushl %edx\r
- pushl %eax\r
- LOAD_EAX\r
- LOAD_EDX\r
- pushl %edx\r
- pushl %eax\r
+ LOAD_REGS\r
+ SAVE_REGS\r
\r
#\r
- # Terminator for the data on stack\r
+ # Load microcode\r
#\r
- pushl $0x00\r
+ movl $TempRamInitApiL3, %esi #CALL_MMX LoadUcode\r
+ movd %mm7, %esi\r
+ jmp ASM_PFX(LoadUcode)\r
+TempRamInitApiL3:\r
\r
#\r
- # Set ECX/EDX to the bootloader temporary memory range\r
+ # EstablishStackFsp\r
#\r
- movl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase), %ecx\r
- movl %ecx, %edx\r
- addl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize), %edx\r
- subl ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize), %edx\r
-\r
- xorl %eax, %eax\r
+ movl $TempRamInitApiL4, %esi #CALL_MMX EstablishStackFsp\r
+ movd %mm7, %esi\r
+ jmp ASM_PFX(EstablishStackFsp)\r
+TempRamInitApiL4:\r
\r
NemInitExit:\r
#\r
LOAD_REGS\r
ret\r
\r
-\r
#----------------------------------------------------------------------------\r
# FspInit API\r
#\r
#----------------------------------------------------------------------------\r
ASM_GLOBAL ASM_PFX(FspInitApi)\r
ASM_PFX(FspInitApi):\r
+ movl $0x01, %eax\r
+ jmp FspApiCommon\r
+\r
+#----------------------------------------------------------------------------\r
+# NotifyPhase API\r
+#\r
+# This FSP API will notify the FSP about the different phases in the boot\r
+# process\r
+#\r
+#----------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(NotifyPhaseApi)\r
+ASM_PFX(NotifyPhaseApi):\r
+ movl $0x02, %eax\r
+ jmp FspApiCommon\r
+\r
+#----------------------------------------------------------------------------\r
+# FspMemoryInit API\r
+#\r
+# This FSP API is called after TempRamInit and initializes the memory.\r
+#\r
+#----------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(FspMemoryInitApi)\r
+ASM_PFX(FspMemoryInitApi):\r
+ movl $0x03, %eax\r
+ jmp FspApiCommon\r
+\r
+#----------------------------------------------------------------------------\r
+# TempRamExitApi API\r
+#\r
+# This API tears down temporary RAM\r
+#\r
+#----------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(TempRamExitApi)\r
+ASM_PFX(TempRamExitApi):\r
+ movl $0x04, %eax\r
+ jmp FspApiCommon\r
+\r
+#----------------------------------------------------------------------------\r
+# FspSiliconInit API\r
+#\r
+# This FSP API initializes the CPU and the chipset including the IO\r
+# controllers in the chipset to enable normal operation of these devices.\r
+#\r
+#----------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(FspSiliconInitApi)\r
+ASM_PFX(FspSiliconInitApi):\r
+ movl $0x05, %eax\r
+ jmp FspApiCommon\r
+\r
+#----------------------------------------------------------------------------\r
+# FspApiCommon API\r
+#\r
+# This is the FSP API common entry point to resume the FSP execution\r
+#\r
+#----------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(FspApiCommon)\r
+ASM_PFX(FspApiCommon):\r
#\r
- # Stack must be ready\r
+ # EAX holds the API index\r
#\r
- pushl $0x087654321\r
- popl %eax\r
- cmpl $0x087654321, %eax\r
- jz FspInitApiL0\r
+\r
+ #\r
+ # Stack must be ready\r
+ # \r
+ pushl %eax\r
+ addl $0x04, %esp\r
+ cmpl -4(%esp), %eax\r
+ jz FspApiCommonL0\r
movl $0x080000003, %eax\r
- jmp FspInitApiexit\r
+ jmp FspApiCommonExit\r
\r
-FspInitApiL0:\r
+FspApiCommonL0:\r
#\r
- # Additional check\r
+ # Verify the calling condition\r
#\r
- pusha\r
- pushl $0x01\r
+ pushal\r
+ pushl %eax\r
call ASM_PFX(FspApiCallingCheck)\r
addl $0x04, %esp\r
- movl %eax, 28(%esp)\r
- popa\r
cmpl $0x00, %eax\r
- jz FspInitApiL1\r
- jmp FspInitApiexit\r
+ jz FspApiCommonL1\r
+ movl %eax, 0x1C(%esp) # mov dword ptr [esp + 4 * 7], eax\r
+ popal\r
+ ret\r
+\r
+FspApiCommonL1:\r
+ popal\r
+ cmpl $0x01, %eax # FspInit API\r
+ jz FspApiCommonL2\r
+ cmpl $0x03, %eax # FspMemoryInit API\r
+ jz FspApiCommonL2\r
+ jmp Pei2LoaderSwitchStack\r
\r
-FspInitApiL1:\r
+FspApiCommonL2:\r
+ #\r
+ # FspInit and FspMemoryInit APIs, setup the initial stack frame\r
+ # \r
+ \r
#\r
# Store the address in FSP which will return control to the BL\r
#\r
- pushl $FspInitApiexit\r
+ pushl $FspApiCommonExit\r
\r
#\r
# Create a Task Frame in the stack for the Boot Loader\r
#\r
- pushfl # 2 pushf for 4 byte alignment\r
+ pushfl # 2 pushf for 4 byte alignment\r
cli\r
pushal\r
\r
#\r
# Setup new FSP stack\r
#\r
- movl %esp, %eax\r
- movl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase), %esp\r
- addl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize), %esp\r
+ movl %esp, %edi\r
+ movl PcdGet32(PcdTemporaryRamBase), %esp\r
+ addl PcdGet32(PcdTemporaryRamSize), %esp\r
subl $(DATA_LEN_AT_STACK_TOP + 0x40), %esp\r
\r
- # Save the bootloader's stack pointer\r
#\r
- pushl %eax\r
+ # Pass the API Idx to SecStartup\r
+ #\r
+ pushl %eax\r
+ \r
+ #\r
+ # Pass the bootloader stack to SecStartup\r
+ #\r
+ pushl %edi\r
\r
#\r
# Pass entry point of the PEI core\r
#\r
- call ASM_PFX(GetFspBaseAddress)\r
- movl ASM_PFX(FspImageSizeOffset), %edi\r
- movl (%eax, %edi), %edi\r
- addl %eax, %edi\r
- subl $0x20, %edi\r
- addl (%edi), %eax\r
- pushl %eax\r
+ call ASM_PFX(GetFspBaseAddress)\r
+ movl %eax, %edi\r
+ addl PcdGet32(PcdFspAreaSize), %edi\r
+ subl $0x20, %edi\r
+ addl %ds:(%edi), %eax\r
+ pushl %eax\r
\r
#\r
# Pass BFV into the PEI Core\r
# PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,\r
# they are different. The code below can handle both cases.\r
#\r
- call ASM_PFX(GetFspBaseAddress)\r
- movl %eax , %edi\r
- call ASM_PFX(GetBootFirmwareVolumeOffset)\r
- addl %edi ,%eax\r
- pushl %eax\r
+ call ASM_PFX(GetFspBaseAddress)\r
+ movl %eax, %edi\r
+ call ASM_PFX(GetBootFirmwareVolumeOffset)\r
+ addl %edi, %eax\r
+ pushl %eax\r
\r
#\r
# Pass stack base and size into the PEI Core\r
#\r
- movl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase), %eax\r
- addl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize), %eax\r
- subl ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize), %eax\r
- pushl %eax\r
- pushl ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize)\r
+ movl PcdGet32(PcdTemporaryRamBase), %eax\r
+ addl PcdGet32(PcdTemporaryRamSize), %eax\r
+ subl PcdGet32(PcdFspTemporaryRamSize), %eax\r
+ pushl %eax\r
+ pushl PcdGet32(PcdFspTemporaryRamSize)\r
\r
#\r
# Pass Control into the PEI Core\r
#\r
call ASM_PFX(SecStartup)\r
\r
-FspInitApiexit:\r
- ret\r
-\r
-\r
-#----------------------------------------------------------------------------\r
-# NotifyPhase API\r
-#\r
-# This FSP API will notify the FSP about the different phases in the boot\r
-# process\r
-#\r
-#----------------------------------------------------------------------------\r
-ASM_GLOBAL ASM_PFX(NotifyPhaseApi)\r
-ASM_PFX(NotifyPhaseApi):\r
- #\r
- # Stack must be ready\r
- #\r
- pushl $0x0087654321\r
- popl %eax\r
- cmpl $0x087654321, %eax\r
- jz NotifyPhaseApiL0\r
- movl $0x080000003, %eax\r
- jmp NotifyPhaseApiErrExit\r
-\r
-NotifyPhaseApiL0:\r
- #\r
- # Verify the calling condition\r
- #\r
- pusha\r
- pushl $0x02\r
- call ASM_PFX(FspApiCallingCheck)\r
- addl $0x04, %esp\r
- movl %eax, 28(%esp)\r
- popa\r
-\r
- cmpl $0x00, %eax\r
- jz NotifyPhaseApiL1\r
-\r
- #\r
- # Error return\r
- #\r
-NotifyPhaseApiErrExit:\r
+FspApiCommonExit:\r
ret\r
\r
-NotifyPhaseApiL1:\r
- jmp ASM_PFX(Pei2LoaderSwitchStack)\r
-\r
-\r
\r
-#END\r
#------------------------------------------------------------------------------\r
#\r
-# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
# Set OSFXSR bit 9 in CR4\r
#\r
movl %cr4, %eax\r
- or BIT9, %eax\r
+ orl $BIT9, %eax\r
movl %eax, %cr4\r
\r
#\r
#------------------------------------------------------------------------------\r
#\r
-# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
ASM_GLOBAL ASM_PFX(SecSwitchStack)\r
ASM_PFX(SecSwitchStack):\r
#\r
-# Save three register: eax, ebx, ecx\r
+# Save four registers: eax, ebx, ecx, edx\r
#\r
- push %eax\r
- push %ebx\r
- push %ecx\r
- push %edx\r
+ pushl %eax\r
+ pushl %ebx\r
+ pushl %ecx\r
+ pushl %edx\r
\r
#\r
# !!CAUTION!! this function address's is pushed into stack after\r
#\r
# Fixup the ebp point to permenent memory\r
#\r
-\r
movl %ebp, %eax\r
subl %ebx, %eax\r
addl %ecx, %eax\r
#\r
# Fixup callee's ebp point for PeiDispatch\r
#\r
- movl %ebp, %eax\r
- subl %ebx, %eax\r
- addl %ecx, %eax\r
- movl %eax, %ebp # From now, ebp is pointed to permenent memory\r
-\r
- pop %edx\r
- pop %ecx\r
- pop %ebx\r
- pop %eax\r
+# movl %ebp, %eax\r
+# subl %ebx, %eax\r
+# addl %ecx, %eax\r
+# movl %eax, %ebp # From now, ebp is pointed to permenent memory\r
+ popl %edx\r
+ popl %ecx\r
+ popl %ebx\r
+ popl %eax \r
ret
\ No newline at end of file
/** @file\r
\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
#include "SecFsp.h"\r
\r
-UINT32 FspImageSizeOffset = FSP_INFO_HEADER_OFF + OFFSET_IN_FSP_INFO_HEADER(ImageSize);\r
-\r
/**\r
\r
Calculate the FSP IDT gate descriptor.\r
It needs to be done as soon as possible after the stack is setup.\r
\r
@param[in,out] PeiFspData Pointer of the FSP global data.\r
- @param[in] BootFirmwareVolume Point to the address of BootFirmwareVolume in stack.\r
+ @param[in] BootloaderStack Bootloader stack.\r
+ @param[in] ApiIdx The index of the FSP API.\r
\r
**/\r
VOID\r
FspGlobalDataInit (\r
IN OUT FSP_GLOBAL_DATA *PeiFspData,\r
- IN VOID **BootFirmwareVolume\r
+ IN UINT32 BootloaderStack,\r
+ IN UINT8 ApiIdx\r
)\r
{\r
VOID *UpdDataRgnPtr;\r
ZeroMem ((VOID *)PeiFspData, sizeof(FSP_GLOBAL_DATA));\r
\r
PeiFspData->Signature = FSP_GLOBAL_DATA_SIGNATURE;\r
- PeiFspData->CoreStack = *(UINTN *)(BootFirmwareVolume + 2);\r
+ PeiFspData->CoreStack = BootloaderStack;\r
PeiFspData->PerfIdx = 2;\r
\r
SetFspMeasurePoint (FSP_PERF_ID_API_FSPINIT_ENTRY);\r
PeiFspData->FspInfoHeader = (FSP_INFO_HEADER *)(GetFspBaseAddress() + FSP_INFO_HEADER_OFF);\r
SecGetPlatformData (PeiFspData);\r
\r
+ //\r
+ // Set API calling mode\r
+ //\r
+ SetFspApiCallingMode (ApiIdx == 1 ? 0 : 1);\r
+\r
//\r
// Initialize UPD pointer.\r
//\r
}\r
ImageId[Idx] = 0;\r
\r
- DEBUG ((DEBUG_INFO | DEBUG_INIT, "\n============= PEIM FSP (%a 0x%08X) =============\n", \\r
- ImageId, PeiFspData->FspInfoHeader->ImageRevision));\r
+ DEBUG ((DEBUG_INFO | DEBUG_INIT, "\n============= PEIM FSP v1.%x (%a v%x.%x.%x.%x) =============\n", \\r
+ PeiFspData->FspInfoHeader->HeaderRevision - 1, \\r
+ ImageId, \\r
+ (PeiFspData->FspInfoHeader->ImageRevision >> 24) & 0xff, \\r
+ (PeiFspData->FspInfoHeader->ImageRevision >> 16) & 0xff, \\r
+ (PeiFspData->FspInfoHeader->ImageRevision >> 8) & 0xff, \\r
+ (PeiFspData->FspInfoHeader->ImageRevision >> 0) & 0xff));\r
\r
}\r
\r
Status = EFI_UNSUPPORTED;\r
}\r
}\r
+ } else if (ApiIdx == 3) {\r
+ //\r
+ // FspMemoryInit check\r
+ //\r
+ if ((UINT32)FspData != 0xFFFFFFFF) {\r
+ Status = EFI_UNSUPPORTED;\r
+ }\r
+ } else if (ApiIdx == 4) {\r
+ //\r
+ // TempRamExit check\r
+ //\r
+ if ((FspData == NULL) || ((UINT32)FspData == 0xFFFFFFFF)) {\r
+ Status = EFI_UNSUPPORTED;\r
+ } else {\r
+ if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {\r
+ Status = EFI_UNSUPPORTED;\r
+ }\r
+ }\r
+ } else if (ApiIdx == 5) {\r
+ //\r
+ // FspSiliconInit check\r
+ //\r
+ if ((FspData == NULL) || ((UINT32)FspData == 0xFFFFFFFF)) {\r
+ Status = EFI_UNSUPPORTED;\r
+ } else {\r
+ if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {\r
+ Status = EFI_UNSUPPORTED;\r
+ }\r
+ }\r
} else {\r
Status = EFI_UNSUPPORTED;\r
}\r
/** @file\r
\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
It needs to be done as soon as possible after the stack is setup.\r
\r
@param[in,out] PeiFspData Pointer of the FSP global data.\r
- @param[in] BootFirmwareVolume Point to the address of BootFirmwareVolume in stack.\r
+ @param[in] BootloaderStack Bootloader stack.\r
+ @param[in] ApiIdx The index of the FSP API.\r
\r
**/\r
VOID\r
FspGlobalDataInit (\r
IN OUT FSP_GLOBAL_DATA *PeiFspData,\r
- IN VOID **BootFirmwareVolume\r
+ IN UINT32 BootloaderStack,\r
+ IN UINT8 ApiIdx\r
);\r
\r
\r
/** @file\r
\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
@param[in] SizeOfRam Size of the temporary memory available for use.\r
@param[in] TempRamBase Base address of tempory ram\r
@param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.\r
- @param[in] PeiCoreEntry Pei Core entrypoint.\r
+ @param[in] PeiCore PeiCore entry point.\r
+ @param[in] BootloaderStack Bootloader stack.\r
+ @param[in] ApiIdx the index of API\r
\r
@return This function never returns.\r
\r
IN UINT32 SizeOfRam,\r
IN UINT32 TempRamBase,\r
IN VOID *BootFirmwareVolume,\r
- IN UINTN PeiCoreEntry\r
+ IN PEI_CORE_ENTRY PeiCore,\r
+ IN UINT32 BootloaderStack,\r
+ IN UINT32 ApiIdx\r
)\r
{\r
EFI_SEC_PEI_HAND_OFF SecCoreData;\r
SEC_IDT_TABLE IdtTableInStack;\r
UINT32 Index;\r
FSP_GLOBAL_DATA PeiFspData;\r
- PEI_CORE_ENTRY PeiCore;\r
UINT64 ExceptionHandler;\r
\r
//\r
//\r
// Iniitalize the global FSP data region\r
//\r
- FspGlobalDataInit (&PeiFspData, &BootFirmwareVolume);\r
+ FspGlobalDataInit (&PeiFspData, BootloaderStack, (UINT8)ApiIdx);\r
\r
//\r
// Update the base address and length of Pei temporary memory\r
\r
//\r
// Call PeiCore Entry\r
- //\r
- PeiCore = (PEI_CORE_ENTRY)(PeiCoreEntry);\r
+ // \r
PeiCore (&SecCoreData, mPeiSecPlatformInformationPpi);\r
\r
//\r
/** @file\r
\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
@param[in] SizeOfRam Size of the temporary memory available for use.\r
@param[in] TempRamBase Base address of tempory ram\r
@param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.\r
- @param[in] PeiCoreEntry Pei Core entrypoint.\r
+ @param[in] PeiCore PeiCore entry point.\r
+ @param[in] BootloaderStack Bootloader stack.\r
\r
@return This function never returns.\r
\r
IN UINT32 SizeOfRam,\r
IN UINT32 TempRamBase,\r
IN VOID *BootFirmwareVolume,\r
- IN UINTN PeiCoreEntry\r
+ IN PEI_CORE_ENTRY PeiCore,\r
+ IN UINT32 BootloaderStack,\r
+ IN UINT32 ApiIdx\r
);\r
\r
/**\r
Intel FSP API definition from Intel Firmware Support Package External\r
Architecture Specification, April 2014, revision 001.\r
\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#ifndef _FSP_API_H_\r
#define _FSP_API_H_\r
\r
-typedef UINT32 FSP_STATUS;\r
+#define FSP_STATUS EFI_STATUS\r
#define FSPAPI EFIAPI\r
\r
/**\r
typedef\r
VOID\r
(* CONTINUATION_PROC) (\r
- IN FSP_STATUS Status,\r
+ IN EFI_STATUS Status,\r
IN VOID *HobListPtr\r
);\r
\r
FSP_INIT_PHASE Phase;\r
} NOTIFY_PHASE_PARAMS;\r
\r
+typedef struct {\r
+ ///\r
+ /// Non-volatile storage buffer pointer.\r
+ ///\r
+ VOID *NvsBufferPtr;\r
+ ///\r
+ /// Runtime buffer pointer\r
+ ///\r
+ VOID *RtBufferPtr;\r
+ ///\r
+ /// Pointer to the HOB data structure defined in the PI specification\r
+ ///\r
+ VOID **HobListPtr;\r
+} FSP_MEMORY_INIT_PARAMS;\r
+\r
#pragma pack()\r
\r
/**\r
\r
@param[in] TempRaminitParamPtr Address pointer to the FSP_TEMP_RAM_INIT_PARAMS structure.\r
\r
- @retval FSP_SUCCESS Temp RAM was initialized successfully.\r
- @retval FSP_INVALID_PARAMETER Input parameters are invalid..\r
- @retval FSP_NOT_FOUND No valid microcode was found in the microcode region.\r
- @retval FSP_UNSUPPORTED The FSP calling conditions were not met.\r
- @retval FSP_DEVICE_ERROR Temp RAM initialization failed.\r
+ @retval EFI_SUCCESS Temp RAM was initialized successfully.\r
+ @retval EFI_INVALID_PARAMETER Input parameters are invalid..\r
+ @retval EFI_NOT_FOUND No valid microcode was found in the microcode region.\r
+ @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
+ @retval EFI_DEVICE_ERROR Temp RAM initialization failed.\r
\r
If this function is successful, the FSP initializes the ECX and EDX registers to point to\r
a temporary but writeable memory range available to the boot loader and returns with\r
to the end of this returned range so that it can be used as a standard stack.\r
**/\r
typedef\r
-FSP_STATUS\r
-(FSPAPI *FSP_TEMP_RAM_INIT) (\r
+EFI_STATUS\r
+(EFIAPI *FSP_TEMP_RAM_INIT) (\r
IN FSP_TEMP_RAM_INIT_PARAMS *FspTempRamInitPtr\r
);\r
\r
\r
@param[in] FspInitParamPtr Address pointer to the FSP_INIT_PARAMS structure.\r
\r
- @retval FSP_SUCCESS FSP execution environment was initialized successfully.\r
- @retval FSP_INVALID_PARAMETER Input parameters are invalid.\r
- @retval FSP_UNSUPPORTED The FSP calling conditions were not met.\r
- @retval FSP_DEVICE_ERROR FSP initialization failed.\r
+ @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r
+ @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
+ @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
+ @retval EFI_DEVICE_ERROR FSP initialization failed.\r
**/\r
typedef\r
-FSP_STATUS\r
-(FSPAPI *FSP_FSP_INIT) (\r
+EFI_STATUS\r
+(EFIAPI *FSP_INIT) (\r
IN OUT FSP_INIT_PARAMS *FspInitParamPtr\r
);\r
\r
+#define FSP_FSP_INIT FSP_INIT\r
+\r
/**\r
This FSP API is used to notify the FSP about the different phases in the boot process.\r
This allows the FSP to take appropriate actions as needed during different initialization\r
\r
@param[in] NotifyPhaseParamPtr Address pointer to the NOTIFY_PHASE_PRAMS\r
\r
- @retval FSP_SUCCESS The notification was handled successfully.\r
- @retval FSP_UNSUPPORTED The notification was not called in the proper order.\r
- @retval FSP_INVALID_PARAMETER The notification code is invalid.\r
+ @retval EFI_SUCCESS The notification was handled successfully.\r
+ @retval EFI_UNSUPPORTED The notification was not called in the proper order.\r
+ @retval EFI_INVALID_PARAMETER The notification code is invalid.\r
**/\r
typedef\r
-FSP_STATUS\r
-(FSPAPI *FSP_NOTIFY_PHASE) (\r
+EFI_STATUS\r
+(EFIAPI *FSP_NOTIFY_PHASE) (\r
IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr\r
);\r
\r
+/**\r
+ This FSP API is called after TempRamInit and initializes the memory.\r
+ This FSP API accepts a pointer to a data structure that will be platform dependent\r
+ and defined for each FSP binary. This will be documented in Integration guide with\r
+ each FSP release.\r
+ After FspMemInit completes its execution, it passes the pointer to the HobList and\r
+ returns to the boot loader from where it was called. Bootloader is responsible to \r
+ migrate it\92s stack and data to Memory.\r
+ FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to\r
+ complete the silicon initialization and provides bootloader an opportunity to get\r
+ control after system memory is available and before the temporary RAM is torn down.\r
+ These APIs are mutually exclusive to the FspInit API.\r
+\r
+ @param[in][out] FspMemoryInitParamPtr Address pointer to the FSP_MEMORY_INIT_PARAMS\r
+ structure.\r
+\r
+ @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r
+ @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
+ @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
+ @retval EFI_DEVICE_ERROR FSP initialization failed.\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *FSP_MEMORY_INIT) (\r
+ IN OUT FSP_MEMORY_INIT_PARAMS *FspMemoryInitParamPtr\r
+ );\r
+\r
+\r
+/**\r
+ This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary\r
+ memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure\r
+ that will be platform dependent and defined for each FSP binary. This will be\r
+ documented in Integration Guide.\r
+ FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to\r
+ complete the silicon initialization and provides bootloader an opportunity to get\r
+ control after system memory is available and before the temporary RAM is torn down.\r
+ These APIs are mutually exclusive to the FspInit API.\r
+\r
+ @param[in][out] TempRamExitParamPtr Pointer to the Temp Ram Exit parameters structure.\r
+ This structure is normally defined in the Integration Guide.\r
+ And if it is not defined in the Integration Guide, pass NULL.\r
+\r
+ @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r
+ @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
+ @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
+ @retval EFI_DEVICE_ERROR FSP initialization failed.\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *FSP_TEMP_RAM_EXIT) (\r
+ IN OUT VOID *TempRamExitParamPtr\r
+ );\r
+\r
+\r
+/**\r
+ This FSP API is called after TempRamExit API.\r
+ FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the\r
+ silicon initialization.\r
+ These APIs are mutually exclusive to the FspInit API.\r
+\r
+ @param[in][out] FspSiliconInitParamPtr Pointer to the Silicon Init parameters structure.\r
+ This structure is normally defined in the Integration Guide.\r
+ And if it is not defined in the Integration Guide, pass NULL.\r
+\r
+ @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r
+ @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
+ @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
+ @retval EFI_DEVICE_ERROR FSP initialization failed.\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *FSP_SILICON_INIT) (\r
+ IN OUT VOID *FspSiliconInitParamPtr\r
+ );\r
+\r
///\r
-/// FSP API Return Status Code\r
-///\r
-#define FSP_SUCCESS 0x00000000\r
-#define FSP_INVALID_PARAMETER 0x80000002\r
-#define FSP_UNSUPPORTED 0x80000003\r
-#define FSP_NOT_READY 0x80000006\r
-#define FSP_DEVICE_ERROR 0x80000007\r
-#define FSP_OUT_OF_RESOURCES 0x80000009\r
-#define FSP_VOLUME_CORRUPTED 0x8000000A\r
-#define FSP_NOT_FOUND 0x8000000E\r
-#define FSP_TIMEOUT 0x80000012\r
-#define FSP_ABORTED 0x80000015\r
-#define FSP_INCOMPATIBLE_VERSION 0x80000010\r
-#define FSP_SECURITY_VIOLATION 0x8000001A\r
-#define FSP_CRC_ERROR 0x8000001B\r
+/// FSP API Return Status Code for backward compatibility with v1.0\r
+///@{\r
+#define FSP_SUCCESS EFI_SUCCESS\r
+#define FSP_INVALID_PARAMETER EFI_INVALID_PARAMETER\r
+#define FSP_UNSUPPORTED EFI_UNSUPPORTED\r
+#define FSP_NOT_READY EFI_NOT_READY\r
+#define FSP_DEVICE_ERROR EFI_DEVICE_ERROR\r
+#define FSP_OUT_OF_RESOURCES EFI_OUT_OF_RESOURCES\r
+#define FSP_VOLUME_CORRUPTED EFI_VOLUME_CORRUPTED\r
+#define FSP_NOT_FOUND EFI_NOT_FOUND\r
+#define FSP_TIMEOUT EFI_TIMEOUT\r
+#define FSP_ABORTED EFI_ABORTED\r
+#define FSP_INCOMPATIBLE_VERSION EFI_INCOMPATIBLE_VERSION\r
+#define FSP_SECURITY_VIOLATION EFI_SECURITY_VIOLATION\r
+#define FSP_CRC_ERROR EFI_CRC_ERROR\r
+///@}\r
\r
#endif\r
Intel FSP Info Header definition from Intel Firmware Support Package External\r
Architecture Specification, April 2014, revision 001.\r
\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#ifndef _FSP_INFO_HEADER_H_\r
#define _FSP_INFO_HEADER_H_\r
\r
+#define FSP_HEADER_REVISION_1 1\r
+#define FSP_HEADER_REVISION_2 2\r
+\r
+#define FSPE_HEADER_REVISION_1 1\r
+#define FSPP_HEADER_REVISION_1 1\r
+\r
///\r
/// Fixed FSP header offset in the FSP image\r
///\r
\r
typedef struct {\r
///\r
- /// Signature ('FSPH') for the FSP Information Header\r
+ /// Byte 0x00: Signature ('FSPH') for the FSP Information Header\r
///\r
UINT32 Signature;\r
///\r
- /// Length of the FSP Information Header\r
+ /// Byte 0x04: Length of the FSP Information Header\r
///\r
UINT32 HeaderLength;\r
///\r
- /// Reserved\r
+ /// Byte 0x08: Reserved\r
///\r
UINT8 Reserved1[3];\r
///\r
- /// Revision of the FSP Information Header\r
+ /// Byte 0x0B: Revision of the FSP Information Header\r
///\r
UINT8 HeaderRevision;\r
///\r
- /// Revision of the FSP binary\r
+ /// Byte 0x0C: Revision of the FSP binary\r
///\r
UINT32 ImageRevision;\r
\r
\r
///\r
- /// Signature string that will help match the FSP Binary to a supported\r
+ /// Byte 0x10: Signature string that will help match the FSP Binary to a supported\r
/// hardware configuration.\r
///\r
CHAR8 ImageId[8];\r
///\r
- /// Size of the entire FSP binary\r
+ /// Byte 0x18: Size of the entire FSP binary\r
///\r
UINT32 ImageSize;\r
///\r
- /// FSP binary preferred base address\r
+ /// Byte 0x18: FSP binary preferred base address\r
///\r
UINT32 ImageBase;\r
\r
\r
///\r
- /// Attribute for the FSP binary\r
+ /// Byte 0x20: Attribute for the FSP binary\r
///\r
UINT32 ImageAttribute;\r
///\r
- /// Offset of the FSP configuration region\r
+ /// Byte 0x24: Offset of the FSP configuration region\r
///\r
UINT32 CfgRegionOffset;\r
///\r
- /// Size of the FSP configuration region\r
+ /// Byte 0x24: Size of the FSP configuration region\r
///\r
UINT32 CfgRegionSize;\r
///\r
- /// Number of API entries this FSP supports\r
+ /// Byte 0x2C: Number of API entries this FSP supports\r
///\r
UINT32 ApiEntryNum;\r
\r
\r
///\r
- /// TempRamInit API entry offset\r
+ /// Byte 0x30: The offset for the API to setup a temporary stack till the memory\r
+ /// is initialized.\r
///\r
UINT32 TempRamInitEntryOffset;\r
///\r
- /// FspInit API entry offset\r
+ /// Byte 0x34: The offset for the API to initialize the CPU and the chipset (SOC)\r
///\r
UINT32 FspInitEntryOffset;\r
///\r
- /// NotifyPhase API entry offset\r
+ /// Byte 0x38: The offset for the API to inform the FSP about the different stages\r
+ /// in the boot process\r
///\r
UINT32 NotifyPhaseEntryOffset;\r
+\r
///\r
- /// Reserved\r
+ /// Below field is added in FSP 1.1\r
///\r
- UINT32 Reserved2;\r
+\r
+ ///\r
+ /// Byte 0x3C: The offset for the API to initialize the memory\r
+ ///\r
+ UINT32 FspMemoryInitEntryOffset;\r
+ ///\r
+ /// Byte 0x40: The offset for the API to tear down temporary RAM\r
+ ///\r
+ UINT32 TempRamExitEntryOffset;\r
+ ///\r
+ /// Byte 0x44: The offset for the API to initialize the CPU and chipset\r
+ ///\r
+ UINT32 FspSiliconInitEntryOffset;\r
\r
} FSP_INFO_HEADER;\r
\r
+///\r
+/// Below structure is added in FSP 1.1\r
+///\r
+typedef struct {\r
+ ///\r
+ /// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header\r
+ ///\r
+ UINT32 Signature;\r
+ ///\r
+ /// Byte 0x04: Length of the FSP Extended Header\r
+ ///\r
+ UINT32 HeaderLength;\r
+ ///\r
+ /// Byte 0x08: Revision of the FSP Extended Header\r
+ ///\r
+ UINT8 Revision;\r
+ ///\r
+ /// Byte 0x09: Reserved for future use.\r
+ ///\r
+ UINT8 Reserved;\r
+ ///\r
+ /// Byte 0x0A: An OEM-supplied string that defines the OEM\r
+ ///\r
+ CHAR8 OemId[6];\r
+ ///\r
+ /// Byte 0x10: An OEM-supplied revision number. Larger numbers are assumed to be newer revisions.\r
+ ///\r
+ UINT32 OemRevision;\r
+\r
+} FSP_EXTENTED_HEADER;\r
+\r
#pragma pack()\r
\r
#endif\r
Intel FSP Hob Guid definition from Intel Firmware Support Package External\r
Architecture Specification, April 2014, revision 001.\r
\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#ifndef __GUID_HOB_FSP_EAS_GUID__\r
#define __GUID_HOB_FSP_EAS_GUID__\r
\r
-extern EFI_GUID gFspBootLoaderTemporaryMemoryGuid;\r
+extern EFI_GUID gFspBootLoaderTempMemoryGuid;\r
+extern EFI_GUID gFspBootLoaderTemporaryMemoryGuid; // Same as gFspBootLoaderTempMemoryGuid\r
+\r
extern EFI_GUID gFspReservedMemoryResourceHobGuid;\r
extern EFI_GUID gFspNonVolatileStorageHobGuid;\r
\r
/** @file\r
\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
IN UINT8 Id\r
);\r
\r
+/**\r
+ This function gets the FSP info header pointer.\r
+\r
+ @retval FspInfoHeader FSP info header pointer\r
+**/\r
+FSP_INFO_HEADER *\r
+EFIAPI\r
+GetFspInfoHeader (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ This function gets FSP API calling mode\r
+\r
+ @retval API calling mode\r
+**/\r
+UINT8\r
+EFIAPI\r
+GetFspApiCallingMode (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ This function sets FSP API calling mode\r
+\r
+ @param[in] Mode API calling mode\r
+**/\r
+VOID\r
+EFIAPI\r
+SetFspApiCallingMode (\r
+ UINT8 Mode\r
+ );\r
+\r
#endif\r
/** @file\r
\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
VOID\r
);\r
\r
+/**\r
+ Set a new stack frame for the continuation function\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FspSetNewStackFrame (\r
+ VOID\r
+ );\r
+\r
/**\r
This function transfer control to the ContinuationFunc passed in by the\r
bootloader.\r
+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#ifndef _FSP_RETURN_LIB_H_\r
-#define _FSP_RETURN_LIB_H_\r
-\r
-/**\r
- Return the control from FSP to the Caller.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-AsmFspReturn (\r
- VOID\r
- );\r
-\r
-#endif\r
/** @file\r
\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
FSP_PLAT_DATA PlatformData;\r
FSP_INFO_HEADER *FspInfoHeader;\r
VOID *UpdDataRgnPtr;\r
+ UINT8 ApiMode;\r
+ UINT8 Reserved[3];\r
UINT32 PerfIdx;\r
UINT64 PerfData[32];\r
// UINT64 PerfData[FixedPcdGet32(PcdFspMaxPerfEntry)];\r
/** @file\r
\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
UINT8 Reserved;\r
UINT32 PatchEntryNum;\r
UINT32 PatchData[FixedPcdGet32(PcdFspMaxPatchEntry)];\r
+ UINT32 VpdBase;\r
} FSP_PATCH_TABLE;\r
\r
#pragma pack()\r
[Includes]\r
Include\r
Include/Private\r
+ \r
+[LibraryClasses]\r
+ ## @libraryclass Provides cache-as-ram support.\r
+ CacheAsRamLib|IntelFspPkg/Include/Library/CacheAsRamLib.h\r
+\r
+ ## @libraryclass Provides cache setting on MTRR.\r
+ CacheLib|IntelFspPkg/Include/Library/CacheLib.h\r
+\r
+ ## @libraryclass Provides debug device abstraction.\r
+ DebugDeviceLib|IntelFspPkg/Include/Library/DebugDeviceLib.h\r
+\r
+ ## @libraryclass Provides FSP related services.\r
+ FspCommonLib|IntelFspPkg/Include/Library/FspCommonLib.h\r
+\r
+ ## @libraryclass Provides FSP platform related actions.\r
+ FspPlatformLib|IntelFspPkg/Include/Library/FspPlatformLib.h\r
+\r
+ ## @libraryclass Provides FSP switch stack function.\r
+ FspSwitchStackLib|IntelFspPkg/Include/Library/FspSwitchStackLib.h\r
\r
[Guids]\r
#\r
\r
# Guid define in FSP EAS\r
gFspHeaderFileGuid = { 0x912740BE, 0x2284, 0x4734, { 0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C } }\r
+ gFspBootLoaderTempMemoryGuid = { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } }\r
gFspBootLoaderTemporaryMemoryGuid = { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } }\r
gFspReservedMemoryResourceHobGuid = { 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } }\r
gFspNonVolatileStorageHobGuid = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }\r
/** @file\r
\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
return FspData->PerfData[(FspData->PerfIdx)++];\r
}\r
+\r
+/**\r
+ This function gets the FSP info header pointer.\r
+\r
+ @retval FspInfoHeader FSP info header pointer\r
+**/\r
+FSP_INFO_HEADER *\r
+EFIAPI\r
+GetFspInfoHeader (\r
+ VOID\r
+ )\r
+{\r
+ return GetFspGlobalDataPointer()->FspInfoHeader;\r
+}\r
+\r
+/**\r
+ This function gets FSP API calling mode\r
+\r
+ @retval API calling mode\r
+**/\r
+UINT8\r
+EFIAPI\r
+GetFspApiCallingMode (\r
+ VOID\r
+ )\r
+{\r
+ return GetFspGlobalDataPointer()->ApiMode;\r
+}\r
+\r
+/**\r
+ This function sets FSP API calling mode\r
+\r
+ @param[in] Mode API calling mode\r
+**/\r
+VOID\r
+EFIAPI\r
+SetFspApiCallingMode (\r
+ UINT8 Mode\r
+ )\r
+{\r
+ FSP_GLOBAL_DATA *FspData;\r
+\r
+ FspData = GetFspGlobalDataPointer ();\r
+ FspData->ApiMode = Mode;\r
+}\r
+\r
\r
[LibraryClasses]\r
BaseMemoryLib\r
+ MemoryAllocationLib\r
\r
[Pcd]\r
gIntelFspPkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES\r
gIntelFspPkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES\r
\r
[Guids]\r
- gFspBootLoaderTemporaryMemoryGuid ## PRODUCES ## HOB\r
+ gFspBootLoaderTempMemoryGuid ## PRODUCES ## HOB\r
\r
[FixedPcd]\r
gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry ## CONSUMES\r
/** @file\r
\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#include <PiPei.h>\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/HobLib.h>\r
VOID\r
)\r
{\r
- FSP_INIT_RT_COMMON_BUFFER *FspInitRtBuffer;\r
- UINT32 BootLoaderTempRamStart;\r
- UINT32 BootLoaderTempRamEnd;\r
- UINT32 BootLoaderTempRamSize;\r
- UINT32 OffsetGap;\r
- UINT32 FspParamPtr;\r
- FSP_INIT_PARAMS *FspInitParams;\r
- UINT32 *NewStackTop;\r
- VOID *BootLoaderTempRamHob;\r
- VOID *UpdDataRgnPtr;\r
- VOID *PlatformDataPtr;\r
+ FSP_INIT_RT_COMMON_BUFFER *FspInitRtBuffer;\r
+ UINT32 BootLoaderTempRamStart;\r
+ UINT32 BootLoaderTempRamEnd;\r
+ UINT32 BootLoaderTempRamSize;\r
+ UINT32 OffsetGap;\r
+ UINT32 FspParamPtr;\r
+ FSP_INIT_PARAMS *FspInitParams;\r
+ UINT32 *NewStackTop;\r
+ VOID *BootLoaderTempRamHob;\r
+ VOID *UpdDataRgnPtr;\r
+ VOID *PlatformDataPtr;\r
+ UINT8 ApiMode;\r
+ \r
+ ApiMode = GetFspApiCallingMode ();\r
\r
//\r
// Get the temporary memory range used by the bootloader\r
//\r
// Build a Boot Loader Temporary Memory GUID HOB\r
//\r
- BootLoaderTempRamHob = BuildGuidHob (&gFspBootLoaderTemporaryMemoryGuid, BootLoaderTempRamSize);\r
+ if (ApiMode == 0) {\r
+ BootLoaderTempRamHob = BuildGuidHob (&gFspBootLoaderTempMemoryGuid, BootLoaderTempRamSize);\r
+ } else {\r
+ BootLoaderTempRamHob = (VOID *)AllocatePool (BootLoaderTempRamSize);\r
+ }\r
+\r
CopyMem (BootLoaderTempRamHob, (VOID *)BootLoaderTempRamStart, BootLoaderTempRamSize);\r
OffsetGap = (UINT32)BootLoaderTempRamHob - BootLoaderTempRamStart;\r
\r
//\r
// Set a new stack frame for the continuation function\r
//\r
- FspInitParams = (FSP_INIT_PARAMS *)GetFspApiParameter ();\r
- FspInitRtBuffer = (FSP_INIT_RT_COMMON_BUFFER *)FspInitParams->RtBufferPtr;\r
- NewStackTop = (UINT32 *)FspInitRtBuffer->StackTop - 1;\r
- SetFspCoreStackPointer (NewStackTop);\r
+ if (ApiMode == 0) {\r
+ FspInitParams = (FSP_INIT_PARAMS *)GetFspApiParameter ();\r
+ FspInitRtBuffer = (FSP_INIT_RT_COMMON_BUFFER *)FspInitParams->RtBufferPtr;\r
+ NewStackTop = (UINT32 *)FspInitRtBuffer->StackTop - 1;\r
+ SetFspCoreStackPointer (NewStackTop);\r
+ }\r
\r
//\r
// Fix the FspInit Parameter Pointers to the new location.\r
((UINT32)PlatformDataPtr < BootLoaderTempRamEnd)) {\r
SetFspPlatformDataPointer ((UINT8 *)PlatformDataPtr + OffsetGap);\r
}\r
-\r
}\r
/** @file\r
\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
VOID\r
)\r
{\r
- FSP_INIT_PARAMS *FspInitParams;\r
-\r
- FspInitParams = (FSP_INIT_PARAMS *)GetFspApiParameter ();\r
-\r
- //\r
- // Modify the parameters for ContinuationFunc\r
- //\r
- SetFspContinuationFuncParameter(EFI_SUCCESS, 0);\r
- SetFspContinuationFuncParameter((UINT32)GetHobList(), 1);\r
+ FSP_INIT_PARAMS *FspInitParams;\r
+\r
+ if (GetFspApiCallingMode() == 0) {\r
+ //\r
+ // FspInit API is used, so jump into the ContinuationFunc\r
+ //\r
+ FspInitParams = (FSP_INIT_PARAMS *)GetFspApiParameter ();\r
+ \r
+ //\r
+ // Modify the parameters for ContinuationFunc\r
+ //\r
+ SetFspContinuationFuncParameter(EFI_SUCCESS, 0);\r
+ SetFspContinuationFuncParameter((UINT32)GetHobList(), 1);\r
+ \r
+ //\r
+ // Modify the return address to ContinuationFunc\r
+ //\r
+ SetFspApiReturnAddress((UINT32)FspInitParams->ContinuationFunc);\r
+ \r
+ //\r
+ // Give control back to the boot loader framework caller after FspInit is done\r
+ // It is done throught the continuation function\r
+ //\r
+ SetFspMeasurePoint (FSP_PERF_ID_API_FSPINIT_EXIT);\r
+ } else {\r
+ //\r
+ // FspMemoryInit API is used, so return directly\r
+ //\r
\r
- //\r
- // Modify the return address to ContinuationFunc\r
- //\r
- SetFspApiReturnAddress((UINT32)FspInitParams->ContinuationFunc);\r
+ //\r
+ // This is the end of the FspSiliconInit API\r
+ // Give control back to the boot loader\r
+ //\r
+ DEBUG ((DEBUG_INFO | DEBUG_INIT, "FspSiliconInitApi() - End\n"));\r
+ SetFspApiReturnStatus (EFI_SUCCESS);\r
+ }\r
\r
- //\r
- // Give control back to the boot loader framework caller after FspInit is done\r
- // It is done throught the continuation function\r
- //\r
- SetFspMeasurePoint (FSP_PERF_ID_API_FSPINIT_EXIT);\r
Pei2LoaderSwitchStack();\r
}\r
\r
//\r
// Notify code does not follow the predefined order\r
//\r
+ DEBUG ((DEBUG_INFO, "Unsupported FSP Notification Value\n"));\r
SetFspApiReturnStatus(EFI_UNSUPPORTED);\r
} else {\r
//\r
// Process Notification and Give control back to the boot loader framework caller\r
//\r
Status = FspNotificationHandler (NotificationValue);\r
+ DEBUG ((DEBUG_INFO, "FSP Notification Handler Returns : 0x%08X\n", Status));\r
SetFspApiReturnStatus(Status);\r
if (!EFI_ERROR(Status)) {\r
NotificationCount++;\r
#------------------------------------------------------------------------------\r
#\r
-# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
#\r
#------------------------------------------------------------------------------\r
\r
-ASM_GLOBAL ASM_PFX(Pei2LoaderSwitchStack)\r
-ASM_GLOBAL ASM_PFX(Loader2PeiSwitchStack)\r
\r
#------------------------------------------------------------------------------\r
# UINT32\r
#------------------------------------------------------------------------------\r
ASM_GLOBAL ASM_PFX(Loader2PeiSwitchStack)\r
ASM_PFX(Loader2PeiSwitchStack):\r
-#Save current contexts\r
+ #\r
+ #Save current contexts\r
+ #\r
push $exit\r
pushf\r
- pushf\r
cli\r
pusha\r
- push $0x0\r
- push $0x0\r
+ sub $0x08, %esp\r
sidt (%esp)\r
\r
+ #\r
# Load new stack\r
+ #\r
push %esp\r
call ASM_PFX(SwapStack)\r
- mov %eax,%esp\r
+ movl %eax, %esp\r
\r
+ #\r
# Restore previous contexts\r
+ #\r
lidt (%esp)\r
- add $8,%esp\r
+ add $0x08,%esp\r
popa\r
popf\r
- popf\r
exit:\r
ret\r
\r
## @ GenCfgOpt.py\r
#\r
-# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials are licensed and made available under\r
# the terms and conditions of the BSD License that accompanies this distribution.\r
# The full text of the license may be found at\r
ElifStack[-1] = ElifStack[-1] + 1\r
else:\r
if len(DscLine) > 0 and DscLine[0] == '!':\r
- self.Error = "Invalid DscLine '%s'" % DscLine\r
- Error = 3\r
- break;\r
+ #\r
+ # Current it can only handle build switch.\r
+ # It does not support INF file in included dsc.\r
+ #\r
else:\r
if reduce(lambda x,y: x and y, IfStack):\r
Handle = True\r
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