ARM: Remove NSACR from the common code

NSACR (Non-Secure Access Control Register) is AArch32 specific.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14522 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index 3326e7b584b59db3fced3f2984872bc0266d8f50..39f264251bb13038a09705cd498ecaab1b7d680e 100644 (file)
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -128,15 +128,7 @@
   # - BIT9 : SIF - Secure Instruction Fetch\r
   # 0x31 = NS | EA | FW\r
   gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r
-  \r
-  # Non Secure Access Control Register\r
-  # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
-  # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31 \r
-  # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r
-  # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r
-  # 0xC00 = cp10 | cp11\r
-  gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r
-  \r
+\r
   # System Memory (DRAM): These PCDs define the region of in-built system memory\r
   # Some platforms can get DRAM extensions, these additional regions will be declared\r
   # to UEFI by ArmPLatformPlib   \r
@@ -182,6 +174,14 @@
   # The FDT blob must be loaded at a 64bit aligned address.\r
   gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026\r
 \r
+  # Non Secure Access Control Register\r
+  # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
+  # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r
+  # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r
+  # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r
+  # 0xC00 = cp10 | cp11\r
+  gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r
+\r
 [PcdsFixedAtBuild.AARCH64]\r
   # By default we do transition to EL2 non-secure mode with Stack for EL2.\r
   #        Mode Description              Bits\r

diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h
index 7f1f44ccc3ea970c0207eceb225125819d3aae85..8b64786004324ae3e15054ead352b3933539e7fd 100644 (file)
--- a/ArmPkg/Include/Chipset/AArch64.h
+++ b/ArmPkg/Include/Chipset/AArch64.h
@@ -34,15 +34,6 @@
 // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions\r
 #define AARCH64_PFR0_FP         (0xF << 16)\r
 \r
-// NSACR - Non-Secure Access Control Register definitions\r
-#define NSACR_CP(cp)            ((1 << (cp)) & 0x3FFF)\r
-#define NSACR_NSD32DIS          (1 << 14)\r
-#define NSACR_NSASEDIS          (1 << 15)\r
-#define NSACR_PLE               (1 << 16)\r
-#define NSACR_TL                (1 << 17)\r
-#define NSACR_NS_SMP            (1 << 18)\r
-#define NSACR_RFR               (1 << 19)\r
-\r
 // SCR - Secure Configuration Register definitions\r
 #define SCR_NS                  (1 << 0)\r
 #define SCR_IRQ                 (1 << 1)\r
@@ -176,4 +167,9 @@ GcdAttributeToPageAttribute (
   IN UINT64 GcdAttributes\r
   );\r
 \r
+UINTN\r
+ArmWriteCptr (\r
+  IN  UINT64 Cptr\r
+  );\r
+\r
 #endif // __AARCH64_H__\r

diff --git a/ArmPkg/Include/Chipset/ArmV7.h b/ArmPkg/Include/Chipset/ArmV7.h
index 479e8d05e11395f4ba57272d82ff3ac4a6b33763..29922eca19fcc7e9b28e3c23c50cfa1cff1c9129 100644 (file)
--- a/ArmPkg/Include/Chipset/ArmV7.h
+++ b/ArmPkg/Include/Chipset/ArmV7.h
@@ -112,5 +112,17 @@ EFIAPI
 ArmReadIdPfr1 (\r
   VOID\r
   );\r
-  \r
+\r
+UINT32\r
+EFIAPI\r
+ArmReadNsacr (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteNsacr (\r
+  IN  UINT32   Nsacr\r
+  );\r
+\r
 #endif // __ARM_V7_H__\r

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 1f1fd9e515b0067bfe87b0ef8d4919757728cbe7..bd1bbc40b406d7ae41254b432ad57154fb07f808 100644 (file)
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -535,18 +535,6 @@ ArmEnableVFP (
   VOID\r
   );\r
 \r
-UINT32\r
-EFIAPI\r
-ArmReadNsacr (\r
-  VOID\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteNsacr (\r
-  IN  UINT32   SetWayFormat\r
-  );\r
-\r
 UINT32\r
 EFIAPI\r
 ArmReadScr (\r

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S
index 9595f224c5511a1939362cf58056373e810bdae9..5ee8b25675461f8ed7f21952a7b2c56350ab7c72 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S
@@ -1,7 +1,7 @@
 #------------------------------------------------------------------------------ \r
 #\r
 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
 #\r
 # This program and the accompanying materials\r
 # are licensed and made available under the terms and conditions of the BSD License\r
@@ -29,6 +29,8 @@ GCC_ASM_EXPORT(ArmEnableInterrupts)
 GCC_ASM_EXPORT(ArmDisableInterrupts)\r
 GCC_ASM_EXPORT(ReadCCSIDR)\r
 GCC_ASM_EXPORT(ReadCLIDR)\r
+GCC_ASM_EXPORT(ArmReadNsacr)\r
+GCC_ASM_EXPORT(ArmWriteNsacr)\r
 \r
 #------------------------------------------------------------------------------\r
 \r
@@ -98,4 +100,12 @@ ASM_PFX(ReadCLIDR):
   mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register\r
   bx  lr\r
 \r
+ASM_PFX(ArmReadNsacr):\r
+  mrc     p15, 0, r0, c1, c1, 2\r
+  bx      lr\r
+\r
+ASM_PFX(ArmWriteNsacr):\r
+  mcr     p15, 0, r0, c1, c1, 2\r
+  bx      lr\r
+\r
 ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm
index a5ff6b26108e5715cdb808206aa06a4fb2b6427b..6af662bda530dcef915b6b618914b4b82491cf45 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm
@@ -1,7 +1,7 @@
 //------------------------------------------------------------------------------ \r
 //\r
 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
 //\r
 // This program and the accompanying materials\r
 // are licensed and made available under the terms and conditions of the BSD License\r
@@ -25,7 +25,9 @@
     EXPORT  ArmDisableInterrupts\r
     EXPORT  ReadCCSIDR\r
     EXPORT  ReadCLIDR\r
-    \r
+    EXPORT  ArmReadNsacr\r
+    EXPORT  ArmWriteNsacr\r
+\r
     AREA ArmLibSupportV7, CODE, READONLY\r
 \r
 \r
@@ -96,5 +98,13 @@ ReadCCSIDR
 ReadCLIDR\r
   mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register\r
   bx  lr\r
-  \r
+\r
+ArmReadNsacr\r
+  mrc     p15, 0, r0, c1, c1, 2\r
+  bx      lr\r
+\r
+ArmWriteNsacr\r
+  mcr     p15, 0, r0, c1, c1, 2\r
+  bx      lr\r
+\r
   END\r

diff --git a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
index 2db812616a35c4f807af7af6b3015088cdcb2c0c..cf2ec76be92dd86fa0c4646bfc2495dfccb6561e 100644 (file)
--- a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
@@ -32,7 +32,7 @@ GCC_ASM_EXPORT (ArmWriteAuxCr)
 GCC_ASM_EXPORT (ArmReadAuxCr)\r
 GCC_ASM_EXPORT (ArmInvalidateTlb)\r
 GCC_ASM_EXPORT (ArmUpdateTranslationTableEntry)\r
-GCC_ASM_EXPORT (ArmWriteNsacr)\r
+GCC_ASM_EXPORT (ArmWriteCptr)\r
 GCC_ASM_EXPORT (ArmWriteScr)\r
 GCC_ASM_EXPORT (ArmWriteMVBar)\r
 GCC_ASM_EXPORT (ArmCallWFE)\r
@@ -176,9 +176,9 @@ ASM_PFX(ArmInvalidateTlb):
    isb\r
    ret\r
 \r
-ASM_PFX(ArmWriteNsacr):\r
+ASM_PFX(ArmWriteCptr):\r
   msr     cptr_el3, x0           // EL3 Coprocessor Trap Reg (CPTR)\r
-  ret                            // Non-Secure Access Control Reg (NSACR) in ARMv7\r
+  ret\r
 \r
 ASM_PFX(ArmWriteScr):\r
   msr     scr_el3, x0            // Secure configuration register EL3\r

diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
index 71aee430739e62615ceab805a9cf210a93b2c138..4c95565e8f085c004609e88e31256855aa5a5f31 100644 (file)
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
@@ -38,8 +38,6 @@ GCC_ASM_EXPORT(ArmWriteAuxCr)
 GCC_ASM_EXPORT(ArmReadAuxCr)\r
 GCC_ASM_EXPORT(ArmInvalidateTlb)\r
 GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)\r
-GCC_ASM_EXPORT(ArmReadNsacr)\r
-GCC_ASM_EXPORT(ArmWriteNsacr)\r
 GCC_ASM_EXPORT(ArmReadScr)\r
 GCC_ASM_EXPORT(ArmWriteScr)\r
 GCC_ASM_EXPORT(ArmReadMVBar)\r
@@ -147,14 +145,6 @@ ASM_PFX(ArmInvalidateTlb):
   isb\r
   bx      lr\r
 \r
-ASM_PFX(ArmReadNsacr):\r
-  mrc     p15, 0, r0, c1, c1, 2\r
-  bx      lr\r
-\r
-ASM_PFX(ArmWriteNsacr):\r
-  mcr     p15, 0, r0, c1, c1, 2\r
-  bx      lr\r
-\r
 ASM_PFX(ArmReadScr):\r
   mrc     p15, 0, r0, c1, c1, 0\r
   bx      lr\r

diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
index 1636010e0f0cbf71344317a66cb64bffa0da53ae..f4b22943ff2c5012c988e959447d6f3e6fc811cf 100644 (file)
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
@@ -38,8 +38,6 @@
     EXPORT ArmReadAuxCr\r
     EXPORT ArmInvalidateTlb\r
     EXPORT ArmUpdateTranslationTableEntry\r
-    EXPORT ArmReadNsacr\r
-    EXPORT ArmWriteNsacr\r
     EXPORT ArmReadScr\r
     EXPORT ArmWriteScr\r
     EXPORT ArmReadMVBar\r
@@ -147,14 +145,6 @@ ArmInvalidateTlb
   isb\r
   bx      lr\r
 \r
-ArmReadNsacr\r
-  mrc     p15, 0, r0, c1, c1, 2\r
-  bx      lr\r
-\r
-ArmWriteNsacr\r
-  mcr     p15, 0, r0, c1, c1, 2\r
-  bx      lr\r
-\r
 ArmReadScr\r
   mrc     p15, 0, r0, c1, c1, 0\r
   bx      lr\r

diff --git a/ArmPlatformPkg/Sec/AArch64/Arch.c b/ArmPlatformPkg/Sec/AArch64/Arch.c
new file mode 100644 (file)
index 0000000..6e7d58e
--- /dev/null
+++ b/ArmPlatformPkg/Sec/AArch64/Arch.c
@@ -0,0 +1,25 @@
+/** @file\r
+*\r
+*  Copyright (c) 2013, ARM Limited. All rights reserved.\r
+*\r
+*  This program and the accompanying materials\r
+*  are licensed and made available under the terms and conditions of the BSD License\r
+*  which accompanies this distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Chipset/AArch64.h>\r
+\r
+VOID\r
+EFIAPI\r
+ArmSecArchTrustzoneInit (\r
+  VOID\r
+  )\r
+{\r
+  // Do not trap any access to Floating Point and Advanced SIMD in EL3.\r
+  ArmWriteCptr (0);\r
+}\r

diff --git a/ArmPlatformPkg/Sec/Arm/Arch.c b/ArmPlatformPkg/Sec/Arm/Arch.c
new file mode 100644 (file)
index 0000000..85df081
--- /dev/null
+++ b/ArmPlatformPkg/Sec/Arm/Arch.c
@@ -0,0 +1,25 @@
+/** @file\r
+*\r
+*  Copyright (c) 2013, ARM Limited. All rights reserved.\r
+*\r
+*  This program and the accompanying materials\r
+*  are licensed and made available under the terms and conditions of the BSD License\r
+*  which accompanies this distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Chipset/ArmV7.h>\r
+\r
+VOID\r
+EFIAPI\r
+ArmSecArchTrustzoneInit (\r
+  VOID\r
+  )\r
+{\r
+  // Write to CP15 Non-secure Access Control Register\r
+  ArmWriteNsacr (PcdGet32 (PcdArmNsacr));\r
+}\r

diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c
index 5282d68ec7d7daf05e60ddb52114aa06a1e98636..088a9247b46f7daf4e9eebf3fdda2de1d02cdf10 100644 (file)
--- a/ArmPlatformPkg/Sec/Sec.c
+++ b/ArmPlatformPkg/Sec/Sec.c
@@ -165,8 +165,8 @@ TrustedWorldInitialization (
   JumpAddress = PcdGet32 (PcdFvBaseAddress);\r
   ArmPlatformSecExtraAction (MpId, &JumpAddress);\r
 \r
-  // Write to CP15 Non-secure Access Control Register\r
-  ArmWriteNsacr (PcdGet32 (PcdArmNsacr));\r
+  // Initialize architecture specific security policy\r
+  ArmSecArchTrustzoneInit ();\r
 \r
   // CP15 Secure Configuration Register\r
   ArmWriteScr (PcdGet32 (PcdArmScr));\r

diff --git a/ArmPlatformPkg/Sec/Sec.inf b/ArmPlatformPkg/Sec/Sec.inf
index dc1c4f2bee4557d3aaf7f757bd3d0a0561c0a83e..3e9a246d737f96e73d0d2bbb1d47e3a3956b3480 100644 (file)
--- a/ArmPlatformPkg/Sec/Sec.inf
+++ b/ArmPlatformPkg/Sec/Sec.inf
@@ -24,12 +24,14 @@
   Sec.c\r
 \r
 [Sources.ARM]\r
+  Arm/Arch.c\r
   Arm/Helper.asm           | RVCT\r
   Arm/Helper.S             | GCC\r
   Arm/SecEntryPoint.S      | GCC\r
   Arm/SecEntryPoint.asm    | RVCT\r
   \r
 [Sources.AARCH64]\r
+  AArch64/Arch.c\r
   AArch64/Helper.S        | GCC\r
   AArch64/SecEntryPoint.S | GCC\r
 \r
@@ -56,14 +58,13 @@
 [FeaturePcd]\r
   gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec\r
   \r
-[FixedPcd]\r
+[FixedPcd.common]\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString\r
 \r
   gArmTokenSpaceGuid.PcdTrustzoneSupport\r
   gArmTokenSpaceGuid.PcdVFPEnabled\r
   \r
   gArmTokenSpaceGuid.PcdArmScr\r
-  gArmTokenSpaceGuid.PcdArmNsacr\r
   gArmTokenSpaceGuid.PcdArmNonSecModeTransition\r
   \r
   gArmTokenSpaceGuid.PcdSecureFvBaseAddress\r
@@ -81,3 +82,6 @@
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
   \r
   gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize  \r
+\r
+[FixedPcd.ARM]\r
+  gArmTokenSpaceGuid.PcdArmNsacr\r

diff --git a/ArmPlatformPkg/Sec/SecInternal.h b/ArmPlatformPkg/Sec/SecInternal.h
index 255059af5fa171b1288855d8fa05c33842a814a3..111123725b482985fe5ba2987573a4528addb7dc 100644 (file)
--- a/ArmPlatformPkg/Sec/SecInternal.h
+++ b/ArmPlatformPkg/Sec/SecInternal.h
@@ -74,4 +74,10 @@ SecCommonExceptionEntry (
   IN UINTN  LR\r
   );\r
 \r
+VOID\r
+EFIAPI\r
+ArmSecArchTrustzoneInit (\r
+  VOID\r
+  );\r
+\r
 #endif\r