ArmPkg/ArmGic: Added GicV3 support to ArmGicLib

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16233 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
index 7d99f9f98ab018d1c9fe4dc1e4125395893c3ce7..1e5924f5a49f0d396d40c76a2d8a5eec18cc120e 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
@@ -18,6 +18,7 @@
 #include <Library/IoLib.h>\r
 \r
 #include "GicV2/ArmGicV2Lib.h"\r
+#include "GicV3/ArmGicV3Lib.h"\r
 \r
 UINTN\r
 EFIAPI\r
@@ -82,6 +83,8 @@ ArmGicAcknowledgeInterrupt (
     if (InterruptId != NULL) {\r
       *InterruptId = Value & ARM_GIC_ICCIAR_ACKINTID;\r
     }\r
+  } else if (Revision == ARM_GIC_ARCH_REVISION_3) {\r
+    Value = ArmGicV3AcknowledgeInterrupt ();\r
   } else {\r
     ASSERT_EFI_ERROR (EFI_UNSUPPORTED);\r
     // Report Spurious interrupt which is what the above controllers would\r
@@ -104,6 +107,8 @@ ArmGicEndOfInterrupt (
   Revision = ArmGicGetSupportedArchRevision ();\r
   if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
     ArmGicV2EndOfInterrupt (GicInterruptInterfaceBase, Source);\r
+  } else if (Revision == ARM_GIC_ARCH_REVISION_3) {\r
+    ArmGicV3EndOfInterrupt (Source);\r
   } else {\r
     ASSERT_EFI_ERROR (EFI_UNSUPPORTED);\r
   }\r
@@ -183,6 +188,8 @@ ArmGicEnableInterruptInterface (
   Revision = ArmGicGetSupportedArchRevision ();\r
   if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
     ArmGicV2EnableInterruptInterface (GicInterruptInterfaceBase);\r
+  } else if (Revision == ARM_GIC_ARCH_REVISION_3) {\r
+    ArmGicV3EnableInterruptInterface ();\r
   } else {\r
     ASSERT_EFI_ERROR (EFI_UNSUPPORTED);\r
   }\r
@@ -199,6 +206,8 @@ ArmGicDisableInterruptInterface (
   Revision = ArmGicGetSupportedArchRevision ();\r
   if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
     ArmGicV2DisableInterruptInterface (GicInterruptInterfaceBase);\r
+  } else if (Revision == ARM_GIC_ARCH_REVISION_3) {\r
+    ArmGicV3DisableInterruptInterface ();\r
   } else {\r
     ASSERT_EFI_ERROR (EFI_UNSUPPORTED);\r
   }\r

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
index ca5cd1942b0885cbe88ef0aaa06a7020cb7258f5..81282b9b82990139628ffd42cab7ba0ce7c57f02 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
@@ -28,9 +28,12 @@
 \r
 [Sources.ARM]\r
   Arm/ArmGicArchLib.c\r
+  GicV3/Arm/ArmGicV3.S     | GCC\r
+  GicV3/Arm/ArmGicV3.asm   | RVCT\r
 \r
 [Sources.AARCH64]\r
   AArch64/ArmGicArchLib.c\r
+  GicV3/AArch64/ArmGicV3.S | GCC\r
 \r
 [LibraryClasses]\r
   ArmLib\r

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
index 45382998f01b9f28e1164a7b68e434eb09ebfed0..573e5e7e506f363d064e77707a019926f9aadae0 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
@@ -28,9 +28,12 @@
 \r
 [Sources.ARM]\r
   Arm/ArmGicArchLib.c\r
+  GicV3/Arm/ArmGicV3.S     | GCC\r
+  GicV3/Arm/ArmGicV3.asm   | RVCT\r
 \r
 [Sources.AARCH64]\r
   AArch64/ArmGicArchLib.c\r
+  GicV3/AArch64/ArmGicV3.S | GCC\r
 \r
 [Packages]\r
   ArmPkg/ArmPkg.dec\r

diff --git a/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S b/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S
new file mode 100644 (file)
index 0000000..793e8aa
--- /dev/null
+++ b/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S
@@ -0,0 +1,114 @@
+#\r
+#  Copyright (c) 2014, ARM Limited. All rights reserved.\r
+#\r
+#  This program and the accompanying materials are licensed and made available\r
+#  under the terms and conditions of the BSD License which accompanies this\r
+#  distribution. The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php\r
+#\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+\r
+#include <AsmMacroIoLibV8.h>\r
+\r
+#define ICC_SRE_EL1             S3_0_C12_C12_5\r
+#define ICC_SRE_EL2             S3_4_C12_C9_5\r
+#define ICC_SRE_EL3             S3_6_C12_C12_5\r
+#define ICC_IGRPEN1_EL1         S3_0_C12_C12_7\r
+#define ICC_EOIR1_EL1           S3_0_C12_C12_1\r
+#define ICC_IAR1_EL1            S3_0_C12_C12_0\r
+#define ICC_PMR_EL1             S3_0_C4_C6_0\r
+#define ICC_BPR1_EL1            S3_0_C12_C12_3\r
+\r
+.text\r
+.align 2\r
+\r
+GCC_ASM_EXPORT(ArmGicGetControlSystemRegisterEnable)\r
+GCC_ASM_EXPORT(ArmGicSetControlSystemRegisterEnable)\r
+GCC_ASM_EXPORT(ArmGicV3EnableInterruptInterface)\r
+GCC_ASM_EXPORT(ArmGicV3DisableInterruptInterface)\r
+GCC_ASM_EXPORT(ArmGicV3EndOfInterrupt)\r
+GCC_ASM_EXPORT(ArmGicV3AcknowledgeInterrupt)\r
+GCC_ASM_EXPORT(ArmGicV3SetPriorityMask)\r
+GCC_ASM_EXPORT(ArmGicV3SetBinaryPointer)\r
+\r
+//UINT32\r
+//EFIAPI\r
+//ArmGicGetControlSystemRegisterEnable (\r
+//  VOID\r
+//  );\r
+ASM_PFX(ArmGicGetControlSystemRegisterEnable):\r
+        EL1_OR_EL2_OR_EL3(x1)\r
+1:  mrs x0, ICC_SRE_EL1\r
+        b       4f\r
+2:  mrs x0, ICC_SRE_EL2\r
+        b       4f\r
+3:  mrs x0, ICC_SRE_EL3\r
+4:  ret\r
+\r
+//VOID\r
+//EFIAPI\r
+//ArmGicSetControlSystemRegisterEnable (\r
+//  IN UINT32         ControlSystemRegisterEnable\r
+//  );\r
+ASM_PFX(ArmGicSetControlSystemRegisterEnable):\r
+        EL1_OR_EL2_OR_EL3(x1)\r
+1:  msr ICC_SRE_EL1, x0\r
+        b       4f\r
+2:  msr ICC_SRE_EL2, x0\r
+        b       4f\r
+3:  msr ICC_SRE_EL3, x0\r
+4:  isb\r
+        ret\r
+\r
+//VOID\r
+//ArmGicV3EnableInterruptInterface (\r
+//  VOID\r
+//  );\r
+ASM_PFX(ArmGicV3EnableInterruptInterface):\r
+        mov     x0, #1\r
+        msr     ICC_IGRPEN1_EL1, x0\r
+        ret\r
+\r
+//VOID\r
+//ArmGicV3DisableInterruptInterface (\r
+//  VOID\r
+//  );\r
+ASM_PFX(ArmGicV3DisableInterruptInterface):\r
+        mov     x0, #0\r
+        msr     ICC_IGRPEN1_EL1, x0\r
+        ret\r
+\r
+//VOID\r
+//ArmGicV3EndOfInterrupt (\r
+//  IN UINTN          InterruptId\r
+//  );\r
+ASM_PFX(ArmGicV3EndOfInterrupt):\r
+        msr     ICC_EOIR1_EL1, x0\r
+        ret\r
+\r
+//UINTN\r
+//ArmGicV3AcknowledgeInterrupt (\r
+//  VOID\r
+//  );\r
+ASM_PFX(ArmGicV3AcknowledgeInterrupt):\r
+        mrs     x0, ICC_IAR1_EL1\r
+        ret\r
+\r
+//VOID\r
+//ArmGicV3SetPriorityMask (\r
+//  IN UINTN          Priority\r
+//  );\r
+ASM_PFX(ArmGicV3SetPriorityMask):\r
+        msr     ICC_PMR_EL1, x0\r
+        ret\r
+\r
+//VOID\r
+//ArmGicV3SetBinaryPointer (\r
+//  IN UINTN          BinaryPoint\r
+//  );\r
+ASM_PFX(ArmGicV3SetBinaryPointer):\r
+        msr     ICC_BPR1_EL1, x0\r
+        ret\r

diff --git a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S
new file mode 100644 (file)
index 0000000..5c64ec6
--- /dev/null
+++ b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S
@@ -0,0 +1,98 @@
+#\r
+#  Copyright (c) 2014, ARM Limited. All rights reserved.\r
+#\r
+#  This program and the accompanying materials are licensed and made available\r
+#  under the terms and conditions of the BSD License which accompanies this\r
+#  distribution. The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php\r
+#\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Library/ArmLib.h>\r
+\r
+// For the moment we assume this will run in SVC mode on ARMv7\r
+\r
+.text\r
+.align 2\r
+\r
+GCC_ASM_EXPORT(ArmGicGetControlSystemRegisterEnable)\r
+GCC_ASM_EXPORT(ArmGicSetControlSystemRegisterEnable)\r
+GCC_ASM_EXPORT(ArmGicV3EnableInterruptInterface)\r
+GCC_ASM_EXPORT(ArmGicV3DisableInterruptInterface)\r
+GCC_ASM_EXPORT(ArmGicV3EndOfInterrupt)\r
+GCC_ASM_EXPORT(ArmGicV3AcknowledgeInterrupt)\r
+GCC_ASM_EXPORT(ArmGicV3SetPriorityMask)\r
+GCC_ASM_EXPORT(ArmGicV3SetBinaryPointer)\r
+\r
+//UINT32\r
+//EFIAPI\r
+//ArmGicGetControlSystemRegisterEnable (\r
+//  VOID\r
+//  );\r
+ASM_PFX(ArmGicGetControlSystemRegisterEnable):\r
+        mrc     p15, 0, r0, c12, c12, 5 // ICC_SRE\r
+        bx      lr\r
+\r
+//VOID\r
+//EFIAPI\r
+//ArmGicSetControlSystemRegisterEnable (\r
+//  IN UINT32         ControlSystemRegisterEnable\r
+//  );\r
+ASM_PFX(ArmGicSetControlSystemRegisterEnable):\r
+        mcr     p15, 0, r0, c12, c12, 5 // ICC_SRE\r
+        isb\r
+        bx      lr\r
+\r
+//VOID\r
+//ArmGicV3EnableInterruptInterface (\r
+//  VOID\r
+//  );\r
+ASM_PFX(ArmGicV3EnableInterruptInterface):\r
+        mov     r0, #1\r
+        mcr     p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1\r
+        bx      lr\r
+\r
+//VOID\r
+//ArmGicV3DisableInterruptInterface (\r
+//  VOID\r
+//  );\r
+ASM_PFX(ArmGicV3DisableInterruptInterface):\r
+        mov     r0, #0\r
+        mcr     p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1\r
+        bx      lr\r
+\r
+//VOID\r
+//ArmGicV3EndOfInterrupt (\r
+//  IN UINTN InterruptId\r
+//  );\r
+ASM_PFX(ArmGicV3EndOfInterrupt):\r
+        mcr     p15, 0, r0, c12, c12, 1 //ICC_EOIR1\r
+        bx      lr\r
+\r
+//UINTN\r
+//ArmGicV3AcknowledgeInterrupt (\r
+//  VOID\r
+//  );\r
+ASM_PFX(ArmGicV3AcknowledgeInterrupt):\r
+        mrc     p15, 0, r0, c12, c8, 0 //ICC_IAR1\r
+        bx      lr\r
+\r
+//VOID\r
+//ArmGicV3SetPriorityMask (\r
+//  IN UINTN                  Priority\r
+//  );\r
+ASM_PFX(ArmGicV3SetPriorityMask):\r
+        mcr     p15, 0, r0, c4, c6, 0 //ICC_PMR\r
+        bx      lr\r
+\r
+//VOID\r
+//ArmGicV3SetBinaryPointer (\r
+//  IN UINTN                  BinaryPoint\r
+//  );\r
+ASM_PFX(ArmGicV3SetBinaryPointer):\r
+        mcr     p15, 0, r0, c12, c12, 3 //ICC_BPR1\r
+        bx      lr\r

diff --git a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm
new file mode 100644 (file)
index 0000000..08d9d4d
--- /dev/null
+++ b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm
@@ -0,0 +1,96 @@
+//\r
+//  Copyright (c) 2014, ARM Limited. All rights reserved.\r
+//\r
+//  This program and the accompanying materials are licensed and made available\r
+//  under the terms and conditions of the BSD License which accompanies this\r
+//  distribution. The full text of the license may be found at\r
+//  http://opensource.org/licenses/bsd-license.php\r
+//\r
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+\r
+// For the moment we assume this will run in SVC mode on ARMv7\r
+\r
+    EXPORT  ArmGicGetControlSystemRegisterEnable\r
+    EXPORT  ArmGicSetControlSystemRegisterEnable\r
+    EXPORT  ArmGicV3EnableInterruptInterface\r
+    EXPORT  ArmGicV3DisableInterruptInterface\r
+    EXPORT  ArmGicV3EndOfInterrupt\r
+    EXPORT  ArmGicV3AcknowledgeInterrupt\r
+    EXPORT  ArmGicV3SetPriorityMask\r
+    EXPORT  ArmGicV3SetBinaryPointer\r
+\r
+    AREA ArmGicV3, CODE, READONLY\r
+\r
+//UINT32\r
+//EFIAPI\r
+//ArmGicGetControlSystemRegisterEnable (\r
+//  VOID\r
+//  );\r
+ArmGicGetControlSystemRegisterEnable\r
+        mrc     p15, 0, r0, c12, c12, 5 // ICC_SRE\r
+        bx      lr\r
+\r
+//VOID\r
+//EFIAPI\r
+//ArmGicSetControlSystemRegisterEnable (\r
+//  IN UINT32         ControlSystemRegisterEnable\r
+//  );\r
+ArmGicSetControlSystemRegisterEnable\r
+        mcr     p15, 0, r0, c12, c12, 5 // ICC_SRE\r
+        isb\r
+        bx      lr\r
+\r
+//VOID\r
+//ArmGicV3EnableInterruptInterface (\r
+//  VOID\r
+//  );\r
+ArmGicV3EnableInterruptInterface\r
+        mov     r0, #1\r
+        mcr     p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1\r
+        bx      lr\r
+\r
+//VOID\r
+//ArmGicV3DisableInterruptInterface (\r
+//  VOID\r
+//  );\r
+ArmGicV3DisableInterruptInterface\r
+        mov     r0, #0\r
+        mcr     p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1\r
+        bx      lr\r
+\r
+//VOID\r
+//ArmGicV3EndOfInterrupt (\r
+//  IN UINTN InterruptId\r
+//  );\r
+ArmGicV3EndOfInterrupt\r
+        mcr     p15, 0, r0, c12, c12, 1 //ICC_EOIR1\r
+        bx      lr\r
+\r
+//UINTN\r
+//ArmGicV3AcknowledgeInterrupt (\r
+//  VOID\r
+//  );\r
+ArmGicV3AcknowledgeInterrupt\r
+        mrc     p15, 0, r0, c12, c8, 0 //ICC_IAR1\r
+        bx      lr\r
+\r
+//VOID\r
+//ArmGicV3SetPriorityMask (\r
+//  IN UINTN                  Priority\r
+//  );\r
+ArmGicV3SetPriorityMask\r
+        mcr     p15, 0, r0, c4, c6, 0 //ICC_PMR\r
+        bx      lr\r
+\r
+//VOID\r
+//ArmGicV3SetBinaryPointer (\r
+//  IN UINTN                  BinaryPoint\r
+//  );\r
+ArmGicV3SetBinaryPointer\r
+        mcr     p15, 0, r0, c12, c12, 3 //ICC_BPR1\r
+        bx      lr\r
+\r
+    END\r

diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Lib.h b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Lib.h
new file mode 100644 (file)
index 0000000..70731c3
--- /dev/null
+++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Lib.h
@@ -0,0 +1,52 @@
+/** @file\r
+*\r
+*  Copyright (c) 2014, ARM Limited. All rights reserved.\r
+*\r
+*  This program and the accompanying materials are licensed and made available\r
+*  under the terms and conditions of the BSD License which accompanies this\r
+*  distribution. The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#ifndef _ARM_GIC_V3_H_\r
+#define _ARM_GIC_V3_H_\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV3EnableInterruptInterface (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV3DisableInterruptInterface (\r
+  VOID\r
+  );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGicV3AcknowledgeInterrupt (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV3EndOfInterrupt (\r
+  IN UINTN                  Source\r
+  );\r
+\r
+VOID\r
+ArmGicV3SetBinaryPointer (\r
+  IN UINTN                  BinaryPoint\r
+  );\r
+\r
+VOID\r
+ArmGicV3SetPriorityMask (\r
+  IN UINTN                  Priority\r
+  );\r
+\r
+#endif\r