ArmPkg/ArmMmuLib AARCH64: drop pointless page table memory type check

This is the AARCH64 counterpart of commit 1f3b1eb3082206e4, to remove
a pointless check against the memory type of the allocations that the
page tables happened to land in. On ArmV8, we use writeback cacheable
exclusively for all memory.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Message-Id: <20200307091008.14918-2-ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
index 221175ca65357de0d6789becd472afbbe742ab19..f2eec7191328cbbaa4d83476e5935db8889b4fe4 100644 (file)
--- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
+++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
@@ -497,7 +497,6 @@ ArmConfigureMmu (
   )\r
 {\r
   VOID*                         TranslationTable;\r
-  UINT32                        TranslationTableAttribute;\r
   UINT64                        MaxAddress;\r
   UINTN                         T0SZ;\r
   UINTN                         RootTableEntryCount;\r
@@ -618,18 +617,7 @@ ArmConfigureMmu (
     RootTableEntryCount * sizeof(UINT64));\r
   ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64));\r
 \r
-  TranslationTableAttribute = TT_ATTR_INDX_INVALID;\r
   while (MemoryTable->Length != 0) {\r
-\r
-    DEBUG_CODE_BEGIN ();\r
-      // Find the memory attribute for the Translation Table\r
-      if ((UINTN)TranslationTable >= MemoryTable->PhysicalBase &&\r
-          (UINTN)TranslationTable + EFI_PAGE_SIZE <= MemoryTable->PhysicalBase +\r
-                                                          MemoryTable->Length) {\r
-        TranslationTableAttribute = MemoryTable->Attributes;\r
-      }\r
-    DEBUG_CODE_END ();\r
-\r
     Status = FillTranslationTable (TranslationTable, MemoryTable);\r
     if (EFI_ERROR (Status)) {\r
       goto FREE_TRANSLATION_TABLE;\r
@@ -637,9 +625,6 @@ ArmConfigureMmu (
     MemoryTable++;\r
   }\r
 \r
-  ASSERT (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ||\r
-          TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK);\r
-\r
   ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) |                      // mapped to EFI_MEMORY_UC\r
               MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC\r
               MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) | // mapped to EFI_MEMORY_WT\r