All POWER_MGMT_REGISTER_PIIX4() macro invocations in OvmfPkg should use
the macros in "I440FxPiix4.h" as arguments.
Cc: Gabriel Somlo <somlo@cmu.edu>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17435
6f19259b-4bc3-4df7-8a09-
765794883524
// Power Management PCI Configuration Register fields\r
//\r
#define PMBA_RTE BIT0\r
-#define PIIX4_PMIOSE BIT0\r
\r
//\r
// Offset in the Power Management Base Address to the ACPI Timer\r
HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
switch (HostBridgeDevId) {\r
case INTEL_82441_DEVICE_ID:\r
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
- AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC\r
- AcpiEnBit = PIIX4_PMIOSE;\r
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
+ AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
+ AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
break;\r
case INTEL_Q35_MCH_DEVICE_ID:\r
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
// Power Management PCI Configuration Register fields\r
//\r
#define PMBA_RTE BIT0\r
-#define PIIX4_PMIOSE BIT0\r
\r
//\r
// Offset in the Power Management Base Address to the ACPI Timer\r
HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
switch (HostBridgeDevId) {\r
case INTEL_82441_DEVICE_ID:\r
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
- AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC\r
- AcpiEnBit = PIIX4_PMIOSE;\r
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
+ AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
+ AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
break;\r
case INTEL_Q35_MCH_DEVICE_ID:\r
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
switch (HostBridgeDevId) {\r
case INTEL_82441_DEVICE_ID:\r
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
break;\r
case INTEL_Q35_MCH_DEVICE_ID:\r
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);\r
switch (HostBridgeDevId) {\r
case INTEL_82441_DEVICE_ID:\r
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
break;\r
case INTEL_Q35_MCH_DEVICE_ID:\r
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
mHostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);\r
switch (mHostBridgeDevId) {\r
case INTEL_82441_DEVICE_ID:\r
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
//\r
// 00:01.0 ISA Bridge (PIIX4) LNK routing targets\r
//\r
switch (HostBridgeDevId) {\r
case INTEL_82441_DEVICE_ID:\r
PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
- AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC\r
- AcpiEnBit = BIT0; // PIIX4_PMIOSE\r
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
+ AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
+ AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
break;\r
case INTEL_Q35_MCH_DEVICE_ID:\r
PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r