--- /dev/null
+/** @file\r
+ This file defines the Legacy SPI Controller Protocol.\r
+\r
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD\r
+ License which accompanies this distribution. The full text of the license may\r
+ be found at http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ This Protocol was introduced in UEFI PI Specification 1.6.\r
+\r
+**/\r
+\r
+#ifndef __LEGACY_SPI_CONTROLLER_PROTOCOL_H__\r
+#define __LEGACY_SPI_CONTROLLER_PROTOCOL_H__\r
+\r
+///\r
+/// Note: The UEFI PI 1.6 specification uses the character 'l' in the GUID\r
+/// definition. This definition assumes it was supposed to be '1'.\r
+///\r
+/// Global ID for the Legacy SPI Controller Protocol\r
+///\r
+#define EFI_LEGACY_SPI_CONTROLLER_GUID \\r
+ { 0x39136fc7, 0x1a11, 0x49de, \\r
+ { 0xbf, 0x35, 0x0e, 0x78, 0xdd, 0xb5, 0x24, 0xfc }}\r
+\r
+typedef\r
+struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL\r
+EFI_LEGACY_SPI_CONTROLLER_PROTOCOL;\r
+\r
+/**\r
+ Set the erase block opcode.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ The menu table contains SPI transaction opcodes which are accessible after\r
+ the legacy SPI flash controller's configuration is locked. The board layer\r
+ specifies the erase block size for the SPI NOR flash part. The SPI NOR flash\r
+ peripheral driver selects the erase block opcode which matches the erase\r
+ block size and uses this API to load the opcode into the opcode menu table.\r
+\r
+ @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL\r
+ structure.\r
+ @param[in] EraseBlockOpcode Erase block opcode to be placed into the opcode\r
+ menu table.\r
+\r
+ @retval EFI_SUCCESS The opcode menu table was updated\r
+ @retval EFI_ACCESS_ERROR The SPI controller is locked\r
+\r
+**/\r
+typedef EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_ERASE_BLOCK_OPCODE) (\r
+ IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,\r
+ IN UINT8 EraseBlockOpcode\r
+ );\r
+\r
+/**\r
+ Set the write status prefix opcode.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ The prefix table contains SPI transaction write prefix opcodes which are\r
+ accessible after the legacy SPI flash controller's configuration is locked.\r
+ The board layer specifies the write status prefix opcode for the SPI NOR\r
+ flash part. The SPI NOR flash peripheral driver uses this API to load the\r
+ opcode into the prefix table.\r
+\r
+ @param[in] This Pointer to an\r
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure.\r
+ @param[in] WriteStatusPrefix Prefix opcode for the write status command.\r
+\r
+ @retval EFI_SUCCESS The prefix table was updated\r
+ @retval EFI_ACCESS_ERROR The SPI controller is locked\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_WRITE_STATUS_PREFIX) (\r
+ IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,\r
+ IN UINT8 WriteStatusPrefix\r
+ );\r
+\r
+/**\r
+ Set the BIOS base address.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ The BIOS base address works with the protect range registers to protect\r
+ portions of the SPI NOR flash from erase and write operat ions. The BIOS\r
+ calls this API prior to passing control to the OS loader.\r
+\r
+ @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL\r
+ structure.\r
+ @param[in] BiosBaseAddress The BIOS base address.\r
+\r
+ @retval EFI_SUCCESS The BIOS base address was properly set\r
+ @retval EFI_ACCESS_ERROR The SPI controller is locked\r
+ @retval EFI_INVALID_PARAMETER The BIOS base address is greater than\r
+ This->Maxi.mumOffset\r
+ @retval EFI_UNSUPPORTED The BIOS base address was already set\r
+\r
+**/\r
+typedef EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_BIOS_BASE_ADDRESS) (\r
+ IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,\r
+ IN UINT32 BiosBaseAddress\r
+ );\r
+\r
+/**\r
+ Clear the SPI protect range registers.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ The BIOS uses this routine to set an initial condition on the SPI protect\r
+ range registers.\r
+\r
+ @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure.\r
+\r
+ @retval EFI_SUCCESS The registers were successfully cleared\r
+ @retval EFI_ACCESS_ERROR The SPI controller is locked\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_CLEAR_SPI_PROTECT) (\r
+ IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This\r
+ );\r
+\r
+/**\r
+ Determine if the SPI range is protected.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ The BIOS uses this routine to verify a range in the SPI is protected.\r
+\r
+ @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL\r
+ structure.\r
+ @param[in] BiosAddress Address within a 4 KiB block to start protecting.\r
+ @param[in] BytesToProtect The number of 4 KiB blocks to protect.\r
+\r
+ @retval TRUE The range is protected\r
+ @retval FALSE The range is not protected\r
+\r
+**/\r
+typedef\r
+BOOLEAN\r
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_IS_RANGE_PROTECTED) (\r
+ IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,\r
+ IN UINT32 BiosAddress,\r
+ IN UINT32 BlocksToProtect\r
+ );\r
+\r
+/**\r
+ Set the next protect range register.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ The BIOS sets the protect range register to prevent write and erase\r
+ operations to a portion of the SPI NOR flash device.\r
+\r
+ @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL\r
+ structure.\r
+ @param[in] BiosAddress Address within a 4 KiB block to start protecting.\r
+ @param[in] BlocksToProtect The number of 4 KiB blocks to protect.\r
+\r
+ @retval EFI_SUCCESS The register was successfully updated\r
+ @retval EFI_ACCESS_ERROR The SPI controller is locked\r
+ @retval EFI_INVALID_PARAMETER BiosAddress < This->BiosBaseAddress, or\r
+ BlocksToProtect * 4 KiB\r
+ > This->MaximumRangeBytes, or\r
+ BiosAddress - This->BiosBaseAddress\r
+ + (BlocksToProtect * 4 KiB)\r
+ > This->MaximumRangeBytes\r
+ @retval EFI_OUT_OF_RESOURCES No protect range register available\r
+ @retval EFI_UNSUPPORTED Call This->SetBaseAddress because the BIOS base\r
+ address is not set\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_PROTECT_NEXT_RANGE) (\r
+ IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,\r
+ IN UINT32 BiosAddress,\r
+ IN UINT32 BlocksToProtect\r
+ );\r
+\r
+/**\r
+ Lock the SPI controller configuration.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ This routine locks the SPI controller's configuration so that the software\r
+ is no longer able to update:\r
+ * Prefix table\r
+ * Opcode menu\r
+ * Opcode type table\r
+ * BIOS base address\r
+ * Protect range registers\r
+\r
+ @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure.\r
+\r
+ @retval EFI_SUCCESS The SPI controller was successfully locked\r
+ @retval EFI_ALREADY_STARTED The SPI controller was already locked\r
+\r
+**/\r
+typedef EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_LOCK_CONTROLLER) (\r
+ IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This\r
+ );\r
+\r
+///\r
+/// Support the extra features of the legacy SPI flash controller.\r
+///\r
+struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL {\r
+ ///\r
+ /// Maximum offset from the BIOS base address that is able to be protected.\r
+ ///\r
+ UINT32 MaximumOffset;\r
+\r
+ ///\r
+ /// Maximum number of bytes that can be protected by one range register.\r
+ ///\r
+ UINT32 MaximumRangeBytes;\r
+\r
+ ///\r
+ /// The number of registers available for protecting the BIOS.\r
+ ///\r
+ UINT32 RangeRegisterCount;\r
+\r
+ ///\r
+ /// Set the erase block opcode.\r
+ ///\r
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_ERASE_BLOCK_OPCODE EraseBlockOpcode;\r
+\r
+ ///\r
+ /// Set the write status prefix opcode.\r
+ ///\r
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_WRITE_STATUS_PREFIX WriteStatusPrefix;\r
+\r
+ ///\r
+ /// Set the BIOS base address.\r
+ ///\r
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_BIOS_BASE_ADDRESS BiosBaseAddress;\r
+\r
+ ///\r
+ /// Clear the SPI protect range registers.\r
+ ///\r
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_CLEAR_SPI_PROTECT ClearSpiProtect;\r
+\r
+ ///\r
+ /// Determine if the SPI range is protected.\r
+ ///\r
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_IS_RANGE_PROTECTED IsRangeProtected;\r
+\r
+ ///\r
+ /// Set the next protect range register.\r
+ ///\r
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_PROTECT_NEXT_RANGE ProtectNextRange;\r
+\r
+ ///\r
+ /// Lock the SPI controller configuration.\r
+ ///\r
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_LOCK_CONTROLLER LockController;\r
+};\r
+\r
+extern EFI_GUID gEfiLegacySpiControllerProtocolGuid;\r
+\r
+#endif // __LEGACY_SPI_CONTROLLER_PROTOCOL_H__\r
--- /dev/null
+/** @file\r
+ This file defines the Legacy SPI Flash Protocol.\r
+\r
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD\r
+ License which accompanies this distribution. The full text of the license may\r
+ be found at http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ This Protocol was introduced in UEFI PI Specification 1.6.\r
+\r
+**/\r
+\r
+#ifndef __LEGACY_SPI_FLASH_PROTOCOL_H__\r
+#define __LEGACY_SPI_FLASH_PROTOCOL_H__\r
+\r
+#include <Protocol/SpiNorFlash.h>\r
+\r
+///\r
+/// Global ID for the Legacy SPI Flash Protocol\r
+///\r
+#define EFI_LEGACY_SPI_FLASH_PROTOCOL_GUID \\r
+ { 0xf01bed57, 0x04bc, 0x4f3f, \\r
+ { 0x96, 0x60, 0xd6, 0xf2, 0xea, 0x22, 0x82, 0x59 }}\r
+\r
+typedef struct _EFI_LEGACY_SPI_FLASH_PROTOCOL EFI_LEGACY_SPI_FLASH_PROTOCOL;\r
+\r
+/**\r
+ Set the BIOS base address.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ The BIOS base address works with the protect range registers to protect\r
+ portions of the SPI NOR flash from erase and write operat ions.\r
+ The BIOS calls this API prior to passing control to the OS loader.\r
+\r
+ @param[in] This Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data\r
+ structure.\r
+ @param[in] BiosBaseAddress The BIOS base address.\r
+\r
+ @retval EFI_SUCCESS The BIOS base address was properly set\r
+ @retval EFI_ACCESS_ERROR The SPI controller is locked\r
+ @retval EFI_INVALID_PARAMETER BiosBaseAddress > This->MaximumOffset\r
+ @retval EFI_UNSUPPORTED The BIOS base address was already set or not a\r
+ legacy SPI host controller\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_BIOS_BASE_ADDRESS) (\r
+ IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This,\r
+ IN UINT32 BiosBaseAddress\r
+ );\r
+\r
+/**\r
+ Clear the SPI protect range registers.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ The BIOS uses this routine to set an initial condition on the SPI protect\r
+ range registers.\r
+\r
+ @param[in] This Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data structure.\r
+\r
+ @retval EFI_SUCCESS The registers were successfully cleared\r
+ @retval EFI_ACCESS_ERROR The SPI controller is locked\r
+ @retval EFI_UNSUPPORTED Not a legacy SPI host controller\r
+\r
+**/\r
+typedef EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_CLEAR_SPI_PROTECT) (\r
+ IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This\r
+ );\r
+\r
+/**\r
+ Determine if the SPI range is protected.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ The BIOS uses this routine to verify a range in the SPI is protected.\r
+\r
+ @param[in] This Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data\r
+ structure.\r
+ @param[in] BiosAddress Address within a 4 KiB block to start protecting.\r
+ @param[in] BlocksToProtect The number of 4 KiB blocks to protect.\r
+\r
+ @retval TRUE The range is protected\r
+ @retval FALSE The range is not protected\r
+\r
+**/\r
+typedef\r
+BOOLEAN\r
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_IS_RANGE_PROTECTED) (\r
+ IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This,\r
+ IN UINT32 BiosAddress,\r
+ IN UINT32 BlocksToProtect\r
+ );\r
+\r
+/**\r
+ Set the next protect range register.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ The BIOS sets the protect range register to prevent write and erase\r
+ operations to a portion of the SPI NOR flash device.\r
+\r
+ @param[in] This Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data\r
+ structure.\r
+ @param[in] BiosAddress Address within a 4 KiB block to start protecting.\r
+ @param[in] BlocksToProtect The number of 4 KiB blocks to protect.\r
+\r
+ @retval EFI_SUCCESS The register was successfully updated\r
+ @retval EFI_ACCESS_ERROR The SPI controller is locked\r
+ @retval EFI_INVALID_PARAMETER BiosAddress < This->BiosBaseAddress, or\r
+ @retval EFI_INVALID_PARAMETER BlocksToProtect * 4 KiB\r
+ > This->MaximumRangeBytes, or\r
+ BiosAddress - This->BiosBaseAddress\r
+ + (BlocksToProtect * 4 KiB)\r
+ > This->MaximumRangeBytes\r
+ @retval EFI_OUT_OF_RESOURCES No protect range register available\r
+ @retval EFI_UNSUPPORTED Call This->SetBaseAddress because the BIOS\r
+ base address is not set Not a legacy SPI host\r
+ controller\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_PROTECT_NEXT_RANGE) (\r
+ IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This,\r
+ IN UINT32 BiosAddress,\r
+ IN UINT32 BlocksToProtect\r
+ );\r
+\r
+/**\r
+ Lock the SPI controller configuration.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ This routine locks the SPI controller's configuration so that the software is\r
+ no longer able to update:\r
+ * Prefix table\r
+ * Opcode menu\r
+ * Opcode type table\r
+ * BIOS base address\r
+ * Protect range registers\r
+\r
+ @param[in] This Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data structure.\r
+\r
+ @retval EFI_SUCCESS The SPI controller was successfully locked\r
+ @retval EFI_ALREADY_STARTED The SPI controller was already locked\r
+ @retval EFI_UNSUPPORTED Not a legacy SPI host controller\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_LOCK_CONTROLLER) (\r
+ IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This\r
+ );\r
+\r
+///\r
+/// The EFI_LEGACY_SPI_FLASH_PROTOCOL extends the EFI_SPI_NOR_FLASH_PROTOCOL\r
+/// with APls to support the legacy SPI flash controller.\r
+///\r
+struct _EFI_LEGACY_SPI_FLASH_PROTOCOL {\r
+ ///\r
+ /// This protocol manipulates the SPI NOR flash parts using a common set of\r
+ /// commands.\r
+ ///\r
+ EFI_SPI_NOR_FLASH_PROTOCOL FlashProtocol;\r
+\r
+ //\r
+ // Legacy flash (SPI host) controller support\r
+ //\r
+\r
+ ///\r
+ /// Set the BIOS base address.\r
+ ///\r
+ EFI_LEGACY_SPI_FLASH_PROTOCOL_BIOS_BASE_ADDRESS BiosBaseAddress;\r
+\r
+ ///\r
+ /// Clear the SPI protect range registers.\r
+ ///\r
+ EFI_LEGACY_SPI_FLASH_PROTOCOL_CLEAR_SPI_PROTECT ClearSpiProtect;\r
+\r
+ ///\r
+ /// Determine if the SPI range is protected.\r
+ ///\r
+ EFI_LEGACY_SPI_FLASH_PROTOCOL_IS_RANGE_PROTECTED IsRangeProtected;\r
+\r
+ ///\r
+ /// Set the next protect range register.\r
+ ///\r
+ EFI_LEGACY_SPI_FLASH_PROTOCOL_PROTECT_NEXT_RANGE ProtectNextRange;\r
+\r
+ ///\r
+ /// Lock the SPI controller configuration.\r
+ ///\r
+ EFI_LEGACY_SPI_FLASH_PROTOCOL_LOCK_CONTROLLER LockController;\r
+};\r
+\r
+extern EFI_GUID gEfiLegacySpiFlashProtocolGuid;\r
+\r
+#endif // __LEGACY_SPI_FLASH_PROTOCOL_H__\r
--- /dev/null
+/** @file\r
+ This file defines the Legacy SPI SMM Controler Protocol.\r
+\r
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD\r
+ License which accompanies this distribution. The full text of the license may\r
+ be found at http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ This Protocol was introduced in UEFI PI Specification 1.6.\r
+\r
+**/\r
+\r
+#ifndef __LEGACY_SPI_SMM_CONTROLLER_PROTOCOL_H__\r
+#define __LEGACY_SPI_SMM_CONTROLLER_PROTOCOL_H__\r
+\r
+#include <Protocol/LegacySpiController.h>\r
+\r
+///\r
+/// Global ID for the Legacy SPI SMM Controller Protocol\r
+///\r
+#define EFI_LEGACY_SPI_SMM_CONTROLLER_PROTOCOL_GUID \\r
+ { 0x62331b78, 0xd8d0, 0x4c8c, \\r
+ { 0x8c, 0xcb, 0xd2, 0x7d, 0xfe, 0x32, 0xdb, 0x9b }}\r
+\r
+typedef\r
+struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL\r
+EFI_LEGACY_SPI_SMM_CONTROLLER_PROTOCOL;\r
+\r
+extern EFI_GUID gEfiLegacySpiSmmControllerProtocolGuid;\r
+\r
+#endif // __LEGACY_SPI_SMM_CONTROLLER_PROTOCOL_H__\r
--- /dev/null
+/** @file\r
+ This file defines the Legacy SPI SMM Flash Protocol.\r
+\r
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD\r
+ License which accompanies this distribution. The full text of the license may\r
+ be found at http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ This Protocol was introduced in UEFI PI Specification 1.6.\r
+\r
+**/\r
+\r
+#ifndef __LEGACY_SPI_SMM_FLASH_PROTOCOL_H__\r
+#define __LEGACY_SPI_SMM_FLASH_PROTOCOL_H__\r
+\r
+#include <Protocol/LegacySpiFlash.h>\r
+\r
+///\r
+/// Global ID for the Legacy SPI SMM Flash Protocol\r
+///\r
+#define EFI_LEGACY_SPI_SMM_FLASH_PROTOCOL_GUID \\r
+ { 0x5e3848d4, 0x0db5, 0x4fc0, \\r
+ { 0x97, 0x29, 0x3f, 0x35, 0x3d, 0x4f, 0x87, 0x9f }}\r
+\r
+typedef\r
+struct _EFI_LEGACY_SPI_FLASH_PROTOCOL\r
+EFI_LEGACY_SPI_SMM_FLASH_PROTOCOL;\r
+\r
+extern EFI_GUID gEfiLegacySpiSmmFlashProtocolGuid;\r
+\r
+#endif // __SPI_SMM_FLASH_PROTOCOL_H__\r
--- /dev/null
+/** @file\r
+ This file defines the SPI Configuration Protocol.\r
+\r
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD\r
+ License which accompanies this distribution. The full text of the license may\r
+ be found at http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ This Protocol was introduced in UEFI PI Specification 1.6.\r
+\r
+**/\r
+\r
+#ifndef __SPI_CONFIGURATION_PROTOCOL_H__\r
+#define __SPI_CONFIGURATION_PROTOCOL_H__\r
+\r
+///\r
+/// Global ID for the SPI Configuration Protocol\r
+///\r
+#define EFI_SPI_CONFIGURATION_GUID \\r
+ { 0x85a6d3e6, 0xb65b, 0x4afc, \\r
+ { 0xb3, 0x8f, 0xc6, 0xd5, 0x4a, 0xf6, 0xdd, 0xc8 }}\r
+\r
+///\r
+/// Macros to easily specify frequencies in hertz, kilohertz and megahertz.\r
+///\r
+#define Hz(Frequency) (Frequency)\r
+#define KHz(Frequency) (1000 * Hz (Frequency))\r
+#define MHz(Frequency) (1000 * KHz (Frequency))\r
+\r
+typedef struct _EFI_SPI_PERIPHERAL EFI_SPI_PERIPHERAL;\r
+\r
+/**\r
+ Manipulate the chip select for a SPI device.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ Update the value of the chip select line for a SPI peripheral.\r
+ The SPI bus layer calls this routine either in the board layer or in the SPI\r
+ controller to manipulate the chip select pin at the start and end of a SPI\r
+ transaction.\r
+\r
+ @param[in] SpiPeripheral The address of an EFI_SPI_PERIPHERAL data structure\r
+ describing the SPI peripheral whose chip select pin\r
+ is to be manipulated. The routine may access the\r
+ ChipSelectParameter field to gain sufficient\r
+ context to complete the operation.\r
+ @param[in] PinValue The value to be applied to the chip select line of\r
+ the SPI peripheral.\r
+\r
+ @retval EFI_SUCCESS The chip select was set successfully\r
+ @retval EFI_NOT_READY Support for the chip select is not properly\r
+ initialized\r
+ @retval EFI_INVALID_PARAMETER The SpiPeripheral->ChipSelectParameter value\r
+ is invalid\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPI_CHIP_SELECT) (\r
+ IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral,\r
+ IN BOOLEAN PinValue\r
+ );\r
+\r
+/**\r
+ Set up the clock generator to produce the correct clock frequency, phase and\r
+ polarity for a SPI chip.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ This routine updates the clock generator to generate the correct frequency\r
+ and polarity for the SPI clock.\r
+\r
+ @param[in] SpiPeripheral Pointer to a EFI_SPI_PERIPHERAL data structure from\r
+ which the routine can access the ClockParameter,\r
+ ClockPhase and ClockPolarity fields. The routine\r
+ also has access to the names for the SPI bus and\r
+ chip which can be used during debugging.\r
+ @param[in] ClockHz Pointer to the requested clock frequency. The clock\r
+ generator will choose a supported clock frequency\r
+ which is less then or equal to this value.\r
+ Specify zero to turn the clock generator off.\r
+ The actual clock frequency supported by the clock\r
+ generator will be returned.\r
+\r
+ @retval EFI_SUCCESS The clock was set up successfully\r
+ @retval EFI_UNSUPPORTED The SPI controller was not able to support the\r
+ frequency requested by CLockHz\r
+\r
+**/\r
+typedef EFI_STATUS\r
+(EFIAPI *EFI_SPI_CLOCK) (\r
+ IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral,\r
+ IN UINT32 *ClockHz\r
+ );\r
+\r
+///\r
+/// The EFI_SPI_PART data structure provides a description of a SPI part which\r
+/// is independent of the use on the board. This data is available directly\r
+/// from the part's datasheet and may be provided by the vendor.\r
+///\r
+typedef struct _EFI_SPI_PART {\r
+ ///\r
+ /// A Unicode string specifying the SPI chip vendor.\r
+ ///\r
+ CONST CHAR16 *Vendor;\r
+\r
+ ///\r
+ /// A Unicode string specifying the SPI chip part number.\r
+ ///\r
+ CONST CHAR16 *PartNumber;\r
+\r
+ ///\r
+ /// The minimum SPI bus clock frequency used to access this chip. This value\r
+ /// may be specified in the chip's datasheet. If not, use the value of zero.\r
+ ///\r
+ UINT32 MinClockHz;\r
+\r
+ ///\r
+ /// The maximum SPI bus clock frequency used to access this chip. This value\r
+ /// is found in the chip's datasheet.\r
+ ///\r
+ UINT32 MaxClockHz;\r
+\r
+ ///\r
+ /// Specify the polarity of the chip select pin. This value can be found in\r
+ /// the SPI chip's datasheet. Specify TRUE when a one asserts the chip select\r
+ ///and FALSE when a zero asserts the chip select.\r
+ ///\r
+ BOOLEAN ChipSelectPolarity;\r
+} EFI_SPI_PART;\r
+\r
+///\r
+/// The EFI_SPI_BUS data structure provides the connection details between the\r
+/// physical SPI bus and the EFI_SPI_HC_PROTOCOL instance which controls that\r
+/// SPI bus. This data structure also describes the details of how the clock is\r
+/// generated for that SPI bus. Finally this data structure provides the list\r
+/// of physical SPI devices which are attached to the SPI bus.\r
+///\r
+typedef struct _EFI_SPI_BUS {\r
+ ///\r
+ /// A Unicode string describing the SPI bus\r
+ ///\r
+ CONST CHAR16 *FriendlyName;\r
+\r
+ ///\r
+ /// Address of the first EFI_SPI_PERIPHERAL data structure connected to this\r
+ /// bus. Specify NULL if there are no SPI peripherals connected to this bus.\r
+ ///\r
+ CONST EFI_SPI_PERIPHERAL *Peripherallist;\r
+\r
+ ///\r
+ /// Address of an EFI_DEVICE_PATH_PROTOCOL data structure which uniquely\r
+ /// describes the SPI controller.\r
+ ///\r
+ CONST EFI_DEVICE_PATH_PROTOCOL *ControllerPath;\r
+\r
+ ///\r
+ /// Address of the routine which controls the clock used by the SPI bus for\r
+ /// this SPI peripheral. The SPI host co ntroller's clock routine is called\r
+ /// when this value is set to NULL.\r
+ ///\r
+ EFI_SPI_CLOCK Clock;\r
+\r
+ ///\r
+ /// Address of a data structure containing the additional values which\r
+ /// describe the necessary control for the clock. When Clock is NULL,\r
+ /// the declaration for this data structure is provided by the vendor of the\r
+ /// host's SPI controller driver. When Clock is not NULL, the declaration for\r
+ /// this data structure is provided by the board layer.\r
+ ///\r
+ VOID *ClockParameter;\r
+} EFI_SPI_BUS;\r
+\r
+///\r
+/// The EFI_SPI_PERIPHERAL data structure describes how a specific block of\r
+/// logic which is connected to the SPI bus. This data structure also selects\r
+/// which upper level driver is used to manipulate this SPI device.\r
+/// The SpiPeripheraLDriverGuid is available from the vendor of the SPI\r
+/// peripheral driver.\r
+///\r
+struct _EFI_SPI_PERIPHERAL {\r
+ ///\r
+ /// Address of the next EFI_SPI_PERIPHERAL data structure. Specify NULL if\r
+ /// the current data structure is the last one on the SPI bus.\r
+ ///\r
+ CONST EFI_SPI_PERIPHERAL *NextSpiPeripheral;\r
+\r
+ ///\r
+ /// A unicode string describing the function of the SPI part.\r
+ ///\r
+ CONST CHAR16 *FriendlyName;\r
+\r
+ ///\r
+ /// Address of a GUID provided by the vendor of the SPI peripheral driver.\r
+ /// Instead of using a " EFI_SPI_IO_PROTOCOL" GUID, the SPI bus driver uses\r
+ /// this GUID to identify an EFI_SPI_IO_PROTOCOL data structure and to\r
+ /// provide the connection points for the SPI peripheral drivers.\r
+ /// This reduces the comparison logic in the SPI peripheral driver's\r
+ /// Supported routine.\r
+ ///\r
+ CONST GUID *SpiPeripheralDriverGuid;\r
+\r
+ ///\r
+ /// The address of an EFI_SPI_PART data structure which describes this chip.\r
+ ///\r
+ CONST EFI_SPI_PART *SpiPart;\r
+\r
+ ///\r
+ /// The maximum clock frequency is specified in the EFI_SPI_P ART. When this\r
+ /// this value is non-zero and less than the value in the EFI_SPI_PART then\r
+ /// this value is used for the maximum clock frequency for the SPI part.\r
+ ///\r
+ UINT32 MaxClockHz;\r
+\r
+ ///\r
+ /// Specify the idle value of the clock as found in the datasheet.\r
+ /// Use zero (0) if the clock'S idle value is low or one (1) if the the\r
+ /// clock's idle value is high.\r
+ ///\r
+ BOOLEAN ClockPolarity;\r
+\r
+ ///\r
+ /// Specify the clock delay after chip select. Specify zero (0) to delay an\r
+ /// entire clock cycle or one (1) to delay only half a clock cycle.\r
+ ///\r
+ BOOLEAN ClockPhase;\r
+\r
+ ///\r
+ /// SPI peripheral attributes, select zero or more of:\r
+ /// * SPI_PART_SUPPORTS_2_B1T_DATA_BUS_W1DTH - The SPI peripheral is wired to\r
+ /// support a 2-bit data bus\r
+ /// * SPI_PART_SUPPORTS_4_B1T_DATA_BUS_W1DTH - The SPI peripheral is wired to\r
+ /// support a 4-bit data bus\r
+ ///\r
+ UINT32 Attributes;\r
+\r
+ ///\r
+ /// Address of a vendor specific data structure containing additional board\r
+ /// configuration details related to the SPI chip. The SPI peripheral layer\r
+ /// uses this data structure when configuring the chip.\r
+ ///\r
+ CONST VOID *ConfigurationData;\r
+\r
+ ///\r
+ /// The address of an EFI_SPI_BUS data structure which describes the SPI bus\r
+ /// to which this chip is connected.\r
+ ///\r
+ CONST EFI_SPI_BUS *SpiBus;\r
+\r
+ ///\r
+ /// Address of the routine which controls the chip select pin for this SPI\r
+ /// peripheral. Call the SPI host controller's chip select routine when this\r
+ /// value is set to NULL.\r
+ ///\r
+ EFI_SPI_CHIP_SELECT ChipSelect;\r
+\r
+ ///\r
+ /// Address of a data structure containing the additional values which\r
+ /// describe the necessary control for the chip select. When ChipSelect is\r
+ /// NULL, the declaration for this data structure is provided by the vendor\r
+ /// of the host's SPI controller driver. The vendor's documentation specifies\r
+ /// the necessary values to use for the chip select pin selection and\r
+ /// control. When Chipselect is not NULL, the declaration for this data\r
+ /// structure is provided by the board layer.\r
+ ///\r
+ VOID *ChipSelectParameter;\r
+};\r
+\r
+///\r
+/// Describe the details of the board's SPI busses to the SPI driver stack.\r
+/// The board layer uses the EFI_SPI_CONFIGURATION_PROTOCOL to expose the data\r
+/// tables which describe the board's SPI busses, The SPI bus layer uses these\r
+/// tables to configure the clock, chip select and manage the SPI transactions\r
+/// on the SPI controllers.\r
+///\r
+typedef struct _EFI_SPI_CONFIGURATION_PROTOCOL {\r
+ ///\r
+ /// The number of SPI busses on the board.\r
+ ///\r
+ UINT32 BusCount;\r
+\r
+ ///\r
+ /// The address of an array of EFI_SPI_BUS data structure addresses.\r
+ ///\r
+ CONST EFI_SPI_BUS *CONST *CONST Buslist;\r
+} EFI_SPI_CONFIGURATION_PROTOCOL;\r
+\r
+extern EFI_GUID gEfiSpiConfigurationProtocolGuid;\r
+\r
+#endif // __SPI_CONFIGURATION_PROTOCOL_H__\r
--- /dev/null
+/** @file\r
+ This file defines the SPI Host Controller Protocol.\r
+\r
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD\r
+ License which accompanies this distribution. The full text of the license may\r
+ be found at http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ This Protocol was introduced in UEFI PI Specification 1.6.\r
+\r
+**/\r
+\r
+#ifndef __SPI_HC_PROTOCOL_H__\r
+#define __SPI_HC_PROTOCOL_H__\r
+\r
+#include <Protocol/SpiConfiguration.h>\r
+#include <Protocol/SpiIo.h>\r
+\r
+///\r
+/// Global ID for the SPI Host Controller Protocol\r
+///\r
+#define EFI_SPI_HOST_GUID \\r
+ { 0xc74e5db2, 0xfa96, 0x4ae2, \\r
+ { 0xb3, 0x99, 0x15, 0x97, 0x7f, 0xe3, 0x0, 0x2d }}\r
+\r
+///\r
+/// EDK2-style name\r
+///\r
+#define EFI_SPI_HC_PROTOCOL_GUID EFI_SPI_HOST_GUID\r
+\r
+typedef struct _EFI_SPI_HC_PROTOCOL EFI_SPI_HC_PROTOCOL;\r
+\r
+/**\r
+ Assert or deassert the SPI chip select.\r
+\r
+ This routine is called at TPL_NOTIFY.\r
+ Update the value of the chip select line for a SPI peripheral. The SPI bus\r
+ layer calls this routine either in the board layer or in the SPI controller\r
+ to manipulate the chip select pin at the start and end of a SPI transaction.\r
+\r
+ @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure.\r
+ @param[in] SpiPeripheral The address of an EFI_SPI_PERIPHERAL data structure\r
+ describing the SPI peripheral whose chip select pin\r
+ is to be manipulated. The routine may access the\r
+ ChipSelectParameter field to gain sufficient\r
+ context to complete the operati on.\r
+ @param[in] PinValue The value to be applied to the chip select line of\r
+ the SPI peripheral.\r
+\r
+ @retval EFI_SUCCESS The chip select was set as requested\r
+ @retval EFI_NOT_READY Support for the chip select is not properly\r
+ initialized\r
+ @retval EFI_INVALID_PARAMETER The ChipSeLect value or its contents are\r
+ invalid\r
+\r
+**/\r
+typedef EFI_STATUS\r
+(EFIAPI *EFI_SPI_HC_PROTOCOL_CHIP_SELECT) (\r
+ IN CONST EFI_SPI_HC_PROTOCOL *This,\r
+ IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral,\r
+ IN BOOLEAN PinValue\r
+ );\r
+\r
+/**\r
+ Set up the clock generator to produce the correct clock frequency, phase and\r
+ polarity for a SPI chip.\r
+\r
+ This routine is called at TPL_NOTIFY.\r
+ This routine updates the clock generator to generate the correct frequency\r
+ and polarity for the SPI clock.\r
+\r
+ @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure.\r
+ @param[in] SpiPeripheral Pointer to a EFI_SPI_PERIPHERAL data structure from\r
+ which the routine can access the ClockParameter,\r
+ ClockPhase and ClockPolarity fields. The routine\r
+ also has access to the names for the SPI bus and\r
+ chip which can be used during debugging.\r
+ @param[in] ClockHz Pointer to the requested clock frequency. The SPI\r
+ host controller will choose a supported clock\r
+ frequency which is less then or equal to this\r
+ value. Specify zero to turn the clock generator\r
+ off. The actual clock frequency supported by the\r
+ SPI host controller will be returned.\r
+\r
+ @retval EFI_SUCCESS The clock was set up successfully\r
+ @retval EFI_UNSUPPORTED The SPI controller was not able to support the\r
+ frequency requested by ClockHz\r
+\r
+**/\r
+typedef EFI_STATUS\r
+(EFIAPI *EFI_SPI_HC_PROTOCOL_CLOCK) (\r
+ IN CONST EFI_SPI_HC_PROTOCOL *This,\r
+ IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral,\r
+ IN UINT32 *ClockHz\r
+ );\r
+\r
+/**\r
+ Perform the SPI transaction on the SPI peripheral using the SPI host\r
+ controller.\r
+\r
+ This routine is called at TPL_NOTIFY.\r
+ This routine synchronously returns EFI_SUCCESS indicating that the\r
+ asynchronous SPI transaction was started. The routine then waits for\r
+ completion of the SPI transaction prior to returning the final transaction\r
+ status.\r
+\r
+ @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure.\r
+ @param[in] BusTransaction Pointer to a EFI_SPI_BUS_ TRANSACTION containing\r
+ the description of the SPI transaction to perform.\r
+\r
+ @retval EFI_SUCCESS The transaction completed successfully\r
+ @retval EFI_BAD_BUFFER_SIZE The BusTransaction->WriteBytes value is invalid,\r
+ or the BusTransaction->ReadinBytes value is\r
+ invalid\r
+ @retval EFI_UNSUPPORTED The BusTransaction-> Transaction Type is\r
+ unsupported\r
+\r
+**/\r
+typedef EFI_STATUS\r
+(EFIAPI *EFI_SPI_HC_PROTOCOL_TRANSACTION) (\r
+ IN CONST EFI_SPI_HC_PROTOCOL *This,\r
+ IN EFI_SPI_BUS_TRANSACTION *BusTransaction\r
+ );\r
+\r
+///\r
+/// Support a SPI data transaction between the SPI controller and a SPI chip.\r
+///\r
+struct _EFI_SPI_HC_PROTOCOL {\r
+ ///\r
+ /// Host control attributes, may have zero or more of the following set:\r
+ /// * HC_SUPPORTS_WRITE_ONLY_OPERATIONS\r
+ /// * HC_SUPPORTS_READ_ONLY_OPERATIONS\r
+ /// * HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS\r
+ /// * HC_TX_FRAME_IN_MOST_SIGNIFICANT_BITS\r
+ /// - The SPI host controller requires the transmit frame to be in most\r
+ /// significant bits instead of least significant bits.The host driver\r
+ /// will adjust the frames if necessary.\r
+ /// * HC_RX_FRAME_IN_MOST_SIGNIFICANT_BITS\r
+ /// - The SPI host controller places the receive frame to be in most\r
+ /// significant bits instead of least significant bits.The host driver\r
+ /// will adjust the frames to be in the least significant bits if\r
+ /// necessary.\r
+ /// * HC_SUPPORTS_2_BIT_DATA_BUS_W1DTH\r
+ /// - The SPI controller supports a 2 - bit data bus\r
+ /// * HC_SUPPORTS_4_B1T_DATA_BUS_WIDTH\r
+ /// - The SPI controller supports a 4 - bit data bus\r
+ /// * HC_TRANSFER_SIZE_INCLUDES_OPCODE\r
+ /// - Transfer size includes the opcode byte\r
+ /// * HC_TRANSFER_SIZE_INCLUDES_ADDRESS\r
+ /// - Transfer size includes the 3 address bytes\r
+ /// The SPI host controller must support full - duplex (receive while\r
+ /// sending) operation.The SPI host controller must support a 1 - bit bus\r
+ /// width.\r
+ ///\r
+ UINT32 Attributes;\r
+\r
+ ///\r
+ /// Mask of frame sizes which the SPI host controller supports. Frame size of\r
+ /// N-bits is supported when bit N-1 is set. The host controller must support\r
+ /// a frame size of 8-bits.\r
+ ///\r
+ UINT32 FrameSizeSupportMask;\r
+\r
+ ///\r
+ /// Maximum transfer size in bytes: 1 - Oxffffffff\r
+ ///\r
+ UINT32 MaximumTransferBytes;\r
+\r
+ ///\r
+ /// Assert or deassert the SPI chip select.\r
+ ///\r
+ EFI_SPI_HC_PROTOCOL_CHIP_SELECT ChipSelect;\r
+\r
+ ///\r
+ /// Set up the clock generator to produce the correct clock frequency, phase\r
+ /// and polarity for a SPI chip.\r
+ ///\r
+ EFI_SPI_HC_PROTOCOL_CLOCK Clock;\r
+\r
+ ///\r
+ /// Perform the SPI transaction on the SPI peripheral using the SPI host\r
+ /// controller.\r
+ ///\r
+ EFI_SPI_HC_PROTOCOL_TRANSACTION Transaction;\r
+};\r
+\r
+extern EFI_GUID gEfiSpiHcProtocolGuid;\r
+\r
+#endif // __SPI_HC_PROTOCOL_H__\r
--- /dev/null
+/** @file\r
+ This file defines the SPI I/O Protocol.\r
+\r
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD\r
+ License which accompanies this distribution. The full text of the license may\r
+ be found at http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ This Protocol was introduced in UEFI PI Specification 1.6.\r
+\r
+**/\r
+\r
+#ifndef __SPI_IO_PROTOCOL_H__\r
+#define __SPI_IO_PROTOCOL_H__\r
+\r
+#include <Protocol/LegacySpiController.h>\r
+#include <Protocol/SpiConfiguration.h>\r
+\r
+typedef struct _EFI_SPI_IO_PROTOCOL EFI_SPI_IO_PROTOCOL;\r
+\r
+///\r
+/// Note: The UEFI PI 1.6 specification does not specify values for the\r
+/// members below. The order matches the specification.\r
+///\r
+typedef enum {\r
+ ///\r
+ /// Data flowing in both direction between the host and\r
+ /// SPI peripheral.ReadBytes must equal WriteBytes and both ReadBuffer and\r
+ /// WriteBuffer must be provided.\r
+ ///\r
+ SPI_TRANSACTION_FULL_DUPLEX,\r
+\r
+ ///\r
+ /// Data flowing from the host to the SPI peripheral.ReadBytes must be\r
+ /// zero.WriteBytes must be non - zero and WriteBuffer must be provided.\r
+ ///\r
+ SPI_TRANSACTION_WRITE_ONLY,\r
+\r
+ ///\r
+ /// Data flowing from the SPI peripheral to the host.WriteBytes must be\r
+ /// zero.ReadBytes must be non - zero and ReadBuffer must be provided.\r
+ ///\r
+ SPI_TRANSACTION_READ_ONLY,\r
+\r
+ ///\r
+ /// Data first flowing from the host to the SPI peripheral and then data\r
+ /// flows from the SPI peripheral to the host.These types of operations get\r
+ /// used for SPI flash devices when control data (opcode, address) must be\r
+ /// passed to the SPI peripheral to specify the data to be read.\r
+ ///\r
+ SPI_TRANSACTION_WRITE_THEN_READ\r
+} EFI_SPI_TRANSACTION_TYPE;\r
+\r
+/**\r
+ Initiate a SPI transaction between the host and a SPI peripheral.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ This routine works with the SPI bus layer to pass the SPI transaction to the\r
+ SPI controller for execution on the SPI bus. There are four types of\r
+ supported transactions supported by this routine:\r
+ * Full Duplex: WriteBuffer and ReadBuffer are the same size.\r
+ * Write Only: WriteBuffer contains data for SPI peripheral, ReadBytes = 0\r
+ * Read Only: ReadBuffer to receive data from SPI peripheral, WriteBytes = 0\r
+ * Write Then Read: WriteBuffer contains control data to write to SPI\r
+ peripheral before data is placed into the ReadBuffer.\r
+ Both WriteBytes and ReadBytes must be non-zero.\r
+\r
+ @param[in] This Pointer to an EFI_SPI_IO_PROTOCOL structure.\r
+ @param[in] TransactionType Type of SPI transaction.\r
+ @param[in] DebugTransaction Set TRUE only when debugging is desired.\r
+ Debugging may be turned on for a single SPI\r
+ transaction. Only this transaction will display\r
+ debugging messages. All other transactions with\r
+ this value set to FALSE will not display any\r
+ debugging messages.\r
+ @param[in] ClockHz Specify the ClockHz value as zero (0) to use\r
+ the maximum clock frequency supported by the\r
+ SPI controller and part. Specify a non-zero\r
+ value only when a specific SPI transaction\r
+ requires a reduced clock rate.\r
+ @param[in] BusWidth Width of the SPI bus in bits: 1, 2, 4\r
+ @param[in] FrameSize Frame size in bits, range: 1 - 32\r
+ @param[in] WriteBytes The length of the WriteBuffer in bytes.\r
+ Specify zero for read-only operations.\r
+ @param[in] WriteBuffer The buffer containing data to be sent from the\r
+ host to the SPI chip. Specify NULL for read\r
+ only operations.\r
+ * Frame sizes 1-8 bits: UINT8 (one byte) per\r
+ frame\r
+ * Frame sizes 7-16 bits: UINT16 (two bytes) per\r
+ frame\r
+ * Frame sizes 17-32 bits: UINT32 (four bytes)\r
+ per frame The transmit frame is in the least\r
+ significant N bits.\r
+ @param[in] ReadBytes The length of the ReadBuffer in bytes.\r
+ Specify zero for write-only operations.\r
+ @param[out] ReadBuffer The buffer to receeive data from the SPI chip\r
+ during the transaction. Specify NULL for write\r
+ only operations.\r
+ * Frame sizes 1-8 bits: UINT8 (one byte) per\r
+ frame\r
+ * Frame sizes 7-16 bits: UINT16 (two bytes) per\r
+ frame\r
+ * Frame sizes 17-32 bits: UINT32 (four bytes)\r
+ per frame The received frame is in the least\r
+ significant N bits.\r
+\r
+ @retval EFI_SUCCESS The SPI transaction completed successfully\r
+ @retval EFI_BAD_BUFFER_SIZE The writeBytes value was invalid\r
+ @retval EFI_BAD_BUFFER_SIZE The ReadBytes value was invalid\r
+ @retval EFI_INVALID_PARAMETER TransactionType is not valid,\r
+ or BusWidth not supported by SPI peripheral or\r
+ SPI host controller,\r
+ or WriteBytes non-zero and WriteBuffer is\r
+ NULL,\r
+ or ReadBytes non-zero and ReadBuffer is NULL,\r
+ or ReadBuffer != WriteBuffer for full-duplex\r
+ type,\r
+ or WriteBuffer was NULL,\r
+ or TPL is too high\r
+ @retval EFI_OUT_OF_RESOURCES Insufficient memory for SPI transaction\r
+ @retval EFI_UNSUPPORTED The FrameSize is not supported by the SPI bus\r
+ layer or the SPI host controller\r
+ @retval EFI_UNSUPPORTED The SPI controller was not able to support\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPI_IO_PROTOCOL_TRANSACTION) (\r
+ IN CONST EFI_SPI_IO_PROTOCOL *This,\r
+ IN EFI_SPI_TRANSACTION_TYPE TransactionType,\r
+ IN BOOLEAN DebugTransaction,\r
+ IN UINT32 ClockHz OPTIONAL,\r
+ IN UINT32 BusWidth,\r
+ IN UINT32 FrameSize,\r
+ IN UINT32 WriteBytes,\r
+ IN UINT8 *WriteBuffer,\r
+ IN UINT32 ReadBytes,\r
+ OUT UINT8 *ReadBuffer\r
+ );\r
+\r
+/**\r
+ Update the SPI peripheral associated with this SPI 10 instance.\r
+\r
+ Support socketed SPI parts by allowing the SPI peripheral driver to replace\r
+ the SPI peripheral after the connection is made. An example use is socketed\r
+ SPI NOR flash parts, where the size and parameters change depending upon\r
+ device is in the socket.\r
+\r
+ @param[in] This Pointer to an EFI_SPI_IO_PROTOCOL structure.\r
+ @param[in] SpiPeripheral Pointer to an EFI_SPI_PERIPHERAL structure.\r
+\r
+ @retval EFI_SUCCESS The SPI peripheral was updated successfully\r
+ @retval EFI_INVALID_PARAMETER The SpiPeripheral value is NULL,\r
+ or the SpiPeripheral->SpiBus is NULL,\r
+ or the SpiP eripheral - >SpiBus pointing at\r
+ wrong bus,\r
+ or the SpiP eripheral - >SpiPart is NULL\r
+\r
+**/\r
+typedef EFI_STATUS\r
+(EFIAPI *EFI_SPI_IO_PROTOCOL_UPDATE_SPI_PERIPHERAL) (\r
+ IN CONST EFI_SPI_IO_PROTOCOL *This,\r
+ IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral\r
+ );\r
+\r
+///\r
+/// The EFI_SPI_BUS_ TRANSACTION data structure contains the description of the\r
+/// SPI transaction to perform on the host controller.\r
+///\r
+typedef struct _EFI_SPI_BUS_TRANSACTION {\r
+ ///\r
+ /// Pointer to the SPI peripheral being manipulated.\r
+ ///\r
+ CONST EFI_SPI_PERIPHERAL *SpiPeripheral;\r
+\r
+ ///\r
+ /// Type of transaction specified by one of the EFI_SPI_TRANSACTION_TYPE\r
+ /// values.\r
+ ///\r
+ EFI_SPI_TRANSACTION_TYPE TransactionType;\r
+\r
+ ///\r
+ /// TRUE if the transaction is being debugged. Debugging may be turned on for\r
+ /// a single SPI transaction. Only this transaction will display debugging\r
+ /// messages. All other transactions with this value set to FALSE will not\r
+ /// display any debugging messages.\r
+ ///\r
+ BOOLEAN DebugTransaction;\r
+\r
+ ///\r
+ /// SPI bus width in bits: 1, 2, 4\r
+ ///\r
+ UINT32 BusWidth;\r
+\r
+ ///\r
+ /// Frame size in bits, range: 1 - 32\r
+ ///\r
+ UINT32 FrameSize;\r
+\r
+ ///\r
+ /// Length of the write buffer in bytes\r
+ ///\r
+ UINT32 WriteBytes;\r
+\r
+ ///\r
+ /// Buffer containing data to send to the SPI peripheral\r
+ /// Frame sizes 1 - 8 bits: UINT8 (one byte) per frame\r
+ /// Frame sizes 7 - 16 bits : UINT16 (two bytes) per frame\r
+ ///\r
+ UINT8 *WriteBuffer;\r
+\r
+ ///\r
+ /// Length of the read buffer in bytes\r
+ ///\r
+ UINT32 ReadBytes;\r
+\r
+ ///\r
+ /// Buffer to receive the data from the SPI peripheral\r
+ /// * Frame sizes 1 - 8 bits: UINT8 (one byte) per frame\r
+ /// * Frame sizes 7 - 16 bits : UINT16 (two bytes) per frame\r
+ /// * Frame sizes 17 - 32 bits : UINT32 (four bytes) per frame\r
+ ///\r
+ UINT8 *ReadBuffer;\r
+} EFI_SPI_BUS_TRANSACTION;\r
+\r
+///\r
+/// Support managed SPI data transactions between the SPI controller and a SPI\r
+/// chip.\r
+///\r
+struct _EFI_SPI_IO_PROTOCOL {\r
+ ///\r
+ /// Address of an EFI_SPI_PERIPHERAL data structure associated with this\r
+ /// protocol instance.\r
+ ///\r
+ CONST EFI_SPI_PERIPHERAL *SpiPeripheral;\r
+\r
+ ///\r
+ /// Address of the original EFI_SPI_PERIPHERAL data structure associated with\r
+ /// this protocol instance.\r
+ ///\r
+ CONST EFI_SPI_PERIPHERAL *OriginalSpiPeripheral;\r
+\r
+ ///\r
+ /// Mask of frame sizes which the SPI 10 layer supports. Frame size of N-bits\r
+ /// is supported when bit N-1 is set. The host controller must support a\r
+ /// frame size of 8-bits. Frame sizes of 16, 24 and 32-bits are converted to\r
+ /// 8-bit frame sizes by the SPI bus layer if the frame size is not supported\r
+ /// by the SPI host controller.\r
+ ///\r
+ UINT32 FrameSizeSupportMask;\r
+\r
+ ///\r
+ /// Maximum transfer size in bytes: 1 - Oxffffffff\r
+ ///\r
+ UINT32 MaximumTransferBytes;\r
+\r
+ ///\r
+ /// Transaction attributes: One or more from:\r
+ /// * SPI_10_SUPPORTS_2_B1T_DATA_BUS_W1DTH\r
+ /// - The SPI host and peripheral supports a 2-bit data bus\r
+ /// * SPI_IO_SUPPORTS_4_BIT_DATA_BUS_W1DTH\r
+ /// - The SPI host and peripheral supports a 4-bit data bus\r
+ /// * SPI_IO_TRANSFER_SIZE_INCLUDES_OPCODE\r
+ /// - Transfer size includes the opcode byte\r
+ /// * SPI_IO_TRANSFER_SIZE_INCLUDES_ADDRESS\r
+ /// - Transfer size includes the 3 address bytes\r
+ ///\r
+ UINT32 Attributes;\r
+\r
+ ///\r
+ /// Pointer to legacy SPI controller protocol\r
+ ///\r
+ CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *LegacySpiProtocol;\r
+\r
+ ///\r
+ /// Initiate a SPI transaction between the host and a SPI peripheral.\r
+ ///\r
+ EFI_SPI_IO_PROTOCOL_TRANSACTION Transaction;\r
+\r
+ ///\r
+ /// Update the SPI peripheral associated with this SPI 10 instance.\r
+ ///\r
+ EFI_SPI_IO_PROTOCOL_UPDATE_SPI_PERIPHERAL UpdateSpiPeripheral;\r
+};\r
+\r
+#endif // __SPI_IO_PROTOCOL_H__\r
--- /dev/null
+/** @file\r
+ This file defines the SPI NOR Flash Protocol.\r
+\r
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD\r
+ License which accompanies this distribution. The full text of the license may\r
+ be found at http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ This Protocol was introduced in UEFI PI Specification 1.6.\r
+\r
+**/\r
+\r
+#ifndef __SPI_NOR_FLASH_PROTOCOL_H__\r
+#define __SPI_NOR_FLASH_PROTOCOL_H__\r
+\r
+#include <Protocol/SpiConfiguration.h>\r
+\r
+///\r
+/// Global ID for the SPI NOR Flash Protocol\r
+///\r
+#define EFI_SPI_NOR_FLASH_PROTOCOL_GUID \\r
+ { 0xb57ec3fe, 0xf833, 0x4ba6, \\r
+ { 0x85, 0x78, 0x2a, 0x7d, 0x6a, 0x87, 0x44, 0x4b }}\r
+\r
+typedef struct _EFI_SPI_NOR_FLASH_PROTOCOL EFI_SPI_NOR_FLASH_PROTOCOL;\r
+\r
+/**\r
+ Read the 3 byte manufacture and device ID from the SPI flash.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ This routine reads the 3 byte manufacture and device ID from the flash part\r
+ filling the buffer provided.\r
+\r
+ @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data structure.\r
+ @param[out] Buffer Pointer to a 3 byte buffer to receive the manufacture and\r
+ device ID.\r
+\r
+\r
+\r
+ @retval EFI_SUCCESS The manufacture and device ID was read\r
+ successfully.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL\r
+ @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_GET_FLASH_ID) (\r
+ IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This,\r
+ OUT UINT8 *Buffer\r
+ );\r
+\r
+/**\r
+ Read data from the SPI flash.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ This routine reads data from the SPI part in the buffer provided.\r
+\r
+ @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data\r
+ structure.\r
+ @param[in] FlashAddress Address in the flash to start reading\r
+ @param[in] LengthInBytes Read length in bytes\r
+ @param[out] Buffer Address of a buffer to receive the data\r
+\r
+ @retval EFI_SUCCESS The data was read successfully.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL, or\r
+ FlashAddress >= This->FlashSize, or\r
+ LengthInBytes > This->FlashSize - FlashAddress\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA) (\r
+ IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This,\r
+ IN UINT32 FlashAddress,\r
+ IN UINT32 LengthInBytes,\r
+ OUT UINT8 *Buffer\r
+ );\r
+\r
+/**\r
+ Read the flash status register.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ This routine reads the flash part status register.\r
+\r
+ @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data\r
+ structure.\r
+ @param[in] LengthInBytes Number of status bytes to read.\r
+ @param[out] FlashStatus Pointer to a buffer to receive the flash status.\r
+\r
+ @retval EFI_SUCCESS The status register was read successfully.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_READ_STATUS) (\r
+ IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This,\r
+ IN UINT32 LengthInBytes,\r
+ OUT UINT8 *FlashStatus\r
+ );\r
+\r
+/**\r
+ Write the flash status register.\r
+\r
+ This routine must be called at or below TPL_N OTIFY.\r
+ This routine writes the flash part status register.\r
+\r
+ @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data\r
+ structure.\r
+ @param[in] LengthInBytes Number of status bytes to write.\r
+ @param[in] FlashStatus Pointer to a buffer containing the new status.\r
+\r
+ @retval EFI_SUCCESS The status write was successful.\r
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate the write buffer.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_STATUS) (\r
+ IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This,\r
+ IN UINT32 LengthInBytes,\r
+ IN UINT8 *FlashStatus\r
+ );\r
+\r
+/**\r
+ Write data to the SPI flash.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ This routine breaks up the write operation as necessary to write the data to\r
+ the SPI part.\r
+\r
+ @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data\r
+ structure.\r
+ @param[in] FlashAddress Address in the flash to start writing\r
+ @param[in] LengthInBytes Write length in bytes\r
+ @param[in] Buffer Address of a buffer containing the data\r
+\r
+ @retval EFI_SUCCESS The data was written successfully.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL, or\r
+ FlashAddress >= This->FlashSize, or\r
+ LengthInBytes > This->FlashSize - FlashAddress\r
+ @retval EFI_OUT_OF_RESOURCES Insufficient memory to copy buffer.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_DATA) (\r
+ IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This,\r
+ IN UINT32 FlashAddress,\r
+ IN UINT32 LengthInBytes,\r
+ IN UINT8 *Buffer\r
+ );\r
+\r
+/**\r
+ Efficiently erases one or more 4KiB regions in the SPI flash.\r
+\r
+ This routine must be called at or below TPL_NOTIFY.\r
+ This routine uses a combination of 4 KiB and larger blocks to erase the\r
+ specified area.\r
+\r
+ @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data\r
+ structure.\r
+ @param[in] FlashAddress Address within a 4 KiB block to start erasing\r
+ @param[in] BlockCount Number of 4 KiB blocks to erase\r
+\r
+ @retval EFI_SUCCESS The erase was completed successfully.\r
+ @retval EFI_INVALID_PARAMETER FlashAddress >= This->FlashSize, or\r
+ BlockCount * 4 KiB\r
+ > This->FlashSize - FlashAddress\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_ERASE) (\r
+ IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This,\r
+ IN UINT32 FlashAddress,\r
+ IN UINT32 BlockCount\r
+ );\r
+\r
+///\r
+/// The EFI_SPI_NOR_FLASH_PROTOCOL exists in the SPI peripheral layer.\r
+/// This protocol manipulates the SPI NOR flash parts using a common set of\r
+/// commands. The board layer provides the interconnection and configuration\r
+/// details for the SPI NOR flash part. The SPI NOR flash driver uses this\r
+/// configuration data to expose a generic interface which provides the\r
+/// following APls:\r
+/// * Read manufacture and device ID\r
+/// * Read data\r
+/// * Read data using low frequency\r
+/// * Read status\r
+/// * Write data\r
+/// * Erase 4 KiB blocks\r
+/// * Erase 32 or 64 KiB blocks\r
+/// * Write status\r
+/// The EFI_SPI_NOR_FLASH_PROTOCOL also exposes some APls to set the security\r
+/// features on the legacy SPI flash controller.\r
+///\r
+struct _EFI_SPI_NOR_FLASH_PROTOCOL {\r
+ ///\r
+ /// Pointer to an EFI_SPI_PERIPHERAL data structure\r
+ ///\r
+ CONST EFI_SPI_PERIPHERAL *SpiPeripheral;\r
+\r
+ ///\r
+ /// Flash size in bytes\r
+ ///\r
+ UINT32 FlashSize;\r
+\r
+ ///\r
+ /// Manufacture and Device ID\r
+ ///\r
+ UINT8 Deviceid[3];\r
+\r
+ ///\r
+ /// Erase block size in bytes\r
+ ///\r
+ UINT32 EraseBlockBytes;\r
+\r
+ ///\r
+ /// Read the 3 byte manufacture and device ID from the SPI flash.\r
+ ///\r
+ EFI_SPI_NOR_FLASH_PROTOCOL_GET_FLASH_ID GetFlashid;\r
+\r
+ ///\r
+ /// Read data from the SPI flash.\r
+ ///\r
+ EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA ReadData;\r
+\r
+ ///\r
+ /// Low frequency read data from the SPI flash.\r
+ ///\r
+ EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA LfReadData;\r
+\r
+ ///\r
+ /// Read the flash status register.\r
+ ///\r
+ EFI_SPI_NOR_FLASH_PROTOCOL_READ_STATUS ReadStatus;\r
+\r
+ ///\r
+ /// Write the flash status register.\r
+ ///\r
+ EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_STATUS WriteStatus;\r
+\r
+ ///\r
+ /// Write data to the SPI flash.\r
+ ///\r
+ EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_DATA WriteData;\r
+\r
+ ///\r
+ /// Efficiently erases one or more 4KiB regions in the SPI flash.\r
+ ///\r
+ EFI_SPI_NOR_FLASH_PROTOCOL_ERASE Erase;\r
+};\r
+\r
+extern EFI_GUID gEfiSpiNorFlashProtocolGuid;\r
+\r
+#endif // __SPI_NOR_FLASH_PROTOCOL_H__\r
--- /dev/null
+/** @file\r
+ This file defines the SPI SMM Configuration Protocol.\r
+\r
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD\r
+ License which accompanies this distribution. The full text of the license may\r
+ be found at http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ This Protocol was introduced in UEFI PI Specification 1.6.\r
+\r
+**/\r
+\r
+#ifndef __SPI_SMM_CONFIGURATION_PROTOCOL_H__\r
+#define __SPI_SMM_CONFIGURATION_PROTOCOL_H__\r
+\r
+#include <Protocol/SpiConfiguration.h>\r
+\r
+///\r
+/// Global ID for the SPI SMM Configuration Protocol\r
+///\r
+#define EFI_SPI_SMM_CONFIGURATION_PROTOCOL_GUID \\r
+ { 0x995c6eca, 0x171b, 0x45fd, \\r
+ { 0xa3, 0xaa, 0xfd, 0x4c, 0x9c, 0x9d, 0xef, 0x59 }}\r
+\r
+typedef\r
+struct _EFI_SPI_CONFIGURATION_PROTOCOL\r
+EFI_SPI_SMM_CONFIGURATION_PROTOCOL;\r
+\r
+extern EFI_GUID gEfiSpiSmmConfigurationProtocolGuid;\r
+\r
+#endif // __SPI_SMM_CONFIGURATION_H__\r
--- /dev/null
+/** @file\r
+ This file defines the SPI SMM Host Controller Protocol.\r
+\r
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD\r
+ License which accompanies this distribution. The full text of the license may\r
+ be found at http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ This Protocol was introduced in UEFI PI Specification 1.6.\r
+\r
+**/\r
+\r
+#ifndef __SPI_SMM_HC_H__\r
+#define __SPI_SMM_HC_H__\r
+\r
+#include <Protocol/SpiHc.h>\r
+\r
+///\r
+/// Global ID for the SPI SMM Host Controller Protocol\r
+///\r
+#define EFI_SPI_SMM_HC_PROTOCOL_GUID \\r
+ { 0xe9f02217, 0x2093, 0x4470, \\r
+ { 0x8a, 0x54, 0x5c, 0x2c, 0xff, 0xe7, 0x3e, 0xcb }}\r
+\r
+typedef\r
+struct _EFI_SPI_HC_PROTOCOL\r
+EFI_SPI_SMM_HC_PROTOCOL;\r
+\r
+extern EFI_GUID gEfiSpiSmmHcProtocolGuid;\r
+\r
+#endif // __SPI_SMM_HC_H__\r
--- /dev/null
+/** @file\r
+ This file defines the SPI SMM NOR Flash Protocol.\r
+\r
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD\r
+ License which accompanies this distribution. The full text of the license may\r
+ be found at http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ This Protocol was introduced in UEFI PI Specification 1.6.\r
+\r
+**/\r
+\r
+#ifndef __SPI_SMM_NOR_FLASH_PROTOCOL_H__\r
+#define __SPI_SMM_NOR_FLASH_PROTOCOL_H__\r
+\r
+#include <Protocol/SpiNorFlash.h>\r
+\r
+///\r
+/// Global ID for the SPI SMM NOR Flash Protocol\r
+///\r
+#define EFI_SPI_SMM_NOR_FLASH_PROTOCOL_GUID \\r
+ { 0xaab18f19, 0xfe14, 0x4666, \\r
+ { 0x86, 0x04, 0x87, 0xff, 0x6d, 0x66, 0x2c, 0x9a } }\r
+\r
+typedef\r
+struct _EFI_SPI_NOR_FLASH_PROTOCOL\r
+EFI_SPI_SMM_NOR_FLASH_PROTOCOL;\r
+\r
+extern EFI_GUID gEfiSpiSmmNorFlashProtocolGuid;\r
+\r
+#endif // __SPI_SMM_NOR_FLASH_PROTOCOL_H__\r
## Include/Protocol/MmCommunication.h\r
gEfiMmCommunicationProtocolGuid = { 0xc68ed8e2, 0x9dc6, 0x4cbd, { 0x9d, 0x94, 0xdb, 0x65, 0xac, 0xc5, 0xc3, 0x32 }}\r
\r
+ #\r
+ # Protocols defined in PI 1.6.\r
+ #\r
+\r
+ ## Include/Protocol/LegacySpiController.h\r
+ gEfiLegacySpiControllerProtocolGuid = { 0x39136fc7, 0x1a11, 0x49de, { 0xbf, 0x35, 0x0e, 0x78, 0xdd, 0xb5, 0x24, 0xfc }}\r
+\r
+ ## Include/Protocol/LegacySpiFlash.h\r
+ gEfiLegacySpiFlashProtocolGuid = { 0xf01bed57, 0x04bc, 0x4f3f, { 0x96, 0x60, 0xd6, 0xf2, 0xea, 0x22, 0x82, 0x59 }}\r
+\r
+ ## Include/Protocol/LegacySpiSmmController.h\r
+ gEfiLegacySpiSmmControllerProtocolGuid = { 0x62331b78, 0xd8d0, 0x4c8c, { 0x8c, 0xcb, 0xd2, 0x7d, 0xfe, 0x32, 0xdb, 0x9b }}\r
+\r
+ ## Include/Protocol/LegacySpiSmmFlash.h\r
+ gEfiLegacySpiSmmFlashProtocolGuid = { 0x5e3848d4, 0x0db5, 0x4fc0, { 0x97, 0x29, 0x3f, 0x35, 0x3d, 0x4f, 0x87, 0x9f }}\r
+\r
+ ## Include/Protocol/SpiConfiguration.h\r
+ gEfiSpiConfigurationProtocolGuid = { 0x85a6d3e6, 0xb65b, 0x4afc, { 0xb3, 0x8f, 0xc6, 0xd5, 0x4a, 0xf6, 0xdd, 0xc8 }}\r
+\r
+ ## Include/Protocol/SpiHc.h\r
+ gEfiSpiHcProtocolGuid = { 0xc74e5db2, 0xfa96, 0x4ae2, { 0xb3, 0x99, 0x15, 0x97, 0x7f, 0xe3, 0x0, 0x2d }}\r
+\r
+ ## Include/Protocol/SpiNorFlash.h\r
+ gEfiSpiNorFlashProtocolGuid = { 0xb57ec3fe, 0xf833, 0x4ba6, { 0x85, 0x78, 0x2a, 0x7d, 0x6a, 0x87, 0x44, 0x4b }}\r
+\r
+ ## Include/Protocol/SpiSmmConfiguration.h\r
+ gEfiSpiSmmConfigurationProtocolGuid = { 0x995c6eca, 0x171b, 0x45fd, { 0xa3, 0xaa, 0xfd, 0x4c, 0x9c, 0x9d, 0xef, 0x59 }}\r
+\r
+ ## Include/Protocol/SpiSmmHc.h\r
+ gEfiSpiSmmHcProtocolGuid = { 0xe9f02217, 0x2093, 0x4470, { 0x8a, 0x54, 0x5c, 0x2c, 0xff, 0xe7, 0x3e, 0xcb }}\r
+\r
+ ## Include/Protocol/SpiSmmNorFlash.h\r
+ gEfiSpiSmmNorFlashProtocolGuid = { 0xaab18f19, 0xfe14, 0x4666, { 0x86, 0x04, 0x87, 0xff, 0x6d, 0x66, 0x2c, 0x9a }}\r
+\r
#\r
# Protocols defined in UEFI2.1/UEFI2.0/EFI1.1\r
#\r