MdePkg/Baseib: Filter/trace MSR access for IA32/X64

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Acked-by: Ard Biesheuvel <ardb@kernel.org>

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index fe8f68bbcfcf7ca9659acd5623496030f48486bc..b76f3af380ea2ae779c799b3ef3083b2555a99ff 100644 (file)
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -413,6 +413,9 @@
   DebugLib\r
   BaseMemoryLib\r
 \r
+[LibraryClasses.X64, LibraryClasses.IA32]\r
+  RegisterFilterLib\r
+\r
 [Pcd]\r
   gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength      ## SOMETIMES_CONSUMES\r
   gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength     ## SOMETIMES_CONSUMES\r

diff --git a/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c b/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c
index 30aa63243be8d29742c241b81f1800e935b76f06..40e8c08beb31c1e944107e82e3866d6a16999e38 100644 (file)
--- a/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c
+++ b/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c
@@ -2,7 +2,7 @@
   GCC inline implementation of BaseLib processor specific functions that use\r
   privlidged instructions.\r
 \r
-  Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
   Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
@@ -10,6 +10,7 @@
 \r
 \r
 #include "BaseLibInternals.h"\r
+#include <Library/RegisterFilterLib.h>\r
 \r
 /**\r
   Enables CPU interrupts.\r
@@ -63,12 +64,17 @@ AsmReadMsr64 (
   )\r
 {\r
   UINT64 Data;\r
-\r
-  __asm__ __volatile__ (\r
-    "rdmsr"\r
-    : "=A" (Data)   // %0\r
-    : "c"  (Index)  // %1\r
-    );\r
+  BOOLEAN Flag;\r
+\r
+  Flag = FilterBeforeMsrRead (Index, &Data);\r
+  if (Flag) {\r
+    __asm__ __volatile__ (\r
+      "rdmsr"\r
+      : "=A" (Data)   // %0\r
+      : "c"  (Index)  // %1\r
+      );\r
+  }\r
+  FilterAfterMsrRead (Index, &Data);\r
 \r
   return Data;\r
 }\r
@@ -97,12 +103,18 @@ AsmWriteMsr64 (
   IN      UINT64                    Value\r
   )\r
 {\r
-  __asm__ __volatile__ (\r
-    "wrmsr"\r
-    :\r
-    : "c" (Index),\r
-      "A" (Value)\r
-    );\r
+  BOOLEAN  Flag;\r
+\r
+  Flag = FilterBeforeMsrWrite (Index, &Value);\r
+  if (Flag) {\r
+    __asm__ __volatile__ (\r
+      "wrmsr"\r
+      :\r
+      : "c" (Index),\r
+        "A" (Value)\r
+      );\r
+  }\r
+  FilterAfterMsrWrite (Index, &Value);\r
 \r
   return Value;\r
 }\r

diff --git a/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c b/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c
index 6d2394b1a3ef3642dcefe83f0d0082fb75b8fa73..afe3aa5bdc9a7e6be475b48c9edb89925ec7bc38 100644 (file)
--- a/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c
@@ -1,13 +1,13 @@
 /** @file\r
   AsmReadMsr64 function\r
 \r
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
 \r
-\r
+#include <Library/RegisterFilterLib.h>\r
 \r
 /**\r
   Returns a 64-bit Machine Specific Register(MSR).\r
@@ -24,8 +24,7 @@
 \r
 **/\r
 UINT64\r
-EFIAPI\r
-AsmReadMsr64 (\r
+AsmReadMsr64Internal (\r
   IN UINT32  Index\r
   )\r
 {\r
@@ -35,3 +34,34 @@ AsmReadMsr64 (
   }\r
 }\r
 \r
+/**\r
+  Returns a 64-bit Machine Specific Register(MSR).\r
+\r
+  Reads and returns the 64-bit MSR specified by Index. No parameter checking is\r
+  performed on Index, and some Index values may cause CPU exceptions. The\r
+  caller must either guarantee that Index is valid, or the caller must set up\r
+  exception handlers to catch the exceptions. This function is only available\r
+  on IA-32 and x64.\r
+\r
+  @param  Index The 32-bit MSR index to read.\r
+\r
+  @return The value of the MSR identified by Index.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMsr64 (\r
+  IN UINT32  Index\r
+  )\r
+{\r
+  UINT64                            Value;\r
+  BOOLEAN                           Flag;\r
+\r
+  Flag = FilterBeforeMsrRead (Index, &Value);\r
+  if (Flag) {\r
+    Value = AsmReadMsr64Internal (Index);\r
+  }\r
+  FilterAfterMsrRead (Index, &Value);\r
+\r
+  return Value;\r
+}\r

diff --git a/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c b/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c
index badf1d8e5830b3103845e10db949ec4e7a715f38..ba0cf3f74c308229c2809ed29b55f52509344e97 100644 (file)
--- a/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c
@@ -1,13 +1,13 @@
 /** @file\r
   AsmWriteMsr64 function\r
 \r
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
 \r
-\r
+#include <Library/RegisterFilterLib.h>\r
 \r
 /**\r
   Writes a 64-bit value to a Machine Specific Register(MSR), and returns the\r
@@ -33,11 +33,19 @@ AsmWriteMsr64 (
   IN UINT64  Value\r
   )\r
 {\r
-  _asm {\r
-    mov     edx, dword ptr [Value + 4]\r
-    mov     eax, dword ptr [Value + 0]\r
-    mov     ecx, Index\r
-    wrmsr\r
+  BOOLEAN                           Flag;\r
+\r
+  Flag = FilterBeforeMsrWrite (Index, &Value);\r
+  if (Flag) {\r
+    _asm {\r
+      mov     edx, dword ptr [Value + 4]\r
+      mov     eax, dword ptr [Value + 0]\r
+      mov     ecx, Index\r
+      wrmsr\r
+    }\r
   }\r
+  FilterAfterMsrWrite (Index, &Value);\r
+\r
+  return Value;\r
 }\r
 \r

diff --git a/MdePkg/Library/BaseLib/X64/GccInlinePriv.c b/MdePkg/Library/BaseLib/X64/GccInlinePriv.c
index 98be19b3c7b7962fb93f7662f5097a1de3ae9db8..e4920f21165b57a3d45cadf51ae704efa09d081b 100644 (file)
--- a/MdePkg/Library/BaseLib/X64/GccInlinePriv.c
+++ b/MdePkg/Library/BaseLib/X64/GccInlinePriv.c
@@ -2,7 +2,7 @@
   GCC inline implementation of BaseLib processor specific functions that use\r
   privlidged instructions.\r
 \r
-  Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
   Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
@@ -10,6 +10,7 @@
 \r
 \r
 #include "BaseLibInternals.h"\r
+#include <Library/RegisterFilterLib.h>\r
 \r
 /**\r
   Enables CPU interrupts.\r
@@ -64,13 +65,20 @@ AsmReadMsr64 (
 {\r
   UINT32 LowData;\r
   UINT32 HighData;\r
-\r
-  __asm__ __volatile__ (\r
-    "rdmsr"\r
-    : "=a" (LowData),   // %0\r
-      "=d" (HighData)   // %1\r
-    : "c"  (Index)      // %2\r
-    );\r
+  UINT64 Value;\r
+  BOOLEAN Flag;\r
+\r
+  Flag = FilterBeforeMsrRead (Index, &Value);\r
+  if (Flag) {\r
+    __asm__ __volatile__ (\r
+      "rdmsr"\r
+      : "=a" (LowData),   // %0\r
+        "=d" (HighData)   // %1\r
+      : "c"  (Index)      // %2\r
+      );\r
+    Value = (((UINT64)HighData) << 32) | LowData;\r
+  }\r
+  FilterAfterMsrRead (Index, &Value);\r
 \r
   return (((UINT64)HighData) << 32) | LowData;\r
 }\r
@@ -101,17 +109,22 @@ AsmWriteMsr64 (
 {\r
   UINT32 LowData;\r
   UINT32 HighData;\r
+  BOOLEAN Flag;\r
 \r
   LowData  = (UINT32)(Value);\r
   HighData = (UINT32)(Value >> 32);\r
 \r
-  __asm__ __volatile__ (\r
-    "wrmsr"\r
-    :\r
-    : "c" (Index),\r
-      "a" (LowData),\r
-      "d" (HighData)\r
-    );\r
+  Flag = FilterBeforeMsrWrite (Index, &Value);\r
+  if (Flag) {\r
+    __asm__ __volatile__ (\r
+      "wrmsr"\r
+      :\r
+      : "c" (Index),\r
+        "a" (LowData),\r
+        "d" (HighData)\r
+      );\r
+  }\r
+  FilterAfterMsrWrite (Index, &Value);\r
 \r
   return Value;\r
 }\r

diff --git a/MdePkg/Library/BaseLib/X64/ReadMsr64.c b/MdePkg/Library/BaseLib/X64/ReadMsr64.c
index 5ee7ca53f30037bc4fde26fc59dded250244cb9d..36a349432cab26b8bc04fc6996142a9f3fec22eb 100644 (file)
--- a/MdePkg/Library/BaseLib/X64/ReadMsr64.c
+++ b/MdePkg/Library/BaseLib/X64/ReadMsr64.c
@@ -1,7 +1,7 @@
 /** @file\r
   CpuBreakpoint function.\r
 \r
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
@@ -10,6 +10,8 @@
   Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.\r
 **/\r
 \r
+#include <Library/RegisterFilterLib.h>\r
+\r
 unsigned __int64 __readmsr (int register);\r
 \r
 #pragma intrinsic(__readmsr)\r
@@ -28,6 +30,15 @@ AsmReadMsr64 (
   IN UINT32  Index\r
   )\r
 {\r
-  return __readmsr (Index);\r
+  UINT64                            Value;\r
+  BOOLEAN                           Flag;\r
+\r
+  Flag = FilterBeforeMsrRead (Index, &Value);\r
+  if (Flag) {\r
+    Value = __readmsr (Index);\r
+  }\r
+  FilterAfterMsrRead (Index, &Value);\r
+\r
+  return Value;\r
 }\r
 \r

diff --git a/MdePkg/Library/BaseLib/X64/WriteMsr64.c b/MdePkg/Library/BaseLib/X64/WriteMsr64.c
index 98c5458d8abb1fc2df06c810370a02837b3e1ef9..bb030832c497c7358078eec4a28952803754201e 100644 (file)
--- a/MdePkg/Library/BaseLib/X64/WriteMsr64.c
+++ b/MdePkg/Library/BaseLib/X64/WriteMsr64.c
@@ -1,7 +1,7 @@
 /** @file\r
   CpuBreakpoint function.\r
 \r
-  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
@@ -10,6 +10,8 @@
   Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.\r
 **/\r
 \r
+#include <Library/RegisterFilterLib.h>\r
+\r
 void __writemsr (unsigned long Register, unsigned __int64 Value);\r
 \r
 #pragma intrinsic(__writemsr)\r
@@ -30,7 +32,14 @@ AsmWriteMsr64 (
   IN UINT64  Value\r
   )\r
 {\r
-  __writemsr (Index, Value);\r
+  BOOLEAN                           Flag;\r
+\r
+  Flag = FilterBeforeMsrWrite (Index, &Value);\r
+  if (Flag) {\r
+    __writemsr (Index, Value);\r
+  }\r
+  FilterAfterMsrWrite (Index, &Value);\r
+\r
   return Value;\r
 }\r
 \r