Instead of depending on ArmLib to retrieve the CWG directly, use
the DMA buffer alignment exposed by the CPU arch protocol. This
removes our dependency on ArmLib, which makes the library a bit
more architecture independent.
While we're in there, rename gCpu to mCpu to better reflect its
local scope, and reflow some lines that we're modifying anyway.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
#include <Library/UncachedMemoryAllocationLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/UncachedMemoryAllocationLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/BaseMemoryLib.h>\r
-#include <Library/ArmLib.h>\r
\r
#include <Protocol/Cpu.h>\r
\r
\r
#include <Protocol/Cpu.h>\r
\r
-EFI_CPU_ARCH_PROTOCOL *gCpu;\r
-UINTN gCacheAlignment = 0;\r
+STATIC EFI_CPU_ARCH_PROTOCOL *mCpu;\r
\r
/**\r
Provides the DMA controller-specific addresses needed to access system memory.\r
\r
/**\r
Provides the DMA controller-specific addresses needed to access system memory.\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- if ((((UINTN)HostAddress & (gCacheAlignment - 1)) != 0) ||\r
- ((*NumberOfBytes & (gCacheAlignment - 1)) != 0)) {\r
+ if ((((UINTN)HostAddress & (mCpu->DmaBufferAlignment - 1)) != 0) ||\r
+ ((*NumberOfBytes & (mCpu->DmaBufferAlignment - 1)) != 0)) {\r
\r
// Get the cacheability of the region\r
Status = gDS->GetMemorySpaceDescriptor (*DeviceAddress, &GcdDescriptor);\r
\r
// Get the cacheability of the region\r
Status = gDS->GetMemorySpaceDescriptor (*DeviceAddress, &GcdDescriptor);\r
DEBUG_CODE_END ();\r
\r
// Flush the Data Cache (should not have any effect if the memory region is uncached)\r
DEBUG_CODE_END ();\r
\r
// Flush the Data Cache (should not have any effect if the memory region is uncached)\r
- gCpu->FlushDataCache (gCpu, *DeviceAddress, *NumberOfBytes, EfiCpuFlushTypeWriteBackInvalidate);\r
+ mCpu->FlushDataCache (mCpu, *DeviceAddress, *NumberOfBytes,\r
+ EfiCpuFlushTypeWriteBackInvalidate);\r
}\r
\r
Map->HostAddress = (UINTN)HostAddress;\r
}\r
\r
Map->HostAddress = (UINTN)HostAddress;\r
//\r
// Make sure we read buffer from uncached memory and not the cache\r
//\r
//\r
// Make sure we read buffer from uncached memory and not the cache\r
//\r
- gCpu->FlushDataCache (gCpu, Map->HostAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);\r
+ mCpu->FlushDataCache (mCpu, Map->HostAddress, Map->NumberOfBytes,\r
+ EfiCpuFlushTypeInvalidate);\r
EFI_STATUS Status;\r
\r
// Get the Cpu protocol for later use\r
EFI_STATUS Status;\r
\r
// Get the Cpu protocol for later use\r
- Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu);\r
+ Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&mCpu);\r
ASSERT_EFI_ERROR(Status);\r
\r
ASSERT_EFI_ERROR(Status);\r
\r
- gCacheAlignment = ArmCacheWritebackGranule ();\r
-\r
UncachedMemoryAllocationLib\r
IoLib\r
BaseMemoryLib\r
UncachedMemoryAllocationLib\r
IoLib\r
BaseMemoryLib\r
\r
[Protocols]\r
gEfiCpuArchProtocolGuid\r
\r
[Protocols]\r
gEfiCpuArchProtocolGuid\r