--- /dev/null
+ TITLE CpuInterrupt.asm: \r
+;------------------------------------------------------------------------------\r
+;*\r
+;* Copyright 2006, Intel Corporation \r
+;* All rights reserved. This program and the accompanying materials \r
+;* are licensed and made available under the terms and conditions of the BSD License \r
+;* which accompanies this distribution. The full text of the license may be found at \r
+;* http://opensource.org/licenses/bsd-license.php \r
+;* \r
+;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+;* \r
+;* CpuInterrupt.asm\r
+;* \r
+;* Abstract:\r
+;*\r
+;------------------------------------------------------------------------------\r
+\r
+EXTERNDEF mExceptionCodeSize:DWORD\r
+\r
+.code\r
+\r
+EXTERN TimerHandler: FAR\r
+EXTERN ExceptionHandler: NEAR\r
+EXTERN mTimerVector: QWORD\r
+\r
+mExceptionCodeSize DD 9\r
+\r
+InitDescriptor PROC\r
+ lea rax, [GDT_BASE] ; RAX=PHYSICAL address of gdt\r
+ mov qword ptr [gdtr + 2], rax ; Put address of gdt into the gdtr\r
+ lgdt fword ptr [gdtr]\r
+ mov rax, 18h\r
+ mov gs, rax\r
+ mov fs, rax\r
+ lea rax, [IDT_BASE] ; RAX=PHYSICAL address of idt\r
+ mov qword ptr [idtr + 2], rax ; Put address of idt into the idtr\r
+ lidt fword ptr [idtr]\r
+ ret\r
+InitDescriptor ENDP\r
+\r
+; VOID\r
+; InstallInterruptHandler (\r
+; UINTN Vector, // rcx\r
+; void (*Handler)(void) // rdx\r
+; )\r
+InstallInterruptHandler PROC \r
+ push rbx\r
+ pushfq ; save eflags\r
+ cli ; turn off interrupts\r
+ sub rsp, 10h ; open some space on the stack\r
+ mov rbx, rsp\r
+ sidt [rbx] ; get fword address of IDT\r
+ mov rbx, [rbx+2] ; move offset of IDT into RBX\r
+ add rsp, 10h ; correct stack\r
+ mov rax, rcx ; Get vector number\r
+ shl rax, 4 ; multiply by 16 to get offset\r
+ add rbx, rax ; add to IDT base to get entry\r
+ mov rax, rdx ; load new address into IDT entry\r
+ mov word ptr [rbx], ax ; write bits 15..0 of offset\r
+ shr rax, 16 ; use ax to copy 31..16 to descriptors\r
+ mov word ptr [rbx+6], ax ; write bits 31..16 of offset\r
+ shr rax, 16 ; use eax to copy 63..32 to descriptors\r
+ mov dword ptr [rbx+8], eax ; write bits 63..32 of offset\r
+ popfq ; restore flags (possible enabling interrupts)\r
+ pop rbx\r
+ ret\r
+\r
+InstallInterruptHandler ENDP\r
+\r
+JmpCommonIdtEntry macro\r
+ ; jmp commonIdtEntry - this must be hand coded to keep the assembler from\r
+ ; using a 8 bit reletive jump when the entries are\r
+ ; within 255 bytes of the common entry. This must\r
+ ; be done to maintain the consistency of the size\r
+ ; of entry points...\r
+ db 0e9h ; jmp 16 bit reletive \r
+ dd commonIdtEntry - $ - 4 ; offset to jump to\r
+endm\r
+\r
+ align 02h\r
+SystemExceptionHandler PROC\r
+INT0:\r
+ push 0h ; push error code place holder on the stack\r
+ push 0h\r
+ JmpCommonIdtEntry\r
+; db 0e9h ; jmp 16 bit reletive \r
+; dd commonIdtEntry - $ - 4 ; offset to jump to\r
+ \r
+INT1:\r
+ push 0h ; push error code place holder on the stack\r
+ push 1h\r
+ JmpCommonIdtEntry\r
+ \r
+INT2:\r
+ push 0h ; push error code place holder on the stack\r
+ push 2h\r
+ JmpCommonIdtEntry\r
+ \r
+INT3:\r
+ push 0h ; push error code place holder on the stack\r
+ push 3h\r
+ JmpCommonIdtEntry\r
+ \r
+INT4:\r
+ push 0h ; push error code place holder on the stack\r
+ push 4h\r
+ JmpCommonIdtEntry\r
+ \r
+INT5:\r
+ push 0h ; push error code place holder on the stack\r
+ push 5h\r
+ JmpCommonIdtEntry\r
+ \r
+INT6:\r
+ push 0h ; push error code place holder on the stack\r
+ push 6h\r
+ JmpCommonIdtEntry\r
+ \r
+INT7:\r
+ push 0h ; push error code place holder on the stack\r
+ push 7h\r
+ JmpCommonIdtEntry\r
+ \r
+INT8:\r
+; Double fault causes an error code to be pushed so no phony push necessary\r
+ nop\r
+ nop\r
+ push 8h\r
+ JmpCommonIdtEntry\r
+ \r
+INT9:\r
+ push 0h ; push error code place holder on the stack\r
+ push 9h\r
+ JmpCommonIdtEntry\r
+ \r
+INT10:\r
+; Invalid TSS causes an error code to be pushed so no phony push necessary\r
+ nop\r
+ nop\r
+ push 10\r
+ JmpCommonIdtEntry\r
+ \r
+INT11:\r
+; Segment Not Present causes an error code to be pushed so no phony push necessary\r
+ nop\r
+ nop\r
+ push 11\r
+ JmpCommonIdtEntry\r
+ \r
+INT12:\r
+; Stack fault causes an error code to be pushed so no phony push necessary\r
+ nop\r
+ nop\r
+ push 12\r
+ JmpCommonIdtEntry\r
+ \r
+INT13:\r
+; GP fault causes an error code to be pushed so no phony push necessary\r
+ nop\r
+ nop\r
+ push 13\r
+ JmpCommonIdtEntry\r
+ \r
+INT14:\r
+; Page fault causes an error code to be pushed so no phony push necessary\r
+ nop\r
+ nop\r
+ push 14\r
+ JmpCommonIdtEntry\r
+ \r
+INT15:\r
+ push 0h ; push error code place holder on the stack\r
+ push 15\r
+ JmpCommonIdtEntry\r
+ \r
+INT16:\r
+ push 0h ; push error code place holder on the stack\r
+ push 16\r
+ JmpCommonIdtEntry\r
+ \r
+INT17:\r
+; Alignment check causes an error code to be pushed so no phony push necessary\r
+ nop\r
+ nop\r
+ push 17\r
+ JmpCommonIdtEntry\r
+ \r
+INT18:\r
+ push 0h ; push error code place holder on the stack\r
+ push 18\r
+ JmpCommonIdtEntry\r
+ \r
+INT19:\r
+ push 0h ; push error code place holder on the stack\r
+ push 19\r
+ JmpCommonIdtEntry\r
+\r
+INTUnknown:\r
+REPEAT (32 - 20)\r
+ push 0h ; push error code place holder on the stack\r
+; push xxh ; push vector number\r
+ db 06ah\r
+ db ( $ - INTUnknown - 3 ) / 9 + 20 ; vector number\r
+ JmpCommonIdtEntry\r
+ENDM\r
+SystemExceptionHandler ENDP\r
+\r
+SystemTimerHandler PROC\r
+ push 0\r
+ push mTimerVector\r
+ JmpCommonIdtEntry\r
+SystemTimerHandler ENDP\r
+\r
+commonIdtEntry:\r
+; +---------------------+ <-- 16-byte aligned ensured by processor\r
+; + Old SS +\r
+; +---------------------+\r
+; + Old RSP +\r
+; +---------------------+\r
+; + RFlags +\r
+; +---------------------+\r
+; + CS +\r
+; +---------------------+\r
+; + RIP +\r
+; +---------------------+\r
+; + Error Code +\r
+; +---------------------+\r
+; + Vector Number +\r
+; +---------------------+\r
+; + RBP +\r
+; +---------------------+ <-- RBP, 16-byte aligned\r
+\r
+ cli\r
+ push rbp\r
+ mov rbp, rsp\r
+\r
+ ;\r
+ ; Since here the stack pointer is 16-byte aligned, so\r
+ ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64\r
+ ; is 16-byte aligned\r
+ ; \r
+\r
+;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;\r
+;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;\r
+ push r15\r
+ push r14\r
+ push r13\r
+ push r12\r
+ push r11\r
+ push r10\r
+ push r9\r
+ push r8\r
+ push rax\r
+ push rcx\r
+ push rdx\r
+ push rbx\r
+ push qword ptr [rbp + 6 * 8] ; RSP\r
+ push qword ptr [rbp] ; RBP\r
+ push rsi\r
+ push rdi\r
+\r
+;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero\r
+ movzx rax, word ptr [rbp + 7 * 8]\r
+ push rax ; for ss\r
+ movzx rax, word ptr [rbp + 4 * 8]\r
+ push rax ; for cs\r
+ mov rax, ds\r
+ push rax\r
+ mov rax, es\r
+ push rax\r
+ mov rax, fs\r
+ push rax\r
+ mov rax, gs\r
+ push rax\r
+\r
+;; UINT64 Rip;\r
+ push qword ptr [rbp + 3 * 8]\r
+\r
+;; UINT64 Gdtr[2], Idtr[2];\r
+ sub rsp, 16\r
+ sidt fword ptr [rsp]\r
+ sub rsp, 16\r
+ sgdt fword ptr [rsp]\r
+\r
+;; UINT64 Ldtr, Tr;\r
+ xor rax, rax\r
+ str ax\r
+ push rax\r
+ sldt ax\r
+ push rax\r
+\r
+;; UINT64 RFlags;\r
+ push qword ptr [rbp + 5 * 8]\r
+\r
+;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;\r
+ mov rax, cr8\r
+ push rax\r
+ mov rax, cr4\r
+ or rax, 208h\r
+ mov cr4, rax\r
+ push rax\r
+ mov rax, cr3\r
+ push rax\r
+ mov rax, cr2\r
+ push rax\r
+ xor rax, rax\r
+ push rax\r
+ mov rax, cr0\r
+ push rax\r
+\r
+;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
+ mov rax, dr7\r
+ push rax\r
+;; clear Dr7 while executing debugger itself\r
+ xor rax, rax\r
+ mov dr7, rax\r
+\r
+ mov rax, dr6\r
+ push rax\r
+;; insure all status bits in dr6 are clear...\r
+ xor rax, rax\r
+ mov dr6, rax\r
+\r
+ mov rax, dr3\r
+ push rax\r
+ mov rax, dr2\r
+ push rax\r
+ mov rax, dr1\r
+ push rax\r
+ mov rax, dr0\r
+ push rax\r
+\r
+;; FX_SAVE_STATE_X64 FxSaveState;\r
+\r
+ sub rsp, 512\r
+ mov rdi, rsp\r
+ db 0fh, 0aeh, 00000111y ;fxsave [rdi]\r
+\r
+;; UINT32 ExceptionData;\r
+ push qword ptr [rbp + 2 * 8]\r
+\r
+;; call into exception handler\r
+;; Prepare parameter and call\r
+ mov rcx, qword ptr [rbp + 1 * 8]\r
+ mov rdx, rsp\r
+ ;\r
+ ; Per X64 calling convention, allocate maximum parameter stack space\r
+ ; and make sure RSP is 16-byte aligned\r
+ ;\r
+ sub rsp, 4 * 8 + 8\r
+ cmp rcx, 32\r
+ jb CallException\r
+ call TimerHandler\r
+ jmp ExceptionDone\r
+CallException:\r
+ call ExceptionHandler\r
+ExceptionDone:\r
+ add rsp, 4 * 8 + 8\r
+\r
+ cli\r
+;; UINT64 ExceptionData;\r
+ add rsp, 8\r
+\r
+;; FX_SAVE_STATE_X64 FxSaveState;\r
+\r
+ mov rsi, rsp\r
+ db 0fh, 0aeh, 00001110y ; fxrstor [rsi]\r
+ add rsp, 512\r
+\r
+;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
+ pop rax\r
+ mov dr0, rax\r
+ pop rax\r
+ mov dr1, rax\r
+ pop rax\r
+ mov dr2, rax\r
+ pop rax\r
+ mov dr3, rax\r
+;; skip restore of dr6. We cleared dr6 during the context save.\r
+ add rsp, 8\r
+ pop rax\r
+ mov dr7, rax\r
+\r
+;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;\r
+ pop rax\r
+ mov cr0, rax\r
+ add rsp, 8 ; not for Cr1\r
+ pop rax\r
+ mov cr2, rax\r
+ pop rax\r
+ mov cr3, rax\r
+ pop rax\r
+ mov cr4, rax\r
+ pop rax\r
+ mov cr8, rax\r
+\r
+;; UINT64 RFlags;\r
+ pop qword ptr [rbp + 5 * 8]\r
+\r
+;; UINT64 Ldtr, Tr;\r
+;; UINT64 Gdtr[2], Idtr[2];\r
+;; Best not let anyone mess with these particular registers...\r
+ add rsp, 48\r
+\r
+;; UINT64 Rip;\r
+ pop qword ptr [rbp + 3 * 8]\r
+\r
+;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;\r
+ pop rax\r
+ ; mov gs, rax ; not for gs\r
+ pop rax\r
+ ; mov fs, rax ; not for fs\r
+ ; (X64 will not use fs and gs, so we do not restore it)\r
+ pop rax\r
+ mov es, rax\r
+ pop rax\r
+ mov ds, rax\r
+ pop qword ptr [rbp + 4 * 8] ; for cs\r
+ pop qword ptr [rbp + 7 * 8] ; for ss\r
+\r
+;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;\r
+;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;\r
+ pop rdi\r
+ pop rsi\r
+ add rsp, 8 ; not for rbp\r
+ pop qword ptr [rbp + 6 * 8] ; for rsp\r
+ pop rbx\r
+ pop rdx\r
+ pop rcx\r
+ pop rax\r
+ pop r8\r
+ pop r9\r
+ pop r10\r
+ pop r11\r
+ pop r12\r
+ pop r13\r
+ pop r14\r
+ pop r15\r
+\r
+ mov rsp, rbp\r
+ pop rbp\r
+ add rsp, 16\r
+ iretq\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+; data\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+\r
+ align 010h\r
+\r
+gdtr dw GDT_END - GDT_BASE - 1 ; GDT limit\r
+ dq 0 ; (GDT base gets set above)\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+; global descriptor table (GDT)\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+\r
+ align 010h\r
+\r
+public GDT_BASE\r
+GDT_BASE:\r
+; null descriptor\r
+NULL_SEL equ $-GDT_BASE ; Selector [0x0]\r
+ dw 0 ; limit 15:0\r
+ dw 0 ; base 15:0\r
+ db 0 ; base 23:16\r
+ db 0 ; type\r
+ db 0 ; limit 19:16, flags\r
+ db 0 ; base 31:24\r
+\r
+; linear data segment descriptor\r
+LINEAR_SEL equ $-GDT_BASE ; Selector [0x8]\r
+ dw 0FFFFh ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 092h ; present, ring 0, data, expand-up, writable\r
+ db 0CFh ; page-granular, 32-bit\r
+ db 0\r
+\r
+; linear code segment descriptor\r
+LINEAR_CODE_SEL equ $-GDT_BASE ; Selector [0x10]\r
+ dw 0FFFFh ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 09Ah ; present, ring 0, data, expand-up, writable\r
+ db 0CFh ; page-granular, 32-bit\r
+ db 0\r
+\r
+; system data segment descriptor\r
+SYS_DATA_SEL equ $-GDT_BASE ; Selector [0x18]\r
+ dw 0FFFFh ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 092h ; present, ring 0, data, expand-up, writable\r
+ db 0CFh ; page-granular, 32-bit\r
+ db 0\r
+\r
+; system code segment descriptor\r
+SYS_CODE_SEL equ $-GDT_BASE ; Selector [0x20]\r
+ dw 0FFFFh ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 09Ah ; present, ring 0, data, expand-up, writable\r
+ db 0CFh ; page-granular, 32-bit\r
+ db 0\r
+\r
+; spare segment descriptor\r
+SPARE3_SEL equ $-GDT_BASE ; Selector [0x28]\r
+ dw 0 ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 0 ; present, ring 0, data, expand-up, writable\r
+ db 0 ; page-granular, 32-bit\r
+ db 0\r
+\r
+;\r
+; system data segment descriptor\r
+;\r
+SYS_DATA64_SEL equ $-GDT_BASE ; Selector [0x30]\r
+ dw 0FFFFh ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 092h ; P | DPL [1..2] | 1 | 1 | C | R | A\r
+ db 0CFh ; G | D | L | AVL | Segment [19..16]\r
+ db 0\r
+\r
+;\r
+; system code segment descriptor\r
+;\r
+SYS_CODE64_SEL equ $-GDT_BASE ; Selector [0x38]\r
+ dw 0FFFFh ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 09Ah ; P | DPL [1..2] | 1 | 1 | C | R | A\r
+ db 0AFh ; G | D | L | AVL | Segment [19..16]\r
+ db 0\r
+\r
+; spare segment descriptor\r
+SPARE4_SEL equ $-GDT_BASE ; Selector [0x40]\r
+ dw 0 ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 0 ; present, ring 0, data, expand-up, writable\r
+ db 0 ; page-granular, 32-bit\r
+ db 0\r
+\r
+GDT_END:\r
+\r
+ align 02h\r
+\r
+\r
+\r
+idtr dw IDT_END - IDT_BASE - 1 ; IDT limit\r
+ dq 0 ; (IDT base gets set above)\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+; interrupt descriptor table (IDT)\r
+;\r
+; Note: The hardware IRQ's specified in this table are the normal PC/AT IRQ\r
+; mappings. This implementation only uses the system timer and all other\r
+; IRQs will remain masked. The descriptors for vectors 33+ are provided\r
+; for convenience.\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+\r
+;idt_tag db "IDT",0 \r
+ align 02h\r
+\r
+public IDT_BASE\r
+IDT_BASE:\r
+; divide by zero (INT 0)\r
+DIV_ZERO_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; debug exception (INT 1)\r
+DEBUG_EXCEPT_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; NMI (INT 2)\r
+NMI_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; soft breakpoint (INT 3)\r
+BREAKPOINT_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; overflow (INT 4)\r
+OVERFLOW_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; bounds check (INT 5)\r
+BOUNDS_CHECK_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; invalid opcode (INT 6)\r
+INVALID_OPCODE_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; device not available (INT 7)\r
+DEV_NOT_AVAIL_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; double fault (INT 8)\r
+DOUBLE_FAULT_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; Coprocessor segment overrun - reserved (INT 9)\r
+RSVD_INTR_SEL1 equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; invalid TSS (INT 0ah)\r
+INVALID_TSS_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; segment not present (INT 0bh)\r
+SEG_NOT_PRESENT_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; stack fault (INT 0ch)\r
+STACK_FAULT_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; general protection (INT 0dh)\r
+GP_FAULT_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; page fault (INT 0eh)\r
+PAGE_FAULT_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; Intel reserved - do not use (INT 0fh)\r
+RSVD_INTR_SEL2 equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; floating point error (INT 10h)\r
+FLT_POINT_ERR_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; alignment check (INT 11h)\r
+ALIGNMENT_CHECK_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; machine check (INT 12h)\r
+MACHINE_CHECK_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; SIMD floating-point exception (INT 13h)\r
+SIMD_EXCEPTION_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+REPEAT (32 - 20)\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+ENDM\r
+\r
+; 72 unspecified descriptors\r
+ db (72 * 16) dup(0)\r
+ \r
+; IRQ 0 (System timer) - (INT 68h)\r
+IRQ0_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; IRQ 1 (8042 Keyboard controller) - (INT 69h)\r
+IRQ1_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; Reserved - IRQ 2 redirect (IRQ 2) - DO NOT USE!!! - (INT 6ah)\r
+IRQ2_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; IRQ 3 (COM 2) - (INT 6bh)\r
+IRQ3_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; IRQ 4 (COM 1) - (INT 6ch)\r
+IRQ4_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; IRQ 5 (LPT 2) - (INT 6dh)\r
+IRQ5_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; IRQ 6 (Floppy controller) - (INT 6eh)\r
+IRQ6_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; IRQ 7 (LPT 1) - (INT 6fh)\r
+IRQ7_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; IRQ 8 (RTC Alarm) - (INT 70h)\r
+IRQ8_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; IRQ 9 - (INT 71h)\r
+IRQ9_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; IRQ 10 - (INT 72h)\r
+IRQ10_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; IRQ 11 - (INT 73h)\r
+IRQ11_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; IRQ 12 (PS/2 mouse) - (INT 74h)\r
+IRQ12_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; IRQ 13 (Floating point error) - (INT 75h)\r
+IRQ13_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; IRQ 14 (Secondary IDE) - (INT 76h)\r
+IRQ14_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+; IRQ 15 (Primary IDE) - (INT 77h)\r
+IRQ15_SEL equ $-IDT_BASE\r
+ dw 0 ; offset 15:0\r
+ dw SYS_CODE64_SEL ; selector 15:0\r
+ db 0 ; 0 for interrupt gate\r
+ db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
+ dw 0 ; offset 31:16\r
+ dd 0 ; offset 63:32\r
+ dd 0 ; 0 for reserved\r
+\r
+ db (1 * 16) dup(0)\r
+\r
+IDT_END:\r
+\r
+ align 02h\r
+\r
+END\r
+++ /dev/null
- TITLE CpuInterrupt.asm: \r
-;------------------------------------------------------------------------------\r
-;*\r
-;* Copyright 2006, Intel Corporation \r
-;* All rights reserved. This program and the accompanying materials \r
-;* are licensed and made available under the terms and conditions of the BSD License \r
-;* which accompanies this distribution. The full text of the license may be found at \r
-;* http://opensource.org/licenses/bsd-license.php \r
-;* \r
-;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-;* \r
-;* CpuInterrupt.asm\r
-;* \r
-;* Abstract:\r
-;*\r
-;------------------------------------------------------------------------------\r
-\r
-EXTERNDEF mExceptionCodeSize:DWORD\r
-\r
-.code\r
-\r
-EXTERN TimerHandler: FAR\r
-EXTERN ExceptionHandler: NEAR\r
-EXTERN mTimerVector: QWORD\r
-\r
-mExceptionCodeSize DD 9\r
-\r
-InitDescriptor PROC\r
- lea rax, [GDT_BASE] ; RAX=PHYSICAL address of gdt\r
- mov qword ptr [gdtr + 2], rax ; Put address of gdt into the gdtr\r
- lgdt fword ptr [gdtr]\r
- mov rax, 18h\r
- mov gs, rax\r
- mov fs, rax\r
- lea rax, [IDT_BASE] ; RAX=PHYSICAL address of idt\r
- mov qword ptr [idtr + 2], rax ; Put address of idt into the idtr\r
- lidt fword ptr [idtr]\r
- ret\r
-InitDescriptor ENDP\r
-\r
-; VOID\r
-; InstallInterruptHandler (\r
-; UINTN Vector, // rcx\r
-; void (*Handler)(void) // rdx\r
-; )\r
-InstallInterruptHandler PROC \r
- push rbx\r
- pushfq ; save eflags\r
- cli ; turn off interrupts\r
- sub rsp, 10h ; open some space on the stack\r
- mov rbx, rsp\r
- sidt [rbx] ; get fword address of IDT\r
- mov rbx, [rbx+2] ; move offset of IDT into RBX\r
- add rsp, 10h ; correct stack\r
- mov rax, rcx ; Get vector number\r
- shl rax, 4 ; multiply by 16 to get offset\r
- add rbx, rax ; add to IDT base to get entry\r
- mov rax, rdx ; load new address into IDT entry\r
- mov word ptr [rbx], ax ; write bits 15..0 of offset\r
- shr rax, 16 ; use ax to copy 31..16 to descriptors\r
- mov word ptr [rbx+6], ax ; write bits 31..16 of offset\r
- shr rax, 16 ; use eax to copy 63..32 to descriptors\r
- mov dword ptr [rbx+8], eax ; write bits 63..32 of offset\r
- popfq ; restore flags (possible enabling interrupts)\r
- pop rbx\r
- ret\r
-\r
-InstallInterruptHandler ENDP\r
-\r
-JmpCommonIdtEntry macro\r
- ; jmp commonIdtEntry - this must be hand coded to keep the assembler from\r
- ; using a 8 bit reletive jump when the entries are\r
- ; within 255 bytes of the common entry. This must\r
- ; be done to maintain the consistency of the size\r
- ; of entry points...\r
- db 0e9h ; jmp 16 bit reletive \r
- dd commonIdtEntry - $ - 4 ; offset to jump to\r
-endm\r
-\r
- align 02h\r
-SystemExceptionHandler PROC\r
-INT0:\r
- push 0h ; push error code place holder on the stack\r
- push 0h\r
- JmpCommonIdtEntry\r
-; db 0e9h ; jmp 16 bit reletive \r
-; dd commonIdtEntry - $ - 4 ; offset to jump to\r
- \r
-INT1:\r
- push 0h ; push error code place holder on the stack\r
- push 1h\r
- JmpCommonIdtEntry\r
- \r
-INT2:\r
- push 0h ; push error code place holder on the stack\r
- push 2h\r
- JmpCommonIdtEntry\r
- \r
-INT3:\r
- push 0h ; push error code place holder on the stack\r
- push 3h\r
- JmpCommonIdtEntry\r
- \r
-INT4:\r
- push 0h ; push error code place holder on the stack\r
- push 4h\r
- JmpCommonIdtEntry\r
- \r
-INT5:\r
- push 0h ; push error code place holder on the stack\r
- push 5h\r
- JmpCommonIdtEntry\r
- \r
-INT6:\r
- push 0h ; push error code place holder on the stack\r
- push 6h\r
- JmpCommonIdtEntry\r
- \r
-INT7:\r
- push 0h ; push error code place holder on the stack\r
- push 7h\r
- JmpCommonIdtEntry\r
- \r
-INT8:\r
-; Double fault causes an error code to be pushed so no phony push necessary\r
- nop\r
- nop\r
- push 8h\r
- JmpCommonIdtEntry\r
- \r
-INT9:\r
- push 0h ; push error code place holder on the stack\r
- push 9h\r
- JmpCommonIdtEntry\r
- \r
-INT10:\r
-; Invalid TSS causes an error code to be pushed so no phony push necessary\r
- nop\r
- nop\r
- push 10\r
- JmpCommonIdtEntry\r
- \r
-INT11:\r
-; Segment Not Present causes an error code to be pushed so no phony push necessary\r
- nop\r
- nop\r
- push 11\r
- JmpCommonIdtEntry\r
- \r
-INT12:\r
-; Stack fault causes an error code to be pushed so no phony push necessary\r
- nop\r
- nop\r
- push 12\r
- JmpCommonIdtEntry\r
- \r
-INT13:\r
-; GP fault causes an error code to be pushed so no phony push necessary\r
- nop\r
- nop\r
- push 13\r
- JmpCommonIdtEntry\r
- \r
-INT14:\r
-; Page fault causes an error code to be pushed so no phony push necessary\r
- nop\r
- nop\r
- push 14\r
- JmpCommonIdtEntry\r
- \r
-INT15:\r
- push 0h ; push error code place holder on the stack\r
- push 15\r
- JmpCommonIdtEntry\r
- \r
-INT16:\r
- push 0h ; push error code place holder on the stack\r
- push 16\r
- JmpCommonIdtEntry\r
- \r
-INT17:\r
-; Alignment check causes an error code to be pushed so no phony push necessary\r
- nop\r
- nop\r
- push 17\r
- JmpCommonIdtEntry\r
- \r
-INT18:\r
- push 0h ; push error code place holder on the stack\r
- push 18\r
- JmpCommonIdtEntry\r
- \r
-INT19:\r
- push 0h ; push error code place holder on the stack\r
- push 19\r
- JmpCommonIdtEntry\r
-\r
-INTUnknown:\r
-REPEAT (32 - 20)\r
- push 0h ; push error code place holder on the stack\r
-; push xxh ; push vector number\r
- db 06ah\r
- db ( $ - INTUnknown - 3 ) / 9 + 20 ; vector number\r
- JmpCommonIdtEntry\r
-ENDM\r
-SystemExceptionHandler ENDP\r
-\r
-SystemTimerHandler PROC\r
- push 0\r
- push mTimerVector\r
- JmpCommonIdtEntry\r
-SystemTimerHandler ENDP\r
-\r
-commonIdtEntry:\r
-; +---------------------+ <-- 16-byte aligned ensured by processor\r
-; + Old SS +\r
-; +---------------------+\r
-; + Old RSP +\r
-; +---------------------+\r
-; + RFlags +\r
-; +---------------------+\r
-; + CS +\r
-; +---------------------+\r
-; + RIP +\r
-; +---------------------+\r
-; + Error Code +\r
-; +---------------------+\r
-; + Vector Number +\r
-; +---------------------+\r
-; + RBP +\r
-; +---------------------+ <-- RBP, 16-byte aligned\r
-\r
- cli\r
- push rbp\r
- mov rbp, rsp\r
-\r
- ;\r
- ; Since here the stack pointer is 16-byte aligned, so\r
- ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64\r
- ; is 16-byte aligned\r
- ; \r
-\r
-;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;\r
-;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;\r
- push r15\r
- push r14\r
- push r13\r
- push r12\r
- push r11\r
- push r10\r
- push r9\r
- push r8\r
- push rax\r
- push rcx\r
- push rdx\r
- push rbx\r
- push qword ptr [rbp + 6 * 8] ; RSP\r
- push qword ptr [rbp] ; RBP\r
- push rsi\r
- push rdi\r
-\r
-;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero\r
- movzx rax, word ptr [rbp + 7 * 8]\r
- push rax ; for ss\r
- movzx rax, word ptr [rbp + 4 * 8]\r
- push rax ; for cs\r
- mov rax, ds\r
- push rax\r
- mov rax, es\r
- push rax\r
- mov rax, fs\r
- push rax\r
- mov rax, gs\r
- push rax\r
-\r
-;; UINT64 Rip;\r
- push qword ptr [rbp + 3 * 8]\r
-\r
-;; UINT64 Gdtr[2], Idtr[2];\r
- sub rsp, 16\r
- sidt fword ptr [rsp]\r
- sub rsp, 16\r
- sgdt fword ptr [rsp]\r
-\r
-;; UINT64 Ldtr, Tr;\r
- xor rax, rax\r
- str ax\r
- push rax\r
- sldt ax\r
- push rax\r
-\r
-;; UINT64 RFlags;\r
- push qword ptr [rbp + 5 * 8]\r
-\r
-;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;\r
- mov rax, cr8\r
- push rax\r
- mov rax, cr4\r
- or rax, 208h\r
- mov cr4, rax\r
- push rax\r
- mov rax, cr3\r
- push rax\r
- mov rax, cr2\r
- push rax\r
- xor rax, rax\r
- push rax\r
- mov rax, cr0\r
- push rax\r
-\r
-;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
- mov rax, dr7\r
- push rax\r
-;; clear Dr7 while executing debugger itself\r
- xor rax, rax\r
- mov dr7, rax\r
-\r
- mov rax, dr6\r
- push rax\r
-;; insure all status bits in dr6 are clear...\r
- xor rax, rax\r
- mov dr6, rax\r
-\r
- mov rax, dr3\r
- push rax\r
- mov rax, dr2\r
- push rax\r
- mov rax, dr1\r
- push rax\r
- mov rax, dr0\r
- push rax\r
-\r
-;; FX_SAVE_STATE_X64 FxSaveState;\r
-\r
- sub rsp, 512\r
- mov rdi, rsp\r
- db 0fh, 0aeh, 00000111y ;fxsave [rdi]\r
-\r
-;; UINT32 ExceptionData;\r
- push qword ptr [rbp + 2 * 8]\r
-\r
-;; call into exception handler\r
-;; Prepare parameter and call\r
- mov rcx, qword ptr [rbp + 1 * 8]\r
- mov rdx, rsp\r
- ;\r
- ; Per X64 calling convention, allocate maximum parameter stack space\r
- ; and make sure RSP is 16-byte aligned\r
- ;\r
- sub rsp, 4 * 8 + 8\r
- cmp rcx, 32\r
- jb CallException\r
- call TimerHandler\r
- jmp ExceptionDone\r
-CallException:\r
- call ExceptionHandler\r
-ExceptionDone:\r
- add rsp, 4 * 8 + 8\r
-\r
- cli\r
-;; UINT64 ExceptionData;\r
- add rsp, 8\r
-\r
-;; FX_SAVE_STATE_X64 FxSaveState;\r
-\r
- mov rsi, rsp\r
- db 0fh, 0aeh, 00001110y ; fxrstor [rsi]\r
- add rsp, 512\r
-\r
-;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
- pop rax\r
- mov dr0, rax\r
- pop rax\r
- mov dr1, rax\r
- pop rax\r
- mov dr2, rax\r
- pop rax\r
- mov dr3, rax\r
-;; skip restore of dr6. We cleared dr6 during the context save.\r
- add rsp, 8\r
- pop rax\r
- mov dr7, rax\r
-\r
-;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;\r
- pop rax\r
- mov cr0, rax\r
- add rsp, 8 ; not for Cr1\r
- pop rax\r
- mov cr2, rax\r
- pop rax\r
- mov cr3, rax\r
- pop rax\r
- mov cr4, rax\r
- pop rax\r
- mov cr8, rax\r
-\r
-;; UINT64 RFlags;\r
- pop qword ptr [rbp + 5 * 8]\r
-\r
-;; UINT64 Ldtr, Tr;\r
-;; UINT64 Gdtr[2], Idtr[2];\r
-;; Best not let anyone mess with these particular registers...\r
- add rsp, 48\r
-\r
-;; UINT64 Rip;\r
- pop qword ptr [rbp + 3 * 8]\r
-\r
-;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;\r
- pop rax\r
- ; mov gs, rax ; not for gs\r
- pop rax\r
- ; mov fs, rax ; not for fs\r
- ; (X64 will not use fs and gs, so we do not restore it)\r
- pop rax\r
- mov es, rax\r
- pop rax\r
- mov ds, rax\r
- pop qword ptr [rbp + 4 * 8] ; for cs\r
- pop qword ptr [rbp + 7 * 8] ; for ss\r
-\r
-;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;\r
-;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;\r
- pop rdi\r
- pop rsi\r
- add rsp, 8 ; not for rbp\r
- pop qword ptr [rbp + 6 * 8] ; for rsp\r
- pop rbx\r
- pop rdx\r
- pop rcx\r
- pop rax\r
- pop r8\r
- pop r9\r
- pop r10\r
- pop r11\r
- pop r12\r
- pop r13\r
- pop r14\r
- pop r15\r
-\r
- mov rsp, rbp\r
- pop rbp\r
- add rsp, 16\r
- iretq\r
-\r
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
-; data\r
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
-\r
- align 010h\r
-\r
-gdtr dw GDT_END - GDT_BASE - 1 ; GDT limit\r
- dq 0 ; (GDT base gets set above)\r
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
-; global descriptor table (GDT)\r
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
-\r
- align 010h\r
-\r
-public GDT_BASE\r
-GDT_BASE:\r
-; null descriptor\r
-NULL_SEL equ $-GDT_BASE ; Selector [0x0]\r
- dw 0 ; limit 15:0\r
- dw 0 ; base 15:0\r
- db 0 ; base 23:16\r
- db 0 ; type\r
- db 0 ; limit 19:16, flags\r
- db 0 ; base 31:24\r
-\r
-; linear data segment descriptor\r
-LINEAR_SEL equ $-GDT_BASE ; Selector [0x8]\r
- dw 0FFFFh ; limit 0xFFFFF\r
- dw 0 ; base 0\r
- db 0\r
- db 092h ; present, ring 0, data, expand-up, writable\r
- db 0CFh ; page-granular, 32-bit\r
- db 0\r
-\r
-; linear code segment descriptor\r
-LINEAR_CODE_SEL equ $-GDT_BASE ; Selector [0x10]\r
- dw 0FFFFh ; limit 0xFFFFF\r
- dw 0 ; base 0\r
- db 0\r
- db 09Ah ; present, ring 0, data, expand-up, writable\r
- db 0CFh ; page-granular, 32-bit\r
- db 0\r
-\r
-; system data segment descriptor\r
-SYS_DATA_SEL equ $-GDT_BASE ; Selector [0x18]\r
- dw 0FFFFh ; limit 0xFFFFF\r
- dw 0 ; base 0\r
- db 0\r
- db 092h ; present, ring 0, data, expand-up, writable\r
- db 0CFh ; page-granular, 32-bit\r
- db 0\r
-\r
-; system code segment descriptor\r
-SYS_CODE_SEL equ $-GDT_BASE ; Selector [0x20]\r
- dw 0FFFFh ; limit 0xFFFFF\r
- dw 0 ; base 0\r
- db 0\r
- db 09Ah ; present, ring 0, data, expand-up, writable\r
- db 0CFh ; page-granular, 32-bit\r
- db 0\r
-\r
-; spare segment descriptor\r
-SPARE3_SEL equ $-GDT_BASE ; Selector [0x28]\r
- dw 0 ; limit 0xFFFFF\r
- dw 0 ; base 0\r
- db 0\r
- db 0 ; present, ring 0, data, expand-up, writable\r
- db 0 ; page-granular, 32-bit\r
- db 0\r
-\r
-;\r
-; system data segment descriptor\r
-;\r
-SYS_DATA64_SEL equ $-GDT_BASE ; Selector [0x30]\r
- dw 0FFFFh ; limit 0xFFFFF\r
- dw 0 ; base 0\r
- db 0\r
- db 092h ; P | DPL [1..2] | 1 | 1 | C | R | A\r
- db 0CFh ; G | D | L | AVL | Segment [19..16]\r
- db 0\r
-\r
-;\r
-; system code segment descriptor\r
-;\r
-SYS_CODE64_SEL equ $-GDT_BASE ; Selector [0x38]\r
- dw 0FFFFh ; limit 0xFFFFF\r
- dw 0 ; base 0\r
- db 0\r
- db 09Ah ; P | DPL [1..2] | 1 | 1 | C | R | A\r
- db 0AFh ; G | D | L | AVL | Segment [19..16]\r
- db 0\r
-\r
-; spare segment descriptor\r
-SPARE4_SEL equ $-GDT_BASE ; Selector [0x40]\r
- dw 0 ; limit 0xFFFFF\r
- dw 0 ; base 0\r
- db 0\r
- db 0 ; present, ring 0, data, expand-up, writable\r
- db 0 ; page-granular, 32-bit\r
- db 0\r
-\r
-GDT_END:\r
-\r
- align 02h\r
-\r
-\r
-\r
-idtr dw IDT_END - IDT_BASE - 1 ; IDT limit\r
- dq 0 ; (IDT base gets set above)\r
-\r
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
-; interrupt descriptor table (IDT)\r
-;\r
-; Note: The hardware IRQ's specified in this table are the normal PC/AT IRQ\r
-; mappings. This implementation only uses the system timer and all other\r
-; IRQs will remain masked. The descriptors for vectors 33+ are provided\r
-; for convenience.\r
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
-\r
-;idt_tag db "IDT",0 \r
- align 02h\r
-\r
-public IDT_BASE\r
-IDT_BASE:\r
-; divide by zero (INT 0)\r
-DIV_ZERO_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; debug exception (INT 1)\r
-DEBUG_EXCEPT_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; NMI (INT 2)\r
-NMI_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; soft breakpoint (INT 3)\r
-BREAKPOINT_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; overflow (INT 4)\r
-OVERFLOW_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; bounds check (INT 5)\r
-BOUNDS_CHECK_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; invalid opcode (INT 6)\r
-INVALID_OPCODE_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; device not available (INT 7)\r
-DEV_NOT_AVAIL_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; double fault (INT 8)\r
-DOUBLE_FAULT_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; Coprocessor segment overrun - reserved (INT 9)\r
-RSVD_INTR_SEL1 equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; invalid TSS (INT 0ah)\r
-INVALID_TSS_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; segment not present (INT 0bh)\r
-SEG_NOT_PRESENT_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; stack fault (INT 0ch)\r
-STACK_FAULT_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; general protection (INT 0dh)\r
-GP_FAULT_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; page fault (INT 0eh)\r
-PAGE_FAULT_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; Intel reserved - do not use (INT 0fh)\r
-RSVD_INTR_SEL2 equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; floating point error (INT 10h)\r
-FLT_POINT_ERR_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; alignment check (INT 11h)\r
-ALIGNMENT_CHECK_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; machine check (INT 12h)\r
-MACHINE_CHECK_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; SIMD floating-point exception (INT 13h)\r
-SIMD_EXCEPTION_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-REPEAT (32 - 20)\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-ENDM\r
-\r
-; 72 unspecified descriptors\r
- db (72 * 16) dup(0)\r
- \r
-; IRQ 0 (System timer) - (INT 68h)\r
-IRQ0_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; IRQ 1 (8042 Keyboard controller) - (INT 69h)\r
-IRQ1_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; Reserved - IRQ 2 redirect (IRQ 2) - DO NOT USE!!! - (INT 6ah)\r
-IRQ2_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; IRQ 3 (COM 2) - (INT 6bh)\r
-IRQ3_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; IRQ 4 (COM 1) - (INT 6ch)\r
-IRQ4_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; IRQ 5 (LPT 2) - (INT 6dh)\r
-IRQ5_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; IRQ 6 (Floppy controller) - (INT 6eh)\r
-IRQ6_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; IRQ 7 (LPT 1) - (INT 6fh)\r
-IRQ7_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; IRQ 8 (RTC Alarm) - (INT 70h)\r
-IRQ8_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; IRQ 9 - (INT 71h)\r
-IRQ9_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; IRQ 10 - (INT 72h)\r
-IRQ10_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; IRQ 11 - (INT 73h)\r
-IRQ11_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; IRQ 12 (PS/2 mouse) - (INT 74h)\r
-IRQ12_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; IRQ 13 (Floating point error) - (INT 75h)\r
-IRQ13_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; IRQ 14 (Secondary IDE) - (INT 76h)\r
-IRQ14_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
-; IRQ 15 (Primary IDE) - (INT 77h)\r
-IRQ15_SEL equ $-IDT_BASE\r
- dw 0 ; offset 15:0\r
- dw SYS_CODE64_SEL ; selector 15:0\r
- db 0 ; 0 for interrupt gate\r
- db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
- dw 0 ; offset 31:16\r
- dd 0 ; offset 63:32\r
- dd 0 ; 0 for reserved\r
-\r
- db (1 * 16) dup(0)\r
-\r
-IDT_END:\r
-\r
- align 02h\r
-\r
-END\r
projects / mirror_edk2.git / commitdiff