Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);\r
AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
**/\r
#define MSR_HASWELL_PLATFORM_INFO 0x000000CE\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.\r
+ MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.\r
+ MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.\r
@{\r
**/\r
#define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2);\r
AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.\r
**/\r
#define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT);\r
AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
**/\r
#define MSR_HASWELL_LBR_SELECT 0x000001C8\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1);\r
AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.\r
**/\r
#define MSR_HASWELL_PKGC_IRTL1 0x0000060B\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2);\r
AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.\r
**/\r
#define MSR_HASWELL_PKGC_IRTL2 0x0000060C\r
\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS);\r
@endcode\r
+ @note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_PKG_PERF_STATUS 0x00000613\r
\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS);\r
@endcode\r
+ @note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619\r
\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS);\r
@endcode\r
+ @note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL);\r
@endcode\r
+ @note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r
**/\r
#define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1);\r
@endcode\r
+ @note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r
**/\r
#define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2);\r
@endcode\r
+ @note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r
**/\r
#define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL);\r
AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r
**/\r
#define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO);\r
AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
**/\r
#define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_IA32_DEBUG_FEATURE);\r
AsmWriteMsr64 (MSR_HASWELL_IA32_DEBUG_FEATURE, Msr);\r
@endcode\r
+ @note MSR_HASWELL_IA32_DEBUG_FEATURE is defined as IA32_DEBUG_FEATURE in SDM.\r
**/\r
#define MSR_HASWELL_IA32_DEBUG_FEATURE 0x00000C80\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL);\r
AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
#define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP);\r
AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
**/\r
#define MSR_HASWELL_SMM_MCA_CAP 0x0000017D\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT);\r
@endcode\r
+ @note MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
#define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r
**/\r
#define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r
**/\r
#define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r
**/\r
#define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG);\r
@endcode\r
+ @note MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r
**/\r
#define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL);\r
AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.\r
**/\r
#define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0\r
\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED);\r
@endcode\r
+ @note MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.\r
**/\r
#define MSR_HASWELL_SMM_DELAYED 0x000004E2\r
\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED);\r
@endcode\r
+ @note MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.\r
**/\r
#define MSR_HASWELL_SMM_BLOCKED 0x000004E3\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT);\r
@endcode\r
+ @note MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
**/\r
#define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT);\r
AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr);\r
@endcode\r
+ @note MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.\r
**/\r
#define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640\r
\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS);\r
@endcode\r
+ @note MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r
**/\r
#define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY);\r
AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr);\r
@endcode\r
+ @note MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.\r
**/\r
#define MSR_HASWELL_PP1_POLICY 0x00000642\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS);\r
AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
**/\r
#define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS);\r
AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.\r
**/\r
#define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS);\r
AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.\r
**/\r
#define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736\r
\r
Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1);\r
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr);\r
@endcode\r
+ @note MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r
**/\r
#define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY);\r
AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.\r
**/\r
#define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY);\r
AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.\r
**/\r
#define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY);\r
AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64);\r
@endcode\r
+ @note MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.\r
**/\r
#define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632\r
\r