--- /dev/null
+/** @file\r
+ OVMF's instance of the PCI Host Bridge Library.\r
+\r
+ Copyright (C) 2016-2021, Red Hat, Inc.\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+#include <IndustryStandard/Pci.h> // PCI_MAX_BUS\r
+#include <IndustryStandard/Q35MchIch9.h> // INTEL_Q35_MCH_DEVIC...\r
+#include <Library/BaseMemoryLib.h> // ZeroMem()\r
+#include <Library/PcdLib.h> // PcdGet64()\r
+#include <Library/PciHostBridgeLib.h> // PCI_ROOT_BRIDGE_APE...\r
+#include <Library/PciHostBridgeUtilityLib.h> // PciHostBridgeUtilit...\r
+#include <Protocol/PciHostBridgeResourceAllocation.h> // EFI_PCI_HOST_BRIDGE...\r
+#include <Protocol/PciRootBridgeIo.h> // EFI_PCI_ATTRIBUTE_I...\r
+\r
+#include "PciHostBridge.h"\r
+\r
+STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture = { MAX_UINT64, 0 };\r
+\r
+\r
+/**\r
+ Return all the root bridge instances in an array.\r
+\r
+ @param Count Return the count of root bridge instances.\r
+\r
+ @return All the root bridge instances in an array.\r
+ The array should be passed into PciHostBridgeFreeRootBridges()\r
+ when it's not used.\r
+**/\r
+PCI_ROOT_BRIDGE *\r
+EFIAPI\r
+PciHostBridgeGetRootBridges (\r
+ UINTN *Count\r
+ )\r
+{\r
+ UINT64 Attributes;\r
+ UINT64 AllocationAttributes;\r
+ PCI_ROOT_BRIDGE_APERTURE Io;\r
+ PCI_ROOT_BRIDGE_APERTURE Mem;\r
+ PCI_ROOT_BRIDGE_APERTURE MemAbove4G;\r
+\r
+ if (PcdGetBool (PcdPciDisableBusEnumeration)) {\r
+ return ScanForRootBridges (Count);\r
+ }\r
+\r
+ ZeroMem (&Io, sizeof (Io));\r
+ ZeroMem (&Mem, sizeof (Mem));\r
+ ZeroMem (&MemAbove4G, sizeof (MemAbove4G));\r
+\r
+ Attributes = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |\r
+ EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |\r
+ EFI_PCI_ATTRIBUTE_ISA_IO_16 |\r
+ EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |\r
+ EFI_PCI_ATTRIBUTE_VGA_MEMORY |\r
+ EFI_PCI_ATTRIBUTE_VGA_IO_16 |\r
+ EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+\r
+ AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;\r
+ if (PcdGet64 (PcdPciMmio64Size) > 0) {\r
+ AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;\r
+ MemAbove4G.Base = PcdGet64 (PcdPciMmio64Base);\r
+ MemAbove4G.Limit = PcdGet64 (PcdPciMmio64Base) +\r
+ PcdGet64 (PcdPciMmio64Size) - 1;\r
+ } else {\r
+ CopyMem (&MemAbove4G, &mNonExistAperture, sizeof (mNonExistAperture));\r
+ }\r
+\r
+ Io.Base = PcdGet64 (PcdPciIoBase);\r
+ Io.Limit = PcdGet64 (PcdPciIoBase) + (PcdGet64 (PcdPciIoSize) - 1);\r
+ Mem.Base = PcdGet64 (PcdPciMmio32Base);\r
+ Mem.Limit = PcdGet64 (PcdPciMmio32Base) + (PcdGet64 (PcdPciMmio32Size) - 1);\r
+\r
+ return PciHostBridgeUtilityGetRootBridges (\r
+ Count,\r
+ Attributes,\r
+ AllocationAttributes,\r
+ FALSE,\r
+ PcdGet16 (PcdOvmfHostBridgePciDevId) != INTEL_Q35_MCH_DEVICE_ID,\r
+ 0,\r
+ PCI_MAX_BUS,\r
+ &Io,\r
+ &Mem,\r
+ &MemAbove4G,\r
+ &mNonExistAperture,\r
+ &mNonExistAperture\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Free the root bridge instances array returned from\r
+ PciHostBridgeGetRootBridges().\r
+\r
+ @param The root bridge instances array.\r
+ @param The count of the array.\r
+**/\r
+VOID\r
+EFIAPI\r
+PciHostBridgeFreeRootBridges (\r
+ PCI_ROOT_BRIDGE *Bridges,\r
+ UINTN Count\r
+ )\r
+{\r
+ PciHostBridgeUtilityFreeRootBridges (Bridges, Count);\r
+}\r
+\r
+\r
+/**\r
+ Inform the platform that the resource conflict happens.\r
+\r
+ @param HostBridgeHandle Handle of the Host Bridge.\r
+ @param Configuration Pointer to PCI I/O and PCI memory resource\r
+ descriptors. The Configuration contains the resources\r
+ for all the root bridges. The resource for each root\r
+ bridge is terminated with END descriptor and an\r
+ additional END is appended indicating the end of the\r
+ entire resources. The resource descriptor field\r
+ values follow the description in\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ .SubmitResources().\r
+**/\r
+VOID\r
+EFIAPI\r
+PciHostBridgeResourceConflict (\r
+ EFI_HANDLE HostBridgeHandle,\r
+ VOID *Configuration\r
+ )\r
+{\r
+ PciHostBridgeUtilityResourceConflict (Configuration);\r
+}\r
--- /dev/null
+/** @file\r
+ Scan the entire PCI bus for root bridges to support OVMF above Xen.\r
+\r
+ Copyright (C) 2021, Red Hat, Inc.\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#include <IndustryStandard/Pci.h> // EFI_PCI_COMMAND_IO_SPACE\r
+#include <IndustryStandard/Q35MchIch9.h> // INTEL_Q35_MCH_DEVICE_ID\r
+#include <Library/BaseLib.h> // DisableInterrupts()\r
+#include <Library/BaseMemoryLib.h> // ZeroMem()\r
+#include <Library/DebugLib.h> // ASSERT()\r
+#include <Library/MemoryAllocationLib.h> // ReallocatePool()\r
+#include <Library/PcdLib.h> // PcdGet16()\r
+#include <Library/PciHostBridgeLib.h> // PCI_ROOT_BRIDGE_APERTURE\r
+#include <Library/PciHostBridgeUtilityLib.h> // PciHostBridgeUtilityInitRoot...\r
+#include <Library/PciLib.h> // PciRead32()\r
+#include <Protocol/PciRootBridgeIo.h> // EFI_PCI_ATTRIBUTE_ISA_IO\r
+\r
+#include "PciHostBridge.h"\r
+\r
+STATIC\r
+VOID\r
+PcatPciRootBridgeBarExisted (\r
+ IN UINTN Address,\r
+ OUT UINT32 *OriginalValue,\r
+ OUT UINT32 *Value\r
+ )\r
+{\r
+ //\r
+ // Preserve the original value\r
+ //\r
+ *OriginalValue = PciRead32 (Address);\r
+\r
+ //\r
+ // Disable timer interrupt while the BAR is probed\r
+ //\r
+ DisableInterrupts ();\r
+\r
+ PciWrite32 (Address, 0xFFFFFFFF);\r
+ *Value = PciRead32 (Address);\r
+ PciWrite32 (Address, *OriginalValue);\r
+\r
+ //\r
+ // Enable interrupt\r
+ //\r
+ EnableInterrupts ();\r
+}\r
+\r
+#define PCI_COMMAND_DECODE ((UINT16)(EFI_PCI_COMMAND_IO_SPACE | \\r
+ EFI_PCI_COMMAND_MEMORY_SPACE))\r
+STATIC\r
+VOID\r
+PcatPciRootBridgeDecodingDisable (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ UINT16 Value;\r
+\r
+ Value = PciRead16 (Address);\r
+ if (Value & PCI_COMMAND_DECODE) {\r
+ PciWrite16 (Address, Value & ~(UINT32)PCI_COMMAND_DECODE);\r
+ }\r
+}\r
+\r
+STATIC\r
+VOID\r
+PcatPciRootBridgeParseBars (\r
+ IN UINT16 Command,\r
+ IN UINTN Bus,\r
+ IN UINTN Device,\r
+ IN UINTN Function,\r
+ IN UINTN BarOffsetBase,\r
+ IN UINTN BarOffsetEnd,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G\r
+\r
+)\r
+{\r
+ UINT32 OriginalValue;\r
+ UINT32 Value;\r
+ UINT32 OriginalUpperValue;\r
+ UINT32 UpperValue;\r
+ UINT64 Mask;\r
+ UINTN Offset;\r
+ UINT64 Base;\r
+ UINT64 Length;\r
+ UINT64 Limit;\r
+ PCI_ROOT_BRIDGE_APERTURE *MemAperture;\r
+\r
+ // Disable address decoding for every device before OVMF starts sizing it\r
+ PcatPciRootBridgeDecodingDisable (\r
+ PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET)\r
+ );\r
+\r
+ for (Offset = BarOffsetBase; Offset < BarOffsetEnd; Offset += sizeof (UINT32)) {\r
+ PcatPciRootBridgeBarExisted (\r
+ PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r
+ &OriginalValue, &Value\r
+ );\r
+ if (Value == 0) {\r
+ continue;\r
+ }\r
+ if ((Value & BIT0) == BIT0) {\r
+ //\r
+ // IO Bar\r
+ //\r
+ if (Command & EFI_PCI_COMMAND_IO_SPACE) {\r
+ Mask = 0xfffffffc;\r
+ Base = OriginalValue & Mask;\r
+ Length = ((~(Value & Mask)) & Mask) + 0x04;\r
+ if (!(Value & 0xFFFF0000)) {\r
+ Length &= 0x0000FFFF;\r
+ }\r
+ Limit = Base + Length - 1;\r
+\r
+ if (Base < Limit) {\r
+ if (Io->Base > Base) {\r
+ Io->Base = Base;\r
+ }\r
+ if (Io->Limit < Limit) {\r
+ Io->Limit = Limit;\r
+ }\r
+ }\r
+ }\r
+ } else {\r
+ //\r
+ // Mem Bar\r
+ //\r
+ if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {\r
+\r
+ Mask = 0xfffffff0;\r
+ Base = OriginalValue & Mask;\r
+ Length = Value & Mask;\r
+\r
+ if ((Value & (BIT1 | BIT2)) == 0) {\r
+ //\r
+ // 32bit\r
+ //\r
+ Length = ((~Length) + 1) & 0xffffffff;\r
+\r
+ MemAperture = Mem;\r
+ } else {\r
+ //\r
+ // 64bit\r
+ //\r
+ Offset += 4;\r
+ PcatPciRootBridgeBarExisted (\r
+ PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r
+ &OriginalUpperValue,\r
+ &UpperValue\r
+ );\r
+\r
+ Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);\r
+ Length = Length | LShiftU64 ((UINT64) UpperValue, 32);\r
+ Length = (~Length) + 1;\r
+\r
+ if (Base < BASE_4GB) {\r
+ MemAperture = Mem;\r
+ } else {\r
+ MemAperture = MemAbove4G;\r
+ }\r
+ }\r
+\r
+ Limit = Base + Length - 1;\r
+ if (Base < Limit) {\r
+ if (MemAperture->Base > Base) {\r
+ MemAperture->Base = Base;\r
+ }\r
+ if (MemAperture->Limit < Limit) {\r
+ MemAperture->Limit = Limit;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture = { MAX_UINT64, 0 };\r
+\r
+PCI_ROOT_BRIDGE *\r
+ScanForRootBridges (\r
+ UINTN *NumberOfRootBridges\r
+ )\r
+{\r
+ UINTN PrimaryBus;\r
+ UINTN SubBus;\r
+ UINT8 Device;\r
+ UINT8 Function;\r
+ UINTN NumberOfDevices;\r
+ UINTN Address;\r
+ PCI_TYPE01 Pci;\r
+ UINT64 Attributes;\r
+ UINT64 Base;\r
+ UINT64 Limit;\r
+ UINT64 Value;\r
+ PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, *MemAperture;\r
+ PCI_ROOT_BRIDGE *RootBridges;\r
+ UINTN BarOffsetEnd;\r
+\r
+\r
+ *NumberOfRootBridges = 0;\r
+ RootBridges = NULL;\r
+\r
+ //\r
+ // After scanning all the PCI devices on the PCI root bridge's primary bus,\r
+ // update the Primary Bus Number for the next PCI root bridge to be this PCI\r
+ // root bridge's subordinate bus number + 1.\r
+ //\r
+ for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {\r
+ SubBus = PrimaryBus;\r
+ Attributes = 0;\r
+\r
+ ZeroMem (&Io, sizeof (Io));\r
+ ZeroMem (&Mem, sizeof (Mem));\r
+ ZeroMem (&MemAbove4G, sizeof (MemAbove4G));\r
+ Io.Base = Mem.Base = MemAbove4G.Base = MAX_UINT64;\r
+ //\r
+ // Scan all the PCI devices on the primary bus of the PCI root bridge\r
+ //\r
+ for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
+\r
+ for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {\r
+\r
+ //\r
+ // Compute the PCI configuration address of the PCI device to probe\r
+ //\r
+ Address = PCI_LIB_ADDRESS (PrimaryBus, Device, Function, 0);\r
+\r
+ //\r
+ // Read the Vendor ID from the PCI Configuration Header\r
+ //\r
+ if (PciRead16 (Address) == MAX_UINT16) {\r
+ if (Function == 0) {\r
+ //\r
+ // If the PCI Configuration Read fails, or a PCI device does not\r
+ // exist, then skip this entire PCI device\r
+ //\r
+ break;\r
+ } else {\r
+ //\r
+ // If PCI function != 0, VendorId == 0xFFFF, we continue to search\r
+ // PCI function.\r
+ //\r
+ continue;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Read the entire PCI Configuration Header\r
+ //\r
+ PciReadBuffer (Address, sizeof (Pci), &Pci);\r
+\r
+ //\r
+ // Increment the number of PCI device found on the primary bus of the\r
+ // PCI root bridge\r
+ //\r
+ NumberOfDevices++;\r
+\r
+ //\r
+ // Look for devices with the VGA Palette Snoop enabled in the COMMAND\r
+ // register of the PCI Config Header\r
+ //\r
+ if ((Pci.Hdr.Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+ }\r
+\r
+ BarOffsetEnd = 0;\r
+\r
+ //\r
+ // PCI-PCI Bridge\r
+ //\r
+ if (IS_PCI_BRIDGE (&Pci)) {\r
+ //\r
+ // Get the Bus range that the PPB is decoding\r
+ //\r
+ if (Pci.Bridge.SubordinateBus > SubBus) {\r
+ //\r
+ // If the subordinate bus number of the PCI-PCI bridge is greater\r
+ // than the PCI root bridge's current subordinate bus number,\r
+ // then update the PCI root bridge's subordinate bus number\r
+ //\r
+ SubBus = Pci.Bridge.SubordinateBus;\r
+ }\r
+\r
+ //\r
+ // Get the I/O range that the PPB is decoding\r
+ //\r
+ Value = Pci.Bridge.IoBase & 0x0f;\r
+ Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;\r
+ Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;\r
+ if (Value == BIT0) {\r
+ Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16);\r
+ Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16);\r
+ }\r
+ if (Base < Limit) {\r
+ if (Io.Base > Base) {\r
+ Io.Base = Base;\r
+ }\r
+ if (Io.Limit < Limit) {\r
+ Io.Limit = Limit;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Get the Memory range that the PPB is decoding\r
+ //\r
+ Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16;\r
+ Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;\r
+ if (Base < Limit) {\r
+ if (Mem.Base > Base) {\r
+ Mem.Base = Base;\r
+ }\r
+ if (Mem.Limit < Limit) {\r
+ Mem.Limit = Limit;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Get the Prefetchable Memory range that the PPB is decoding\r
+ // and merge it into Memory range\r
+ //\r
+ Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;\r
+ Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;\r
+ Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)\r
+ << 16) | 0xfffff;\r
+ MemAperture = &Mem;\r
+ if (Value == BIT0) {\r
+ Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);\r
+ Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);\r
+ MemAperture = &MemAbove4G;\r
+ }\r
+ if (Base < Limit) {\r
+ if (MemAperture->Base > Base) {\r
+ MemAperture->Base = Base;\r
+ }\r
+ if (MemAperture->Limit < Limit) {\r
+ MemAperture->Limit = Limit;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Look at the PPB Configuration for legacy decoding attributes\r
+ //\r
+ if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA)\r
+ == EFI_PCI_BRIDGE_CONTROL_ISA) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
+ }\r
+ if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA)\r
+ == EFI_PCI_BRIDGE_CONTROL_VGA) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
+ if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16)\r
+ != 0) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r
+ }\r
+ }\r
+\r
+ BarOffsetEnd = OFFSET_OF (PCI_TYPE01, Bridge.Bar[2]);\r
+ } else {\r
+ //\r
+ // Parse the BARs of the PCI device to get what I/O Ranges, Memory\r
+ // Ranges, and Prefetchable Memory Ranges the device is decoding\r
+ //\r
+ if ((Pci.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) {\r
+ BarOffsetEnd = OFFSET_OF (PCI_TYPE00, Device.Bar[6]);\r
+ }\r
+ }\r
+\r
+ PcatPciRootBridgeParseBars (\r
+ Pci.Hdr.Command,\r
+ PrimaryBus,\r
+ Device,\r
+ Function,\r
+ OFFSET_OF (PCI_TYPE00, Device.Bar),\r
+ BarOffsetEnd,\r
+ &Io,\r
+ &Mem, &MemAbove4G\r
+ );\r
+\r
+ //\r
+ // See if the PCI device is an IDE controller\r
+ //\r
+ if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE,\r
+ PCI_CLASS_MASS_STORAGE_IDE)) {\r
+ if (Pci.Hdr.ClassCode[0] & 0x80) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
+ }\r
+ if (Pci.Hdr.ClassCode[0] & 0x01) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
+ }\r
+ if (Pci.Hdr.ClassCode[0] & 0x04) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
+ }\r
+ }\r
+\r
+ //\r
+ // See if the PCI device is a legacy VGA controller or\r
+ // a standard VGA controller\r
+ //\r
+ if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) ||\r
+ IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA)\r
+ ) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r
+ }\r
+\r
+ //\r
+ // See if the PCI Device is a PCI - ISA or PCI - EISA\r
+ // or ISA_POSITIVE_DECODE Bridge device\r
+ //\r
+ if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {\r
+ if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA ||\r
+ Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA ||\r
+ Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
+ }\r
+ }\r
+\r
+ //\r
+ // If this device is not a multi function device, then skip the rest\r
+ // of this PCI device\r
+ //\r
+ if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // If at least one PCI device was found on the primary bus of this PCI\r
+ // root bridge, then the PCI root bridge exists.\r
+ //\r
+ if (NumberOfDevices > 0) {\r
+ RootBridges = ReallocatePool (\r
+ (*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),\r
+ (*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),\r
+ RootBridges\r
+ );\r
+ ASSERT (RootBridges != NULL);\r
+ PciHostBridgeUtilityInitRootBridge (\r
+ Attributes, Attributes, 0,\r
+ FALSE, PcdGet16 (PcdOvmfHostBridgePciDevId) != INTEL_Q35_MCH_DEVICE_ID,\r
+ (UINT8) PrimaryBus, (UINT8) SubBus,\r
+ &Io, &Mem, &MemAbove4G, &mNonExistAperture, &mNonExistAperture,\r
+ &RootBridges[*NumberOfRootBridges]\r
+ );\r
+ RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;\r
+ //\r
+ // Increment the index for the next PCI Root Bridge\r
+ //\r
+ (*NumberOfRootBridges)++;\r
+ }\r
+ }\r
+\r
+ return RootBridges;\r
+}\r
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