0, // Power Mgt 2 Ctrl Reg Blk unsupported\r
PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk\r
GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk\r
- GPE1_BLK, // Port addr of General Purpose Event 1 Reg Blk\r
+ 0, // General Purpose Event 1 Reg Blk unsupported\r
PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk\r
PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk\r
0, // Power Mgt 2 Ctrl Reg Blk unsupported\r
PM_TM_LEN, // Byte Length of ports at pm_tm_blk\r
GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk\r
- GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk\r
- GPE1_BASE, // offset in gpe model where gpe1 events start\r
+ 0, // General Purpose Event 1 Reg Blk unsupported\r
+ 0, // General Purpose Event 1 Reg Blk unsupported\r
0, // _CST support\r
P_LVL2_LAT, // worst case HW latency to enter/exit C2 state\r
P_LVL3_LAT, // worst case HW latency to enter/exit C3 state\r
#define PM1a_CNT_BLK 0x0000b004\r
#define PM_TMR_BLK 0x0000b008\r
#define GPE0_BLK 0x0000afe0\r
-#define GPE1_BLK 0x00000000\r
#define PM1_EVT_LEN 0x04\r
#define PM1_CNT_LEN 0x02\r
#define PM_TM_LEN 0x04\r
#define GPE0_BLK_LEN 0x04\r
-#define GPE1_BLK_LEN 0x00\r
-#define GPE1_BASE 0x00\r
#define RESERVED 0x00\r
#define P_LVL2_LAT 0x0065\r
#define P_LVL3_LAT 0x03E9\r