//\r
// Set TCR that allows us to retrieve T0SZ in the subsequent functions\r
//\r
- if ((ArmReadCurrentEL () == AARCH64_EL2) || (ArmReadCurrentEL () == AARCH64_EL3)) {\r
- //Note: Bits 23 and 31 are reserved bits in TCR_EL2 and TCR_EL3\r
+ // Ideally we will be running at EL2, but should support EL1 as well.\r
+ // UEFI should not run at EL3.\r
+ if (ArmReadCurrentEL () == AARCH64_EL2) {\r
+ //Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2\r
TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;\r
\r
// Set the Physical Address Size using MaxAddress\r
} else if (MaxAddress < SIZE_256TB) {\r
TCR |= TCR_PS_256TB;\r
} else {\r
- DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU support.\n", MaxAddress));\r
+ DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));\r
+ ASSERT (0); // Bigger than 48-bit memory space are not supported\r
+ return RETURN_UNSUPPORTED;\r
+ }\r
+ } else if (ArmReadCurrentEL () == AARCH64_EL1) {\r
+ TCR = T0SZ | TCR_TG0_4KB;\r
+\r
+ // Set the Physical Address Size using MaxAddress\r
+ if (MaxAddress < SIZE_4GB) {\r
+ TCR |= TCR_IPS_4GB;\r
+ } else if (MaxAddress < SIZE_64GB) {\r
+ TCR |= TCR_IPS_64GB;\r
+ } else if (MaxAddress < SIZE_1TB) {\r
+ TCR |= TCR_IPS_1TB;\r
+ } else if (MaxAddress < SIZE_4TB) {\r
+ TCR |= TCR_IPS_4TB;\r
+ } else if (MaxAddress < SIZE_16TB) {\r
+ TCR |= TCR_IPS_16TB;\r
+ } else if (MaxAddress < SIZE_256TB) {\r
+ TCR |= TCR_IPS_256TB;\r
+ } else {\r
+ DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));\r
ASSERT (0); // Bigger than 48-bit memory space are not supported\r
return RETURN_UNSUPPORTED;\r
}\r
} else {\r
- ASSERT (0); // Bigger than 48-bit memory space are not supported\r
+ ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3.\r
return RETURN_UNSUPPORTED;\r
}\r
\r