https://bugzilla.tianocore.org/show_bug.cgi?id=849
In V2, use "mov rax, strict qword 0" to replace the hard code db.
1. Use lea instruction to get the address instead of mov instruction.
2. Use the dummy address as jmp destination, and add the logic to fix up
the address to the absolute address at boot time.
3. On MpFuncs.nasm, use ExchangeInfo to record InitializeFloatingPointUnits.
This way is same to MpInitLib.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
/** @file\r
Code for Processor S3 restoration\r
\r
/** @file\r
Code for Processor S3 restoration\r
\r
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
#include "PiSmmCpuDxeSmm.h"\r
\r
\r
#include "PiSmmCpuDxeSmm.h"\r
\r
typedef struct {\r
UINTN Lock;\r
VOID *StackStart;\r
typedef struct {\r
UINTN Lock;\r
VOID *StackStart;\r
IA32_DESCRIPTOR IdtrProfile;\r
UINT32 BufferStart;\r
UINT32 Cr3;\r
IA32_DESCRIPTOR IdtrProfile;\r
UINT32 BufferStart;\r
UINT32 Cr3;\r
+ UINTN InitializeFloatingPointUnitsAddress;\r
} MP_CPU_EXCHANGE_INFO;\r
} MP_CPU_EXCHANGE_INFO;\r
\r
typedef struct {\r
UINT8 *RendezvousFunnelAddress;\r
\r
typedef struct {\r
UINT8 *RendezvousFunnelAddress;\r
mExchangeInfo->StackSize = mAcpiCpuData.StackSize;\r
mExchangeInfo->BufferStart = (UINT32) StartupVector;\r
mExchangeInfo->Cr3 = (UINT32) (AsmReadCr3 ());\r
mExchangeInfo->StackSize = mAcpiCpuData.StackSize;\r
mExchangeInfo->BufferStart = (UINT32) StartupVector;\r
mExchangeInfo->Cr3 = (UINT32) (AsmReadCr3 ());\r
+ mExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits;\r
;------------------------------------------------------------------------------ ;\r
;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
\r
ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint\r
\r
\r
ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint\r
\r
+global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)\r
+ASM_PFX(PiSmmCpuSmiEntryFixupAddress):\r
+ ret\r
;------------------------------------------------------------------------------ ;\r
;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
mov byte [eax], 1\r
pop eax\r
jmp [ASM_PFX(mSmmRelocationOriginalAddress)]\r
mov byte [eax], 1\r
pop eax\r
jmp [ASM_PFX(mSmmRelocationOriginalAddress)]\r
+\r
+global ASM_PFX(PiSmmCpuSmmInitFixupAddress)\r
+ASM_PFX(PiSmmCpuSmmInitFixupAddress):\r
+ ret\r
/** @file\r
Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
\r
/** @file\r
Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
\r
-Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
UINTN ModelId;\r
UINT32 Cr3;\r
\r
UINTN ModelId;\r
UINT32 Cr3;\r
\r
+ //\r
+ // Initialize address fixup\r
+ //\r
+ PiSmmCpuSmmInitFixupAddress ();\r
+ PiSmmCpuSmiEntryFixupAddress ();\r
+\r
//\r
// Initialize Debug Agent to support source level debug in SMM code\r
//\r
//\r
// Initialize Debug Agent to support source level debug in SMM code\r
//\r
IN UINT64 *Attributes\r
);\r
\r
IN UINT64 *Attributes\r
);\r
\r
+/**\r
+ This function fixes up the address of the global variable or function\r
+ referred in SmmInit assembly files to be the absoute address.\r
+**/\r
+VOID\r
+EFIAPI\r
+PiSmmCpuSmmInitFixupAddress (\r
+ );\r
+\r
+/**\r
+ This function fixes up the address of the global variable or function\r
+ referred in SmiEntry assembly files to be the absoute address.\r
+**/\r
+VOID\r
+EFIAPI\r
+PiSmmCpuSmiEntryFixupAddress (\r
+ );\r
+\r
;------------------------------------------------------------------------------ ;\r
;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
;\r
;-------------------------------------------------------------------------------\r
\r
;\r
;-------------------------------------------------------------------------------\r
\r
-extern ASM_PFX(InitializeFloatingPointUnits)\r
-\r
%define VacantFlag 0x0\r
%define NotVacantFlag 0xff\r
\r
%define VacantFlag 0x0\r
%define NotVacantFlag 0xff\r
\r
%define IdtrLocation LockLocation + 0x2A\r
%define BufferStartLocation LockLocation + 0x34\r
%define Cr3OffsetLocation LockLocation + 0x38\r
%define IdtrLocation LockLocation + 0x2A\r
%define BufferStartLocation LockLocation + 0x34\r
%define Cr3OffsetLocation LockLocation + 0x38\r
+%define InitializeFloatingPointUnitsAddress LockLocation + 0x3C\r
\r
;-------------------------------------------------------------------------------------\r
;RendezvousFunnelProc procedure follows. All APs execute their procedure. This\r
\r
;-------------------------------------------------------------------------------------\r
;RendezvousFunnelProc procedure follows. All APs execute their procedure. This\r
;\r
; Call assembly function to initialize FPU.\r
;\r
;\r
; Call assembly function to initialize FPU.\r
;\r
- mov rax, ASM_PFX(InitializeFloatingPointUnits)\r
+ mov rax, qword [esi + InitializeFloatingPointUnitsAddress]\r
sub rsp, 0x20\r
call rax\r
add rsp, 0x20\r
sub rsp, 0x20\r
call rax\r
add rsp, 0x20\r
; comments here for definition of address map\r
global ASM_PFX(AsmGetAddressMap)\r
ASM_PFX(AsmGetAddressMap):\r
; comments here for definition of address map\r
global ASM_PFX(AsmGetAddressMap)\r
ASM_PFX(AsmGetAddressMap):\r
- mov rax, RendezvousFunnelProcStart\r
+ lea rax, [RendezvousFunnelProcStart]\r
mov qword [rcx], rax\r
mov qword [rcx+0x8], PMODE_ENTRY - RendezvousFunnelProcStart\r
mov qword [rcx+0x10], FLAT32_JUMP - RendezvousFunnelProcStart\r
mov qword [rcx], rax\r
mov qword [rcx+0x8], PMODE_ENTRY - RendezvousFunnelProcStart\r
mov qword [rcx+0x10], FLAT32_JUMP - RendezvousFunnelProcStart\r
;------------------------------------------------------------------------------ ;\r
;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
mov cr0, rbx\r
retf\r
@LongMode: ; long mode (64-bit code) starts here\r
mov cr0, rbx\r
retf\r
@LongMode: ; long mode (64-bit code) starts here\r
- mov rax, ASM_PFX(gSmiHandlerIdtr)\r
+ mov rax, strict qword 0 ; mov rax, ASM_PFX(gSmiHandlerIdtr)\r
+SmiHandlerIdtrAbsAddr:\r
lidt [rax]\r
lea ebx, [rdi + DSC_OFFSET]\r
mov ax, [rbx + DSC_DS]\r
lidt [rax]\r
lea ebx, [rdi + DSC_OFFSET]\r
mov ax, [rbx + DSC_DS]\r
mov gs, eax\r
mov ax, [rbx + DSC_SS]\r
mov ss, eax\r
mov gs, eax\r
mov ax, [rbx + DSC_SS]\r
mov ss, eax\r
-; jmp _SmiHandler ; instruction is not needed\r
+ mov rax, strict qword 0 ; mov rax, _SmiHandler\r
+_SmiHandlerAbsAddr:\r
+ jmp rax\r
\r
_SmiHandler:\r
mov rbx, [rsp + 0x8] ; rcx <- CpuIndex\r
\r
_SmiHandler:\r
mov rbx, [rsp + 0x8] ; rcx <- CpuIndex\r
add rsp, -0x20\r
\r
mov rcx, rbx\r
add rsp, -0x20\r
\r
mov rcx, rbx\r
- mov rax, ASM_PFX(CpuSmmDebugEntry)\r
- call rax\r
+ call ASM_PFX(CpuSmmDebugEntry)\r
- mov rax, ASM_PFX(SmiRendezvous) ; rax <- absolute addr of SmiRedezvous\r
- call rax\r
+ call ASM_PFX(SmiRendezvous)\r
- mov rax, ASM_PFX(CpuSmmDebugExit)\r
- call rax\r
+ call ASM_PFX(CpuSmmDebugExit)\r
- mov rax, ASM_PFX(mXdSupported)\r
+ lea rax, [ASM_PFX(mXdSupported)]\r
mov al, [rax]\r
cmp al, 0\r
jz .1\r
mov al, [rax]\r
cmp al, 0\r
jz .1\r
\r
ASM_PFX(gcSmiHandlerSize) DW $ - _SmiEntryPoint\r
\r
\r
ASM_PFX(gcSmiHandlerSize) DW $ - _SmiEntryPoint\r
\r
+global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)\r
+ASM_PFX(PiSmmCpuSmiEntryFixupAddress):\r
+ lea rax, [ASM_PFX(gSmiHandlerIdtr)]\r
+ lea rcx, [SmiHandlerIdtrAbsAddr]\r
+ mov qword [rcx - 8], rax\r
+\r
+ lea rax, [_SmiHandler]\r
+ lea rcx, [_SmiHandlerAbsAddr]\r
+ mov qword [rcx - 8], rax\r
+ ret\r
;------------------------------------------------------------------------------ ;\r
;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
\r
;; call into exception handler\r
mov rcx, [rbp + 8]\r
\r
;; call into exception handler\r
mov rcx, [rbp + 8]\r
- mov rax, ASM_PFX(SmiPFHandler)\r
+ lea rax, [ASM_PFX(SmiPFHandler)]\r
\r
;; Prepare parameter and call\r
mov rdx, rsp\r
\r
;; Prepare parameter and call\r
mov rdx, rsp\r
;------------------------------------------------------------------------------ ;\r
;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
ASM_PFX(gSmmCr0): DD 0\r
mov cr0, rax ; enable protected mode & paging\r
DB 0x66, 0xea ; far jmp to long mode\r
ASM_PFX(gSmmCr0): DD 0\r
mov cr0, rax ; enable protected mode & paging\r
DB 0x66, 0xea ; far jmp to long mode\r
-ASM_PFX(gSmmJmpAddr): DQ @LongMode\r
+ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode\r
@LongMode: ; long-mode starts here\r
DB 0x48, 0xbc ; mov rsp, imm64\r
ASM_PFX(gSmmInitStack): DQ 0\r
@LongMode: ; long-mode starts here\r
DB 0x48, 0xbc ; mov rsp, imm64\r
ASM_PFX(gSmmInitStack): DQ 0\r
sub ebp, 0x30000\r
jmp ebp\r
@L1:\r
sub ebp, 0x30000\r
jmp ebp\r
@L1:\r
- DQ ASM_PFX(SmmStartup)\r
+ DQ 0; ASM_PFX(SmmStartup)\r
\r
ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)\r
\r
\r
ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)\r
\r
;\r
db 0xff, 0x25\r
ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0\r
;\r
db 0xff, 0x25\r
ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0\r
+\r
+global ASM_PFX(PiSmmCpuSmmInitFixupAddress)\r
+ASM_PFX(PiSmmCpuSmmInitFixupAddress):\r
+ lea rax, [@LongMode]\r
+ lea rcx, [ASM_PFX(gSmmJmpAddr)]\r
+ mov qword [rcx], rax\r
+\r
+ lea rax, [ASM_PFX(SmmStartup)]\r
+ lea rcx, [@L1]\r
+ mov qword [rcx], rax\r
+ ret\r