UefiCpuPkg: Update PiSmmCpuDxeSmm pass XCODE5 tool chain

https://bugzilla.tianocore.org/show_bug.cgi?id=849

In V2, use "mov rax, strict qword 0" to replace the hard code db.

1. Use lea instruction to get the address instead of mov instruction.
2. Use the dummy address as jmp destination, and add the logic to fix up
the address to the absolute address at boot time.
3. On MpFuncs.nasm, use ExchangeInfo to record InitializeFloatingPointUnits.
This way is same to MpInitLib.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 94e5ab2c0ee22398fb846ac720ada8a3535be9e4..554629536a5db5da465f24397289b30dd1a346b6 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -1,7 +1,7 @@
 /** @file\r
 Code for Processor S3 restoration\r
 \r
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -14,6 +14,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 \r
 #include "PiSmmCpuDxeSmm.h"\r
 \r
+#pragma pack(1)\r
 typedef struct {\r
   UINTN             Lock;\r
   VOID              *StackStart;\r
@@ -23,7 +24,9 @@ typedef struct {
   IA32_DESCRIPTOR   IdtrProfile;\r
   UINT32            BufferStart;\r
   UINT32            Cr3;\r
+  UINTN             InitializeFloatingPointUnitsAddress;\r
 } MP_CPU_EXCHANGE_INFO;\r
+#pragma pack()\r
 \r
 typedef struct {\r
   UINT8 *RendezvousFunnelAddress;\r
@@ -456,6 +459,7 @@ PrepareApStartupVector (
   mExchangeInfo->StackSize   = mAcpiCpuData.StackSize;\r
   mExchangeInfo->BufferStart = (UINT32) StartupVector;\r
   mExchangeInfo->Cr3         = (UINT32) (AsmReadCr3 ());\r
+  mExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits;\r
 }\r
 \r
 /**\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
index 4d2383ff972e1d262838c0177248648b3dc80025..a8324a7f4a841e964c41be2dc2ad9cb9a4d6467f 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -207,3 +207,6 @@ ASM_PFX(SmiHandler):
 \r
 ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint\r
 \r
+global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)\r
+ASM_PFX(PiSmmCpuSmiEntryFixupAddress):\r
+    ret\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
index d9df3626c7545165b946c3acf90bafe8f4db95ec..a5c62e77ce5e0204989ad4e05f44f5dae282b07d 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -85,3 +85,7 @@ ASM_PFX(SmmRelocationSemaphoreComplete):
     mov     byte [eax], 1\r
     pop     eax\r
     jmp     [ASM_PFX(mSmmRelocationOriginalAddress)]\r
+\r
+global ASM_PFX(PiSmmCpuSmmInitFixupAddress)\r
+ASM_PFX(PiSmmCpuSmmInitFixupAddress):\r
+    ret\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 4b66a0dfd931eef8083e4f33054c24c53ff02af3..a27d1f4684f5cc0e0d2b601544cba445d5469714 100755 (executable)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -1,7 +1,7 @@
 /** @file\r
 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
 \r
-Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
 \r
 This program and the accompanying materials\r
@@ -542,6 +542,12 @@ PiCpuSmmEntry (
   UINTN                      ModelId;\r
   UINT32                     Cr3;\r
 \r
+  //\r
+  // Initialize address fixup\r
+  //\r
+  PiSmmCpuSmmInitFixupAddress ();\r
+  PiSmmCpuSmiEntryFixupAddress ();\r
+\r
   //\r
   // Initialize Debug Agent to support source level debug in SMM code\r
   //\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index cbaa513244d5a78d7a3b6b87c7115ab691001c4d..a2babb987732ea15b5a712d19b0852cbe510e6ee 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -1158,4 +1158,22 @@ EdkiiSmmGetMemoryAttributes (
   IN  UINT64                                *Attributes\r
   );\r
 \r
+/**\r
+  This function fixes up the address of the global variable or function\r
+  referred in SmmInit assembly files to be the absoute address.\r
+**/\r
+VOID\r
+EFIAPI\r
+PiSmmCpuSmmInitFixupAddress (\r
+ );\r
+\r
+/**\r
+  This function fixes up the address of the global variable or function\r
+  referred in SmiEntry assembly files to be the absoute address.\r
+**/\r
+VOID\r
+EFIAPI\r
+PiSmmCpuSmiEntryFixupAddress (\r
+ );\r
+\r
 #endif\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm
index 702233d6e49d14b1ab074d66ea7512915eb25f35..704942ec276b2c86d1c372de14c960de9326597b 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -18,8 +18,6 @@
 ;\r
 ;-------------------------------------------------------------------------------\r
 \r
-extern ASM_PFX(InitializeFloatingPointUnits)\r
-\r
 %define VacantFlag 0x0\r
 %define NotVacantFlag 0xff\r
 \r
@@ -31,6 +29,7 @@ extern ASM_PFX(InitializeFloatingPointUnits)
 %define IdtrLocation LockLocation + 0x2A\r
 %define BufferStartLocation LockLocation + 0x34\r
 %define Cr3OffsetLocation LockLocation + 0x38\r
+%define InitializeFloatingPointUnitsAddress LockLocation + 0x3C\r
 \r
 ;-------------------------------------------------------------------------------------\r
 ;RendezvousFunnelProc  procedure follows. All APs execute their procedure. This\r
@@ -153,7 +152,7 @@ Releaselock:
         ;\r
         ; Call assembly function to initialize FPU.\r
         ;\r
-        mov         rax, ASM_PFX(InitializeFloatingPointUnits)\r
+        mov         rax, qword [esi + InitializeFloatingPointUnitsAddress]\r
         sub         rsp, 0x20\r
         call        rax\r
         add         rsp, 0x20\r
@@ -185,7 +184,7 @@ RendezvousFunnelProcEnd:
 ; comments here for definition of address map\r
 global ASM_PFX(AsmGetAddressMap)\r
 ASM_PFX(AsmGetAddressMap):\r
-        mov         rax, RendezvousFunnelProcStart\r
+        lea         rax, [RendezvousFunnelProcStart]\r
         mov         qword [rcx], rax\r
         mov         qword [rcx+0x8], PMODE_ENTRY - RendezvousFunnelProcStart\r
         mov         qword [rcx+0x10], FLAT32_JUMP - RendezvousFunnelProcStart\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index dc56dc7852e278c90c72c89dde3b82e53c266214..697fd2bec7c616c8d1fd855dd3afccf4f846afcb 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -158,7 +158,8 @@ Base:
     mov     cr0, rbx\r
     retf\r
 @LongMode:                              ; long mode (64-bit code) starts here\r
-    mov     rax, ASM_PFX(gSmiHandlerIdtr)\r
+    mov     rax, strict qword 0         ;  mov     rax, ASM_PFX(gSmiHandlerIdtr)\r
+SmiHandlerIdtrAbsAddr:\r
     lidt    [rax]\r
     lea     ebx, [rdi + DSC_OFFSET]\r
     mov     ax, [rbx + DSC_DS]\r
@@ -169,7 +170,9 @@ Base:
     mov     gs, eax\r
     mov     ax, [rbx + DSC_SS]\r
     mov     ss, eax\r
-;   jmp     _SmiHandler                 ; instruction is not needed\r
+    mov     rax, strict qword 0         ;   mov     rax, _SmiHandler\r
+_SmiHandlerAbsAddr:\r
+    jmp     rax\r
 \r
 _SmiHandler:\r
     mov     rbx, [rsp + 0x8]             ; rcx <- CpuIndex\r
@@ -184,16 +187,13 @@ _SmiHandler:
     add     rsp, -0x20\r
 \r
     mov     rcx, rbx\r
-    mov     rax, ASM_PFX(CpuSmmDebugEntry)\r
-    call    rax\r
+    call    ASM_PFX(CpuSmmDebugEntry)\r
 \r
     mov     rcx, rbx\r
-    mov     rax, ASM_PFX(SmiRendezvous)  ; rax <- absolute addr of SmiRedezvous\r
-    call    rax\r
+    call    ASM_PFX(SmiRendezvous)\r
 \r
     mov     rcx, rbx\r
-    mov     rax, ASM_PFX(CpuSmmDebugExit)\r
-    call    rax\r
+    call    ASM_PFX(CpuSmmDebugExit)\r
 \r
     add     rsp, 0x20\r
 \r
@@ -205,7 +205,7 @@ _SmiHandler:
 \r
     add     rsp, 0x200\r
 \r
-    mov     rax, ASM_PFX(mXdSupported)\r
+    lea     rax, [ASM_PFX(mXdSupported)]\r
     mov     al, [rax]\r
     cmp     al, 0\r
     jz      .1\r
@@ -222,3 +222,13 @@ _SmiHandler:
 \r
 ASM_PFX(gcSmiHandlerSize)    DW      $ - _SmiEntryPoint\r
 \r
+global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)\r
+ASM_PFX(PiSmmCpuSmiEntryFixupAddress):\r
+    lea    rax, [ASM_PFX(gSmiHandlerIdtr)]\r
+    lea    rcx, [SmiHandlerIdtrAbsAddr]\r
+    mov    qword [rcx - 8], rax\r
+\r
+    lea    rax, [_SmiHandler]\r
+    lea    rcx, [_SmiHandlerAbsAddr]\r
+    mov    qword [rcx - 8], rax\r
+    ret\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm
index b2e2e6dee6021f304f48837a05170303e4c4dd51..a8a9af300869a49789c1a435bc81a4315d510de2 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -289,7 +289,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile):
 \r
 ;; call into exception handler\r
     mov     rcx, [rbp + 8]\r
-    mov     rax, ASM_PFX(SmiPFHandler)\r
+    lea     rax, [ASM_PFX(SmiPFHandler)]\r
 \r
 ;; Prepare parameter and call\r
     mov     rdx, rsp\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index 9d05e2cb0582b3fd648fcea066d0a85654dc8c83..2701689c3de4afa75fbac1a107a557bc974d7339 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -60,7 +60,7 @@ ASM_PFX(gSmmCr4): DD 0
 ASM_PFX(gSmmCr0): DD 0\r
     mov     cr0, rax                    ; enable protected mode & paging\r
     DB      0x66, 0xea                   ; far jmp to long mode\r
-ASM_PFX(gSmmJmpAddr): DQ @LongMode\r
+ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode\r
 @LongMode:                              ; long-mode starts here\r
     DB      0x48, 0xbc                   ; mov rsp, imm64\r
 ASM_PFX(gSmmInitStack): DQ 0\r
@@ -99,7 +99,7 @@ ASM_PFX(gcSmmInitTemplate):
     sub ebp, 0x30000\r
     jmp ebp\r
 @L1:\r
-    DQ      ASM_PFX(SmmStartup)\r
+    DQ     0; ASM_PFX(SmmStartup)\r
 \r
 ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)\r
 \r
@@ -128,3 +128,14 @@ ASM_PFX(mRebasedFlagAddr32): dd 0
     ;\r
     db      0xff, 0x25\r
 ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0\r
+\r
+global ASM_PFX(PiSmmCpuSmmInitFixupAddress)\r
+ASM_PFX(PiSmmCpuSmmInitFixupAddress):\r
+    lea    rax, [@LongMode]\r
+    lea    rcx, [ASM_PFX(gSmmJmpAddr)]\r
+    mov    qword [rcx], rax\r
+\r
+    lea    rax, [ASM_PFX(SmmStartup)]\r
+    lea    rcx, [@L1]\r
+    mov    qword [rcx], rax\r
+    ret\r