OvmfPkg: Q35: Use correct ACPI PM control register:bit

On PIIX4, function 3, the PMREGMISC register at offset 0x80, with
default value 0x00 has its bit 0 (PMIOSE) indicate whether the PM
IO space given in the PMBA register (offset 0x40) is enabled.
PMBA must be configured *before* setting this bit.

On Q35/ICH9+, function 0x1f, the equivalent role is fulfilled by
bit 7 (ACPI_EN) in the ACPI Control Register (ACPI_CNTL) at offset
0x44, also with a default value of 0x00.

Currently, OVMF hangs when Q35 reboots, because while PMBA is reset
by QEMU, the register at offset 0x80 (matching PMREGMISC on PIIX4)
is not reset, since it has a completely different meaning on LPC.
As such, the power management initialization logic in OVMF finds
the "PMIOSE" bit enabled after a reboot and decides to skip setting
PMBA. This causes the ACPI timer tick routine to read a constant
value from the wrong register, which in turn causes the ACPI delay
loop to hang indefinitely.

This patch modifies the Base[Rom]AcpiTimerLib constructors and the
PlatformPei ACPI PM init routines to use ACPI_CNTL:ACPI_EN instead
of PMREGMISC:PMIOSE when running on Q35.

Reported-by: Reza Jelveh <reza.jelveh@tuhh.de>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17076 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
index 28280539b683cae4ec54902c7c34811f2dfa6ac9..58938b5d8bb8647eb9410c79fdcca9cd708015cf 100644 (file)
--- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
@@ -21,8 +21,9 @@
 //\r
 // Power Management PCI Configuration Register fields\r
 //\r
-#define PMBA_RTE  BIT0\r
-#define PMIOSE    BIT0\r
+#define PMBA_RTE      BIT0\r
+#define PIIX4_PMIOSE  BIT0\r
+#define Q35_ACPI_EN   BIT7\r
 \r
 //\r
 // Offset in the Power Management Base Address to the ACPI Timer\r
@@ -49,7 +50,8 @@ AcpiTimerLibConstructor (
 {\r
   UINT16 HostBridgeDevId;\r
   UINTN Pmba;\r
-  UINTN PmRegMisc;\r
+  UINTN AcpiCtlReg;\r
+  UINT8 AcpiEnBit;\r
 \r
   //\r
   // Query Host Bridge DID to determine platform type\r
@@ -57,12 +59,14 @@ AcpiTimerLibConstructor (
   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r
-      Pmba      = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
-      PmRegMisc = POWER_MGMT_REGISTER_PIIX4 (0x80);\r
+      Pmba       = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
+      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC\r
+      AcpiEnBit  = PIIX4_PMIOSE;\r
       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
-      Pmba      = POWER_MGMT_REGISTER_Q35 (0x40);\r
-      PmRegMisc = POWER_MGMT_REGISTER_Q35 (0x80);\r
+      Pmba       = POWER_MGMT_REGISTER_Q35 (0x40);\r
+      AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (0x44); // ACPI_CNTL\r
+      AcpiEnBit  = Q35_ACPI_EN;\r
       break;\r
     default:\r
       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
@@ -76,7 +80,7 @@ AcpiTimerLibConstructor (
   //\r
   // Check to see if the Power Management Base Address is already enabled\r
   //\r
-  if ((PciRead8 (PmRegMisc) & PMIOSE) == 0) {\r
+  if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
     //\r
     // If the Power Management Base Address is not programmed,\r
     // then program the Power Management Base Address from a PCD.\r
@@ -84,9 +88,9 @@ AcpiTimerLibConstructor (
     PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
 \r
     //\r
-    // Enable PMBA I/O port decodes in PMREGMISC\r
+    // Enable PMBA I/O port decodes\r
     //\r
-    PciOr8 (PmRegMisc, PMIOSE);\r
+    PciOr8 (AcpiCtlReg, AcpiEnBit);\r
   }\r
 \r
   return RETURN_SUCCESS;\r

diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
index 05b14d724668e617d8a70834459577c556175c16..c9601d8e97819256a07a42530bc427350a42c1b7 100644 (file)
--- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
@@ -22,8 +22,9 @@
 //\r
 // Power Management PCI Configuration Register fields\r
 //\r
-#define PMBA_RTE  BIT0\r
-#define PMIOSE    BIT0\r
+#define PMBA_RTE      BIT0\r
+#define PIIX4_PMIOSE  BIT0\r
+#define Q35_ACPI_EN   BIT7\r
 \r
 //\r
 // Offset in the Power Management Base Address to the ACPI Timer\r
@@ -47,7 +48,8 @@ AcpiTimerLibConstructor (
 {\r
   UINT16 HostBridgeDevId;\r
   UINTN Pmba;\r
-  UINTN PmRegMisc;\r
+  UINTN AcpiCtlReg;\r
+  UINT8 AcpiEnBit;\r
 \r
   //\r
   // Query Host Bridge DID to determine platform type\r
@@ -55,12 +57,14 @@ AcpiTimerLibConstructor (
   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r
-      Pmba      = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
-      PmRegMisc = POWER_MGMT_REGISTER_PIIX4 (0x80);\r
+      Pmba       = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
+      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC\r
+      AcpiEnBit  = PIIX4_PMIOSE;\r
       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
-      Pmba      = POWER_MGMT_REGISTER_Q35 (0x40);\r
-      PmRegMisc = POWER_MGMT_REGISTER_Q35 (0x80);\r
+      Pmba       = POWER_MGMT_REGISTER_Q35 (0x40);\r
+      AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (0x44); // ACPI_CNTL\r
+      AcpiEnBit  = Q35_ACPI_EN;\r
       break;\r
     default:\r
       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
@@ -72,7 +76,7 @@ AcpiTimerLibConstructor (
   //\r
   // Check to see if the Power Management Base Address is already enabled\r
   //\r
-  if ((PciRead8 (PmRegMisc) & PMIOSE) == 0) {\r
+  if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
     //\r
     // If the Power Management Base Address is not programmed,\r
     // then program the Power Management Base Address from a PCD.\r
@@ -80,9 +84,9 @@ AcpiTimerLibConstructor (
     PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
 \r
     //\r
-    // Enable PMBA I/O port decodes in PMREGMISC\r
+    // Enable PMBA I/O port decodes\r
     //\r
-    PciOr8 (PmRegMisc, PMIOSE);\r
+    PciOr8 (AcpiCtlReg, AcpiEnBit);\r
   }\r
 \r
   return RETURN_SUCCESS;\r

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 1940e01640fd177aa5646ed7b7ed07e96fd11c73..5ce0a9099a4a0cf7c79a651f202268e0c99f1adb 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -232,7 +232,8 @@ MiscInitialization (
   UINT16 HostBridgeDevId;\r
   UINTN  PmCmd;\r
   UINTN  Pmba;\r
-  UINTN  PmRegMisc;\r
+  UINTN  AcpiCtlReg;\r
+  UINT8  AcpiEnBit;\r
 \r
   //\r
   // Disable A20 Mask\r
@@ -250,14 +251,16 @@ MiscInitialization (
   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r
-      PmCmd     = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
-      Pmba      = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
-      PmRegMisc = POWER_MGMT_REGISTER_PIIX4 (0x80);\r
+      PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
+      Pmba       = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
+      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC\r
+      AcpiEnBit  = BIT0; // PIIX4_PMIOSE\r
       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
-      PmCmd     = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
-      Pmba      = POWER_MGMT_REGISTER_Q35 (0x40);\r
-      PmRegMisc = POWER_MGMT_REGISTER_Q35 (0x80);\r
+      PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
+      Pmba       = POWER_MGMT_REGISTER_Q35 (0x40);\r
+      AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (0x44); // ACPI_CNTL\r
+      AcpiEnBit  = BIT7; // Q35_ACPI_EN\r
       break;\r
     default:\r
       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
@@ -268,13 +271,13 @@ MiscInitialization (
   PcdSet16 (PcdOvmfHostBridgePciDevId, HostBridgeDevId);\r
 \r
   //\r
-  // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for\r
-  // example by Xen) and skip the setup here. This matches the logic in\r
-  // AcpiTimerLibConstructor ().\r
+  // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
+  // has been configured (e.g., by Xen) and skip the setup here.\r
+  // This matches the logic in AcpiTimerLibConstructor ().\r
   //\r
-  if ((PciRead8 (PmRegMisc) & 0x01) == 0) {\r
+  if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
     //\r
-    // The PEI phase should be exited with fully accessibe PIIX4 IO space:\r
+    // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
     // 1. set PMBA\r
     //\r
     PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
@@ -285,9 +288,9 @@ MiscInitialization (
     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
 \r
     //\r
-    // 3. set PMREGMISC/PMIOSE\r
+    // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
     //\r
-    PciOr8 (PmRegMisc, 0x01);\r
+    PciOr8 (AcpiCtlReg, AcpiEnBit);\r
   }\r
 }\r
 \r