MdePkg: Add PCI Express 5.0 Header File

The header includes Physical Layer PCI Express Extended Capability
definitions based on section 7.7.6 of PCI Express Base Specification 5.0.

Signed-off-by: Felix Polyudov <felixp@ami.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

diff --git a/MdePkg/Include/IndustryStandard/PciExpress50.h b/MdePkg/Include/IndustryStandard/PciExpress50.h
new file mode 100644 (file)
index 0000000..26eae0b
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/PciExpress50.h
@@ -0,0 +1,136 @@
+/** @file\r
+Support for the PCI Express 5.0 standard.\r
+\r
+This header file may not define all structures.  Please extend as required.\r
+\r
+Copyright (c) 2020, American Megatrends International LLC. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef _PCIEXPRESS50_H_\r
+#define _PCIEXPRESS50_H_\r
+\r
+#include <IndustryStandard/PciExpress40.h>\r
+\r
+#pragma pack(1)\r
+\r
+/// The Physical Layer PCI Express Extended Capability definitions.\r
+///\r
+/// Based on section 7.7.6 of PCI Express Base Specification 5.0.\r
+///@{\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_ID    0x002A\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1  0x1\r
+\r
+// Register offsets from Physical Layer PCI-E Ext Cap Header\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET                         0x04\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET                              0x08\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET                               0x0C\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET               0x10\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET               0x14\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSET              0x18\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSET              0x1C\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFFSET            0x20\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 EqualizationByPassToHighestRateSupport                  : 1; // bit 0\r
+    UINT32 NoEqualizationNeededSupport                             : 1; // bit 1\r
+    UINT32 Reserved1                                               : 6; // Reserved bit 2:7\r
+    UINT32 ModifiedTSUsageMode0Support                             : 1; // bit 8\r
+    UINT32 ModifiedTSUsageMode1Support                             : 1; // bit 9\r
+    UINT32 ModifiedTSUsageMode2Support                             : 1; // bit 10\r
+    UINT32 ModifiedTSReservedUsageModes                            : 5; // bit 11:15\r
+    UINT32 Reserved2                                               : 16; // Reserved bit 16:31\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 EqualizationByPassToHighestRateDisable                  : 1; // bit 0\r
+    UINT32 NoEqualizationNeededDisable                             : 1; // bit 1\r
+    UINT32 Reserved1                                               : 6; // Reserved bit 2:7\r
+    UINT32 ModifiedTSUsageModeSelected                             : 3; // bit 8:10\r
+    UINT32 Reserved2                                               : 21; // Reserved bit 11:31\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 EqualizationComplete      : 1; // bit 0\r
+    UINT32 EqualizationPhase1Success : 1; // bit 1\r
+    UINT32 EqualizationPhase2Success : 1; // bit 2\r
+    UINT32 EqualizationPhase3Success : 1; // bit 3\r
+    UINT32 LinkEqualizationRequest   : 1; // bit 4\r
+    UINT32 ModifiedTSRcvd            : 1; // bit 5\r
+    UINT32 RcvdEnhancedLinkControl   : 2; // bit 6:7\r
+    UINT32 TransmitterPrecodingOn    : 1; // bit 8\r
+    UINT32 TransmitterPrecodeRequest : 1; // bit 9\r
+    UINT32 NoEqualizationNeededRcvd  : 1; // bit 10\r
+    UINT32 Reserved                  : 21; // Reserved bit 11:31\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 RcvdModifiedTSUsageMode   : 3; // bit 0:2\r
+    UINT32 RcvdModifiedTSUsageInfo1  : 13; // bit 3:15\r
+    UINT32 RcvdModifiedTSVendorId    : 16; // bit 16:31\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 RcvdModifiedTSUsageInfo2     : 24; // bit 0:23\r
+    UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25\r
+    UINT32 Reserved                     : 6; // Reserved bit 26:31\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 TransModifiedTSUsageMode   : 3; // bit 0:2\r
+    UINT32 TransModifiedTSUsageInfo1  : 13; // bit 3:15\r
+    UINT32 TransModifiedTSVendorId    : 16; // bit 16:31\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT32 TransModifiedTSUsageInfo2    : 24; // bit 0:23\r
+    UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25\r
+    UINT32 Reserved                     : 6; // Reserved bit 26:31\r
+  } Bits;\r
+  UINT32   Uint32;\r
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2;\r
+\r
+typedef union {\r
+  struct {\r
+    UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3\r
+    UINT8 UpstreamPortTransmitterPreset   : 4; //bit 4..7\r
+  } Bits;\r
+  UINT8   Uint8;\r
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL;\r
+\r
+typedef struct {\r
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                      Header;\r
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES              Capablities;\r
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL                   Control;\r
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS                    Status;\r
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1    RcvdModifiedTs1Data;\r
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2    RcvdModifiedTs2Data;\r
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1   TransModifiedTs1Data;\r
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2   TransModifiedTs2Data;\r
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];\r
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0;\r
+///@}\r
+\r
+#pragma pack()\r
+\r
+#endif\r