ArmPlatformPkg: introduce PCDs for describing PCI address spaces

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16893 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec
index 57a43c503758b3667b67f58713d25fb2aa53044a..2515af8e5918486d014d13f3c7c3fba2fbb5510b 100644 (file)
--- a/ArmPlatformPkg/ArmPlatformPkg.dec
+++ b/ArmPlatformPkg/ArmPlatformPkg.dec
@@ -152,6 +152,68 @@
   gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r
   gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022\r
 \r
+  #\r
+  # Inclusive range of allowed PCI buses.\r
+  #\r
+  gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E\r
+  gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F\r
+\r
+  #\r
+  # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
+  # Note that "IO" is just another MMIO range that simulates IO space; there\r
+  # are no special instructions to access it.\r
+  #\r
+  # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
+  # specific to their containing address spaces. In order to get the physical\r
+  # address for the CPU, for a given access, the respective translation value\r
+  # has to be added.\r
+  #\r
+  # The translations always have to be initialized like this, using UINT64:\r
+  #\r
+  #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space\r
+  #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
+  #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
+  #\r
+  #   PcdPciIoTranslation     = IoCpuBase     - PcdPciIoBase;\r
+  #   PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
+  #   PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
+  #\r
+  # because (a) the target address space (ie. the cpu-physical space) is\r
+  # 64-bit, and (b) the translation values are meant as offsets for *modular*\r
+  # arithmetic.\r
+  #\r
+  # Accordingly, the translation itself needs to be implemented as:\r
+  #\r
+  #   UINT64 UntranslatedIoAddress;     // input parameter\r
+  #   UINT32 UntranslatedMmio32Address; // input parameter\r
+  #   UINT64 UntranslatedMmio64Address; // input parameter\r
+  #\r
+  #   UINT64 TranslatedIoAddress;       // output parameter\r
+  #   UINT64 TranslatedMmio32Address;   // output parameter\r
+  #   UINT64 TranslatedMmio64Address;   // output parameter\r
+  #\r
+  #   TranslatedIoAddress     = UntranslatedIoAddress +\r
+  #                             PcdPciIoTranslation;\r
+  #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
+  #                             PcdPciMmio32Translation;\r
+  #   TranslatedMmio64Address = UntranslatedMmio64Address +\r
+  #                             PcdPciMmio64Translation;\r
+  #\r
+  #  The modular arithmetic performed in UINT64 ensures that the translation\r
+  #  works correctly regardless of the relation between IoCpuBase and\r
+  #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
+  #  PcdPciMmio64Base.\r
+  #\r
+  gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040\r
+  gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041\r
+  gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042\r
+  gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043\r
+  gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044\r
+  gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045\r
+  gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046\r
+  gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047\r
+  gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048\r
+\r
 [PcdsFixedAtBuild.ARM]\r
   # Stack for CPU Cores in Secure Monitor Mode\r
   gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r